JP2011171859A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver that accurately demodulates serial data without reducing a data transmission rate and regardless of the length of a transmission medium. <P>SOLUTION: A frequency divider 32 generates a synchronization clock signal 26 to be supplied to a transmitter 21. A serial-data generating part 25 of the transmitter 21 transmits serial data 24 and a strobe signal 27 in synchronization with the synchronization clock signal 26. If detecting the start of the transmission of the serial data 24 on the basis of the strobe signal 27, a demodulation-clock-signal generating part 33 generates a demodulation clock signal 36 that has the same signal waveform as that of the synchronization clock signal 26, rises at predetermined timing within a data period of each bit of the serial data 24, and indicates timing of reading data of each bit of the serial data 24. A data demodulation part 34 sequentially reads the serial data 24 by bit in synchronization with the demodulation clock signal 36. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a receiver that receives serial data transmitted from a transmitter in clock synchronous serial data communication.

  There is a serial communication system as a system for transmitting and receiving data between apparatuses, and there is a clock signal reproducing apparatus that regenerates transmitted serial data into a clock signal (for example, see Patent Document 1). For example, in the conventional technology, in industrial and consumer electronic devices, data is transmitted between a plurality of computers using a serial communication method. In mechatronics related equipment, sensor signals and operation command signals are transmitted between the controller and the mechanism using a serial communication method.

  FIG. 3 is a block diagram showing an electrical configuration of the transmitter 1 and the receiver 2. The transmitter 1 and the receiver 2 are connected by a transmission medium that transmits an electric signal such as an electric wire, and performs clock synchronous serial communication via the transmission medium.

  The transmitter 1 is realized by a serial data generation unit 5 that converts digital data 3 composed of parallel data into serial data 4. The digital data 3 is given from a digital data generation unit realized by a microcomputer or the like. The serial data generation unit 5 provides the receiver 2 with the strobe signal 7 and the converted serial data 4 in synchronization with a synchronization clock signal (hereinafter referred to as synchronization clock signal) 6 provided from the receiver 2.

  The receiver 2 includes a clock generation unit 8 and a data demodulation unit 9. The clock generation unit 8 generates a clock signal that repeats a high voltage high level H and a low voltage low level L at a constant frequency, and supplies the generated clock signal to the serial data generation unit 5 as a synchronization clock signal 6. At the same time, the generated clock signal is supplied to the data demodulator 9 as a demodulation clock signal (hereinafter referred to as a demodulation clock signal) 10. The synchronization clock signal 6 and the demodulation clock signal 10 are generated by branching the clock signal generated by the clock generation unit 8, and thus have the same phase.

  When receiving the strobe signal 7 indicating that the transmission of the serial data 4 starts, the data demodulator 9 reads the serial data 4 bit by bit in synchronization with the demodulation clock signal 10.

  FIG. 4 is a timing chart of data transmitted and received by the transmitter 1 or the receiver 2. In FIG. 4, the horizontal axis represents time. In FIG. 4, the synchronization clock signal 6 represents a signal waveform received by the serial data generation unit 5, and the demodulation clock signal 10, the strobe signal 7, and the serial data 4 represent the signal waveforms received by the data demodulation unit 9. To express.

  Since the phase of the synchronization clock signal 6 is delayed by transmitting the transmission medium, the synchronization clock signal 6 received by the serial data generation unit 5 and the demodulation clock signal 10 received by the data demodulation unit 9 are obtained. Causes a phase difference. In FIG. 4, this phase difference is ignored on the assumption that the distance of the transmission medium is short. Similarly, the strobe signal 7 and serial data 4 transmitted by the serial data generating unit 5 and the strobe signal 7 and serial data 4 received by the data demodulating unit 9 are transmitted through a transmission medium so that the phase difference between the data is transmitted. However, this phase difference is ignored in FIG.

  The strobe signal 7 indicates that serial data 4 is not transmitted when it is at a high level H, and indicates that serial data 4 is transmitted when it is at a low level L. That is, when the strobe signal 7 falls from the high level H to the low level L, it indicates that the transmission of the serial data 4 starts. When the strobe signal 7 rises from the low level L to the high level H, the transmission of the serial data 4 ends. Represents that. The serial data generation unit 5 switches the strobe signal 7 from the high level H to the low level L or from the low level L to the high level H in synchronization with the falling of the synchronization clock signal 6 according to the transmission of the serial data 4. The serial data generation unit 5 generates and outputs data of each bit constituting the serial data 4 in synchronization with the falling edge of the synchronization clock signal 6. Therefore, the period T of the data of each bit constituting the serial data 4 is the same as the period T (hereinafter referred to as the basic period T) of the synchronization clock signal 6 and the demodulation clock signal 10. FIG. 4 shows serial data 4 when the serial data generation unit 5 transmits N + 1-bit serial data 4 from data (0) to data (N) (the symbol “N” represents a natural number). As described above, the serial data 4 has a phase delay caused by transmission through the transmission medium. Since this delay is ignored, the data constituting the serial data 4 are sequentially switched at the falling edge of the demodulation clock signal 10. .

  When the demodulation clock signal 10 is switched from the high level H to the low level L at time t1, the strobe signal 7 is switched from the high level H to the low level L in synchronization with this, and the transmission of the serial data 4 is started. . The data demodulator 9 detects the start of transmission of the serial data 4 by detecting the falling edge of the strobe signal 7.

  The demodulating clock signal 10 is switched from the low level L to the high level H at time t2, which is a half period (T / 2) of the basic period T from time t1. The data demodulator 9 reads the serial data 4 when it detects the rising edge of the demodulation clock signal 10 when the strobe signal 7 is at the low level L, that is, when the serial data 4 is being transmitted. Is read whether the data (0) constituting the high level H or low level L.

  Next, since the strobe signal 7 maintains the low level L at the fall of the demodulation clock signal 10 at time t3, it is detected that the serial data 4 is further transmitted, and the data constituting the serial data 4 is detected. However, data (0) is switched to data (1). Similarly, the data demodulator 9 reads the serial data 4 sequentially bit by bit by reading the serial data 4 in synchronization with the rising edge of the demodulation clock signal 10.

  When the strobe signal 7 is switched from the low level L to the high level H at time tX, the data demodulator 9 detects the end of transmission of the serial data 4 and ends reading of the serial data 4.

  As described above, the data demodulator 9 can read the serial data 4 in synchronization with the transmitter 1 by reading the serial data 4 in synchronization with the rising edge of the demodulation clock signal 10. In this way, the serial data 4 is transmitted from the transmitter 1 to the receiver 2.

  Further, in order to synchronize and execute data transmission / reception between the transmitter 1 and the receiver 2 without using the synchronization clock signal 6, data for synchronization is added to the digital data 3 to be transmitted. There is also a method for transmitting the serial data. For example, in the Ethernet (registered trademark) protocol, a preamble and an SFD (Start of Frame Delimiter) are provided at the head of a MAC frame to synchronize the transmitter and the receiver.

JP 2002-44063 A

  In the timing chart shown in FIG. 4, the length of the transmission medium between the transmitter 1 and the receiver 2 is short, and the phase delay caused by transmitting the transmission medium is neglected as being small. The longer the length, the greater the phase delay, and the phase delay cannot be ignored.

  Since the phase of the synchronization clock signal 6 received by the serial data generation unit 5 is transmitted through the transmission medium, a delay occurs with respect to the phase of the demodulation clock signal 10 received by the data demodulation unit 9. Since the strobe signal 7 and the serial data 4 transmitted by the serial data generation unit 5 are generated in synchronization with the synchronization clock signal 6 in which the phase delay has occurred, the demodulation clock signal 10 is generated in the same manner as the synchronization clock signal 6. A delay occurs with respect to the phase. The strobe signal 7 and serial data 4 received by the data demodulator 9 are further delayed in phase with respect to the phase of the demodulation clock signal 10 by transmitting the transmission medium. That is, the strobe signal 7 and the serial data 4 received by the data demodulator 9 have a phase delay corresponding to the case where the transmission medium reciprocates with respect to the phase of the demodulation clock signal 10 received by the data demodulator 9. For example, when a 2 Mhz clock signal is transmitted through a transmission medium at the speed of light, a half-cycle phase delay occurs at 75 meters. When transmitting a transmission medium composed of electric wires, a half-cycle phase delay occurs at a distance shorter than 75 meters. Since the data demodulator 9 reads the serial data 4 in synchronization with the demodulation clock signal 10 regardless of the length of the transmission medium, that is, the phase delay, the serial data is accurately demodulated into the digital data 3 when the phase delay increases. You may not be able to.

  FIG. 5 shows an example in which the transmitter 1 or the receiver 2 receives a delay of a quarter cycle (T / 4) in the phase of the synchronization clock signal 6 with respect to the phase of the demodulation clock signal 10. It is a timing chart of the data to perform. The strobe signal 7 and the serial data 4 are transmitted in synchronization with the synchronization clock signal 6 delayed by a quarter cycle (T / 4) phase with respect to the demodulation clock signal 10. Therefore, the strobe signal 7 and the serial data 4 received by the data demodulator 9 are delayed by a half cycle (T / 2) with respect to the demodulation clock signal 10 by transmitting the transmission medium.

  At time t1, the demodulation clock signal 10 falls, and the synchronization clock signal 6 transmitted from the receiver 2 also falls. The serial data generation unit 5 receives the falling edge of the synchronization clock signal 6 at time t2 after a quarter cycle (T / 4) from time t1 because a phase delay occurs in the synchronization clock signal 6. The serial data generation unit 5 switches the strobe signal 7 from the high level H to the low level L in synchronization with the falling of the synchronization clock signal 6 at time t2, and starts transmission of the serial data 4. The data demodulator 9 receives the falling edge of the strobe signal 7 and the start of transmission of the serial data 4 at time t3, which is a quarter cycle (T / 4) from time t2. At this time t3, the demodulation clock signal 10 rises.

  Since the data demodulator 9 simultaneously receives the rising edge of the demodulating clock signal 10 and the start of transmission of the serial data 4 at time t3, the rising edge of the demodulating clock signal 10 and each bit constituting the serial data 4 are thereafter received. Simultaneously receive data switching. That is, the data demodulator 9 receives the rising edge of the demodulation clock signal 10 at the time t4 after the basic period T from the time t3 and simultaneously receives the data (1) switched from the data (0). Further, the data demodulator 9 receives the rising edge of the demodulating clock signal 10 at time t5 after the basic period T from time t4, and simultaneously receives data (2) switched from data (1). As described above, the data demodulator 9 reads the serial data 4 in synchronization with the rise of the demodulation clock signal 10 when the strobe signal 7 is at the low level L, so that the data of each bit constituting the serial data 4 is switched. Sometimes serial data 4 is read. When the serial data 4 is switched from the low level L to the high level H or from the high level H to the low level L, the serial data 4 is switched from the low level L to the high level H or from the high level H to the low level L. Since a predetermined time is required for stabilization, the serial data 4 is not stable at either the high level H or the low level L at the time when the data of each bit constituting the serial data 4 is switched. As described above, the data demodulator 9 reads the serial data 4 at the time when the serial data 4 is in an unstable state of the low level L or the high level H. Therefore, the data demodulator 9 reads the serial data 4 accurately. The serial data 4 cannot be accurately demodulated into the digital data 3 composed of parallel data.

  In order to compensate for such a phase delay, it is conceivable to adjust the timing at which the serial data 4 is read with respect to the demodulation clock signal 10 by reversely calculating the phase delay based on the length of the transmission medium. In this case, it is necessary to adjust the timing for reading the serial data 4 according to the length of the transmission medium, and the versatility of the receiver 2 is lowered.

  In addition, in order to synchronize and execute data transmission / reception between the transmitter and the receiver without using the synchronization clock signal 6, serial data is obtained by adding data for synchronization to digital data to be transmitted. When data is transmitted, synchronization data is added to the digital data. This causes a problem that the redundancy increases and the transmission speed decreases.

  Accordingly, an object of the present invention is to provide a receiver capable of accurately demodulating serial data without reducing the data transmission rate and irrespective of the length of the transmission medium.

The present invention provides a synchronization clock signal that is transmitted to a transmitter that transmits serial data and a strobe signal indicating a timing for transmitting the serial data in synchronization with a received synchronization clock signal. Clock signal generating means;
When the start of transmission of serial data is detected based on the strobe signal transmitted from the transmitter, each bit of the serial data transmitted from the transmitter has the same signal waveform as the clock signal for synchronization. A demodulating clock signal generating means for generating a demodulating clock signal representing a timing of reading data of each bit of serial data transmitted from the transmitter, rising or falling at a predetermined timing within a cycle of data;
And a data reading means for sequentially reading the serial data bit by bit in synchronization with a demodulating clock signal.

The present invention further includes reference clock signal generation means for generating a reference clock signal having a frequency higher than that of the synchronization clock signal and the demodulation clock signal,
The synchronization clock signal generation means generates a synchronization clock signal by dividing a reference clock signal,
The demodulation clock signal generating means generates a demodulation clock signal by dividing the reference clock signal.

  Further, the present invention is characterized in that the predetermined timing is a time in the vicinity of a half cycle of a cycle in which each bit of serial data is estimated to be most stable.

  According to the present invention, the synchronization clock signal generation means generates a synchronization clock signal and supplies it to the transmitter. The transmitter transmits a strobe signal and serial data in synchronization with a synchronization clock signal provided from the receiver. The strobe signal represents the timing for transmitting serial data.

  There is a delay in the phase of the data before the data is transmitted from the transmitter to the receiver. Since the transmission distance between the strobe signal and the serial data between the transmitter and the receiver is substantially equal, the magnitudes of the phase delays are also substantially equal. The demodulation clock signal generation means reliably detects the start timing of serial data transmission regardless of the transmission distance between the transmitter and the receiver, based on a strobe signal that causes a phase delay almost equal to that of serial data. can do. The demodulating clock signal generating means generates a demodulating clock signal that represents the timing of reading each bit of data in accordance with the detected start timing of serial data transmission. The demodulation clock signal has the same signal waveform as that of the synchronization clock signal, and rises or falls at a predetermined timing within the data cycle of each bit of the serial data.

  Since the transmitter transmits data in synchronization with the clock signal for synchronization given from the receiver, the frequency of the data of each bit of the serial data sent from the transmitter is the clock signal for synchronization given by the receiver. Surely matches. The frequency of the demodulating clock signal generated by the demodulating clock signal generating means is the same as the frequency of the synchronizing clock signal, and is therefore the same as the data frequency of each bit of the serial data. Therefore, when a demodulating clock signal representing the timing for reading data is generated at a predetermined timing within the data cycle of the first bit of each bit of serial data in time series, each bit of serial data is naturally generated. At a predetermined timing within the data cycle, a demodulation clock signal representing the timing for reading each bit of data is sequentially generated.

  The data reading means sequentially reads serial data bit by bit in synchronization with the demodulation clock signal, so that the serial data can be reliably read in synchronization with the data of each bit of the serial data. In this way, the start timing of serial data transmission is reliably detected irrespective of the data transmission distance between the transmitter and the receiver, and the clock signal for demodulation is synchronized with the start of serial data transmission. Therefore, the timing for reading serial data does not change depending on the transmission distance of data as in the conventional technique. Therefore, unlike the conventional technology, serial data is not read at the timing at which the data of each bit of the serial data is switched at a predetermined data transmission distance, and the serial data is accurately set regardless of the data transmission distance. Can be read.

  In addition, since it is not necessary to transmit serial data to which data for synchronization is added, the redundancy does not increase and the data transmission speed does not decrease.

  According to the present invention, the synchronization clock signal and the demodulation clock signal are generated by dividing the reference clock signal. When generating the clock signal for synchronization and the clock signal for demodulation using separate oscillation circuits, it is difficult to make the frequencies coincide with each other, but for synchronization by dividing the reference clock signal The frequency of the clock signal and the frequency of the demodulation clock signal can be easily matched. In addition, the clock signal for synchronization and the clock signal for demodulation can be generated only by the oscillation circuit that generates the reference clock signal, so that each clock signal is received compared to the case where each clock signal is generated using a separate oscillation circuit. The configuration of the machine becomes simple.

  Further, according to the present invention, the demodulation clock signal generation means is a demodulation clock that represents the timing for reading serial data at a time in the vicinity of a half cycle of the period estimated to be most stable for each bit of the serial data. Generate a signal. Since the data reading means reads serial data in synchronization with the demodulation clock signal, the data reading means reads serial data at a time farthest from the time at which the data of each bit of the serial data is switched. The time most distant from the time at which the data of each bit of the serial data is switched is the time when the serial data is estimated to be the most stable, so the serial data is read most accurately by reading the serial data at this time. Can be read.

It is a block diagram which shows the electric constitution of the transmitter 21 and receiver 22 of one Embodiment of this invention. 4 is a timing chart of data and a high-frequency clock signal 35 received by a transmitter 21 or a receiver 22, respectively. 2 is a block diagram showing an electrical configuration of a transmitter 1 and a receiver 2. FIG. It is a timing chart of the data which the transmitter 1 or the receiver 2 receives. As an example, the timing of data received by the transmitter 1 or the receiver 2 when a delay of a quarter period (T / 4) occurs in the phase of the synchronization clock signal 6 with respect to the phase of the demodulation clock signal 10 It is a chart.

  FIG. 1 is a block diagram showing an electrical configuration of a transmitter 21 and a receiver 22 according to an embodiment of the present invention. The transmitter 21 and the receiver 22 are connected by a transmission medium that transmits an electrical signal such as an electric wire, and constitutes a transmission / reception system that performs clock synchronous serial communication via the transmission medium. The transmitter 21 and the receiver 22 are provided in, for example, industrial and consumer electronic devices, transmit data between a plurality of computers, or are provided in mechatronics related devices, and a sensor is provided between the controller and the mechanism unit. Transmit signals and operation command signals.

  The transmitter 21 is realized by a serial data generation unit 25 that converts digital data 23 composed of parallel data into serial data 24. The digital data 23 is composed of, for example, 8-bit or 16-bit parallel data, and is generated by a digital data generation unit realized by a microcomputer or the like. The serial data generation unit 25 provides the receiver 22 with the strobe signal 27 and the converted serial data 24 in synchronization with a synchronization clock signal (hereinafter referred to as a synchronization clock signal) 26 supplied from the receiver 22.

  The strobe signal 27 represents the timing at which the serial data 24 is transmitted. In the present embodiment, the strobe signal 27 indicates that serial data 24 is transmitted when it is at a low level L, and indicates that serial data 24 is not transmitted when it is at a high level H. That is, when the strobe signal 27 falls from the high level H to the low level L, transmission of the serial data 24 starts. When the strobe signal 27 rises from the low level L to the high level H, transmission of the serial data 24 is completed. Represents that. The serial data generation unit 25 switches the strobe signal 27 from the high level H to the low level L or from the low level L to the high level H in synchronization with the falling of the synchronization clock signal 26 according to the transmission of the serial data 24. The serial data generation unit 25 generates and outputs data of each bit of the serial data 24 in synchronization with the falling of the synchronization clock signal 26. Therefore, the period T of the data of each bit of the serial data 24 is the same as the period T (hereinafter referred to as the basic period) T of the synchronization clock signal 26. In the present embodiment, a procedure in which the transmitter 21 transmits N + 1 bit serial data 24 from data (0) to data (N) and the receiver 22 receives the serial data 24 will be described. The serial data generation unit 25 is realized by a parallel-serial conversion circuit including a shift register, for example.

  The receiver 22 corresponds to a clock signal generation unit 31 corresponding to a reference clock signal generation unit, a frequency division unit 32 corresponding to a synchronization clock signal generation unit, a demodulation clock signal generation unit 33, and a data reading unit. And a data demodulator 34. The clock signal generator 31 generates a high frequency clock signal 35 that repeats a high voltage high level H and a low voltage low level L at a constant frequency, and supplies the generated high frequency clock signal 35 to the frequency divider 32. This is also provided to the demodulation clock signal generation unit 33. The clock signal generation unit 31 is realized by an oscillation circuit including a crystal resonator, for example.

  The frequency divider 32 divides the high-frequency clock signal 35 provided from the clock signal generator 31 by n (symbol “n” indicates a natural number of 2 or more) to generate a low-frequency synchronization clock signal 26. The generated synchronization clock signal 26 is supplied to the serial data generation unit 25. In the present embodiment, the frequency divider 32 divides the high frequency clock signal 35 by 8 to generate the synchronization clock signal 26. That is, the frequency of the synchronization clock signal 26 is 1/8 (f / 8) of the frequency f of the high-frequency clock signal 35. The frequency dividing unit 32 is realized by, for example, an n-ary counter that includes a flip-flop.

  When the demodulation clock signal generation unit 33 detects the start of transmission of the serial data 24 based on the strobe signal 27, the demodulation clock signal generation unit 33 outputs the data of each bit at a predetermined timing within the data period T of each bit of the serial data 24. A demodulation clock signal (hereinafter referred to as a demodulation clock signal) 36 representing the read timing is generated. The demodulation clock signal 36 rises or falls at a predetermined timing within the data period T of each bit of the serial data 24. The period T of the demodulation clock signal 36 is selected to be equal to the period T of the synchronization clock signal 26. Further, the predetermined timing in the present embodiment is selected in the half cycle (T / 2) of each bit data of the serial data 24.

  In another embodiment of the present invention, not only dividing by 8 but dividing by 2 when the delay is T / 4 may be used. However, depending on the amount of delay, the data may deviate from the most stable central portion. In the above-described embodiment, the frequency is divided by 8 as an example in which a point closer to the center can be sampled.

  There is a delay in the phase of the data before the data is transmitted from the transmitter 21 to the receiver 22. Since the transmission distance between the strobe signal 27 and the serial data 24 between the transmitter 21 and the receiver 22 is substantially equal, the magnitudes of the phase delays are also substantially equal. The demodulation clock signal generation unit 33 starts transmission of the serial data 24 regardless of the transmission distance between the transmitter 21 and the receiver 22 based on the strobe signal 27 in which a phase delay substantially equal to that of the serial data 24 occurs. Can be detected reliably. Specifically, the demodulation clock signal generation unit 33 detects the start of demodulation of the serial data 24 by detecting the falling edge of the strobe signal 27.

  The demodulation clock signal generation unit 33 divides the high frequency clock signal 35 supplied from the clock signal generation unit 31 to generate the low frequency demodulation clock signal 36 when the strobe signal 27 is at the low level L. The demodulated clock signal 36 is supplied to the data demodulator 34. That is, the demodulation clock signal generation unit 33 starts transmission of the demodulation clock signal 36 in synchronization with the fall of the strobe signal 27, and stops transmission of the demodulation clock signal 36 when the strobe signal 27 rises. In the present embodiment, the demodulation clock signal generation unit 33 generates a demodulation clock signal 36 that rises at a predetermined timing within the data period T of each bit of the serial data 24. That is, the demodulation clock signal generation unit 33 generates the demodulation clock signal 36 that rises after a half period (T / 2) of the basic period T from the time when the data of each bit of the serial data 24 is switched.

  The demodulation clock signal generator 33 generates a demodulation clock signal 36 having the same signal waveform as that of the synchronization clock signal 26. In the present embodiment, the demodulation clock signal generation unit 33 divides the high frequency clock signal 35 by 8 to generate the demodulation clock signal 36. That is, the frequency of the demodulation clock signal 36 is 1/8 (f / 8) of the frequency f of the high frequency clock signal 35.

  As described above, the synchronization clock signal 26 and the demodulation clock signal 36 are generated by dividing the high-frequency clock signal 35. When the synchronization clock signal 26 and the demodulation clock signal 36 are generated using separate oscillation circuits, it is difficult to make the frequencies coincide with each other. However, the synchronization is achieved by dividing the high-frequency clock signal 35. The frequency of the clock signal for use 26 and the frequency of the clock signal for demodulation 36 can be easily matched. In addition, since only the clock signal generator 31 that generates the high-frequency clock signal 35 can generate the synchronization clock signal 26 and the demodulation clock signal 36, each clock signal is generated using a separate oscillation circuit. The configuration of the receiver 22 is simpler than that.

  As described above, the cycle T of the data of each bit of the serial data 24 transmitted from the serial data generation unit 25 is equal to the cycle T of the synchronization clock signal 26. Since the frequency of the demodulation clock signal 36 generated by the demodulation clock signal generation unit 33 is the same as the frequency of the synchronization clock signal 26, the frequency of each bit of the serial data 24 is the same. Therefore, when the demodulation clock signal 36 representing the data reading timing is generated at a predetermined timing within the data period T of the first bit of the serial data 24 in time series, the serial data 24 At a predetermined timing within the cycle T of the data of each bit, a demodulation clock signal 36 indicating the timing for reading each bit of data is sequentially generated.

  The demodulation clock signal generation unit 33 is realized by a select circuit and an n-ary counter, for example. The select circuit passes the high-frequency clock signal 35 when the strobe signal 27 is at the low level L and applies it to the n-ary counter, and when the strobe signal 27 is at the high level H, it cuts off the high-frequency clock signal 35 to the n-ary counter. Don't give. The select circuit is realized by, for example, an inverter that inverts the strobe signal 27, and an AND circuit to which the output from the inverter and the high-frequency clock signal 35 are input.

  The data demodulator 34 is given a strobe signal 27 from the transmitter 21. The strobe signal 27 received by the data demodulator 34 is a signal obtained by branching the strobe signal 27 received by the demodulation clock signal generator 33. When receiving the strobe signal 27 indicating that the transmission of the serial data 24 is started, the data demodulator 34 reads the serial data 24 bit by bit in synchronization with the demodulation clock signal 36. The data demodulating unit 34 includes a serial-parallel conversion circuit including a shift register, for example.

  The serial-parallel conversion circuit reads the serial data 24 in synchronization with the rising edge of the demodulation clock signal 36 and demodulates the serial data 24 into digital data 23 composed of parallel data.

  FIG. 2 is a timing chart of data received by the transmitter 21 or the receiver 22 and the high-frequency clock signal 35, respectively. In FIG. 2, the horizontal axis represents time. In FIG. 2, a synchronization clock signal 26 represents a signal waveform received by the serial data generation unit 25, and a demodulation clock signal 36, a strobe signal 27, and serial data 24 represent a signal waveform received by the data demodulation unit 34. To express. In the present embodiment, a case where a phase delay of a quarter period (T / 4) occurs with respect to the basic period T of the synchronization clock signal 26 by transmitting data through the transmission line will be described.

  The serial data generation unit 25 switches the strobe signal 27 from the high level H to the low level L in synchronization with the falling of the synchronization clock signal 26 at time t1, and starts transmission of the serial data 24. The strobe signal 27 and the serial data 24 are transmitted to the data demodulator 34 at a time t2 after a quarter period (T / 4) of the basic period T from the time t1. The At time t2, the strobe signal 27 received by the demodulation clock generator 33 is switched from the high level H to the low level L.

  When the strobe signal 27 is switched from the high level H to the low level L at time t2, the demodulation clock signal generation unit 33 starts counting the high frequency clock signal 35 and starts generating the demodulation clock signal 36. Since the frequency of the demodulation clock signal 36 is 1/8 (f / 8) of the frequency f of the high frequency clock signal 35 as described above, the time after the half period (T / 2) of the basic period T from the time t2. At t3, the demodulation clock signal 36 rises from the low level L to the high level H. Thereafter, the demodulation clock signal generation unit 33 continues to provide the data demodulation unit 34 with the demodulation clock signal 36 of the basic period T until the strobe signal 27 is switched from the low level L to the high level H.

  Since the data demodulator 34 reads the serial data 24 in synchronization with the rise of the demodulation clock signal 36, the data demodulator 34 reads the data (0) at the time t3 when the demodulation clock signal 36 rises. At time t4, which is a half period (T / 2) of the basic period T from time t3, the demodulation clock signal 36 falls and the serial data 24 is switched from data (0) to data (1). At time t5, which is a half period (T / 2) of the basic period T from time t4, the demodulation clock signal 36 rises from low level L to high level H, so the data demodulation unit 34 reads data (1). Include. Thereafter, when the strobe signal 27 is at the low level L, the data demodulator 34 sequentially reads the data of each bit of the serial data 24 in synchronization with the rising of the demodulation clock signal 36.

  At time tY, the serial data generation unit 25 switches the strobe signal 27 from the low level L to the high level H in synchronization with the falling of the synchronization clock signal 26 and stops the transmission of the serial data 24. The rise of the strobe signal 27 and the stop of the transmission of the serial data 24 are transmitted to the data demodulator 34 at time tZ after a quarter period (T / 4) of the basic period T by transmitting the transmission medium. To reach.

  When the strobe signal 27 rises from the low level L to the high level H at time tZ, the demodulation clock signal generation unit 33 stops generating the demodulation clock signal 36 and the data demodulation unit 34 Stop reading.

  The data demodulator 34 demodulates the read serial data 24 into digital data 23 composed of parallel data, and gives it to a microcomputer or the like.

  According to the receiver 22 of the present embodiment described above, the demodulation clock signal generator 33 starts transmission of the serial data 24 regardless of the data transmission distance between the transmitter 21 and the receiver 22. Since the timing is reliably detected and the demodulation clock signal 36 is generated at the start of the transmission of the serial data 24, the timing for reading the serial data depends on the transmission distance of the data as in the prior art. No change. Since the data demodulator 34 reads the serial data 24 in synchronization with the demodulated clock signal 36 generated in this way, the serial data is read in the case of a predetermined data transmission distance as in the prior art. The serial data is not read at the timing when the data of each bit is switched, and the serial data 24 can be read accurately regardless of the data transmission distance.

  In addition, since it is not necessary to transmit serial data to which data for synchronization is added, the redundancy does not increase and the data transmission speed does not decrease.

  Further, according to the receiver 22 of the present embodiment, the demodulation clock signal generation unit 33 reads the timing at which the serial data 24 is read at the time of the half period (T / 2) of the period T of each bit of the serial data 24. A demodulating clock signal 36 is generated. Since the demodulation clock signal generation unit 33 reads the serial data 24 in synchronization with the demodulation clock signal generation unit 33, the serial data 24 is at a time farthest from the time at which the data of each bit of the serial data 24 is switched. Is read. The time most distant from the time at which the data of each bit of the serial data 24 is switched is the time at which the serial data 24 is estimated to be most stable. Therefore, by reading the serial data 24 at this time, it is most accurate. Serial data 24 can be read.

  The frequency dividing unit 32 and the demodulation clock signal generating unit 33 of the receiver 22 according to the present embodiment are configured to divide the high frequency clock signal 35 by 8; The clock signal for synchronization 26 and the clock signal for demodulation 36 may be generated by rounding. The data demodulator 34 can read the serial data 24 accurately by synchronizing with the demodulation clock signal 36.

DESCRIPTION OF SYMBOLS 21 Transmitter 22 Receiver 23 Digital data 24 Serial data 25 Serial data generation part 26 Synchronization clock signal 27 Strobe signal 31 Clock generation part 32 Frequency division part 33 Demodulation clock signal generation part 34 Data demodulation part 35 High frequency clock signal 36 Demodulation Clock signal

Claims (3)

A synchronization clock signal for generating the synchronization clock signal to be transmitted to a transmitter for transmitting serial data and a strobe signal indicating the timing for transmitting the serial data in synchronization with the synchronization clock signal to be received Generating means;
When the start of transmission of serial data is detected based on the strobe signal transmitted from the transmitter, each bit of the serial data transmitted from the transmitter has the same signal waveform as the clock signal for synchronization. A demodulating clock signal generating means for generating a demodulating clock signal representing a timing of reading data of each bit of serial data transmitted from the transmitter, rising or falling at a predetermined timing within a cycle of data;
And a data reading means for sequentially reading the serial data bit by bit in synchronization with a demodulation clock signal. Reference clock signal generation means for generating a reference clock signal having a higher frequency than the clock signal for synchronization and the clock signal for demodulation,
The synchronization clock signal generation means generates a synchronization clock signal by dividing a reference clock signal,
2. The receiver according to claim 1, wherein the demodulation clock signal generation means generates a demodulation clock signal by dividing the reference clock signal.   3. The receiver according to claim 1, wherein the predetermined timing is a time in the vicinity of a half cycle of a cycle in which each bit of serial data is estimated to be most stable.

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