JP2000124886A - Method and device for detecting multiframe synchronism - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the synchronism of multiframe speedily without requiring a large capacity memory. SOLUTION: When HDLC pattern data are detected twice by a specified pattern comparing part 26 at the same time interval as the transmission cycle of frames, the bit of the next bit clock timing is decided as being the frame bit of each frame. Then, rather than having the bit information of multiframe as a whole fetched into a memory circuit 32 only the bit information which is decided as being the frame bit is fetched and based on the fetched contents, the timing at the head of multiframe is detected. Hence, the storage capacity of a storage device for storing bit stream signals can be reduced and the circuit scale of the device can be miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method and an apparatus for detecting the synchronization of a multi-frame used for serial data transmission.

[0002]

2. Description of the Related Art Conventionally, a multi-frame used for serial transmission is composed of a fixed number of continuous frames, and a 1-bit frame bit (also referred to as an "F bit") is placed at the beginning of a bit string constituting one frame. .)
Are known.

For example, of the primary group interfaces of ISDN, ITU-T. I. 1.5 as defined in 431
In the 44 Mbps interface, the configuration of the multi-frame is defined as follows. That is, one frame is composed of one frame bit and 24 time slots (8 bits) as shown in FIG.
The number of bits in one entire frame is 193 bits. It is defined that one multi-frame is composed of 24 frames (see FIGS. 7A and 7B).

[0004] One multi-frame includes 24 frame bits, each of which has a defined use. As shown in FIG. 8, the frame bits indicated by e1 to e6 are CRC-6 (Cyclic Redu).
The frame bit indicated by the DL is mainly used for transmitting maintenance information and the like for fault isolation, which is used for detecting a transmission error on the receiving side according to the danency checking-6) procedure. Then, every fourth frame from the fourth frame, that is, the fourth, eighth, twelfth, and first frames
The frame bits of the sixth, twentieth and twenty-fourth frames are
FAS (Frame Alignment Signa)
l) are bits for performing multi-frame synchronization detection, and are sequentially “0”, “0”, “1”, “0”,
"1", "1", etc. are stored. That is, the pattern of “001011” is stored in the 6-bit FAS.

Using this FAS, it is possible to detect the synchronization of a multi-frame, that is, to detect the start timing of the multi-frame, as follows. That is, FAS is 4
Since it is a frame bit for each frame, bit information of serial data sequentially transmitted is extracted at a time interval corresponding to a transmission time of four frames (that is, a bit interval of four frames), and a pattern of “001011” is extracted. (Hereinafter referred to as a synchronization pattern). If they match, the head timing of the multiframe can be detected based on the matching timing. And
If they do not match, the operation of shifting the bit information extraction timing by one bit and checking whether they match the synchronization pattern is performed, and if they match, the start timing of the multiframe is determined based on the matching timing. Is detected.

In this way, the multi-frame synchronization can be detected. However, the bit storing the bit information constituting the synchronization pattern is only one bit out of the number of bits included in the four frames. Therefore, in the above method, the detection time is the maximum (transmission time of one multiframe).
+ (Number of bits for 4 frames) × (access time). In order to detect the synchronization of a multi-frame in a short time, the following method can be considered.

That is, first, one multi-frame data is read from the transmitted serial data. Then, from the head of the read bit string, 772 (= 193)
× 4: the number of bits for four frames) 1 at bit intervals
Each bit (that is, 6 bits) is extracted, and it is compared whether or not the extracted bit information matches the synchronization pattern. If they do not match, the bit positions to be extracted are shifted one by one, and the comparison with the synchronization pattern is repeated again. Then, if a synchronization pattern is detected,
The bit position in the stored bit string can be calculated, and the leading timing can be obtained.

At this time, even if bit information is extracted from a portion other than the FAS, there is a possibility that the bit pattern coincides with the synchronization pattern. At that time, an erroneous bit position is calculated as the head of the multiframe. Therefore, in order to suppress the occurrence of such an error, the bit information for several multi-frames is read, and it is determined whether or not the synchronization pattern is continuously detected at the same position over several multi-frames. do it.

[0009]

However, a large amount of data is required to quickly detect the synchronization of a multi-frame, and a large amount of data is required to suppress the occurrence of erroneous synchronization detection. Is required. Therefore, in the multi-frame synchronization detection circuit, a large memory resource for reading the data is required, which causes a problem that the scale of the entire apparatus for performing the multi-frame synchronization detection becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a multi-frame synchronization detection method and apparatus capable of quickly detecting multi-frame synchronization without requiring a large-capacity memory. And

[0011]

According to a first aspect of the present invention, there is provided a multi-frame synchronization detecting method comprising the steps of: transmitting a specific pattern data from serial data using a multi-frame; When the specific pattern data is detected, the leading bits of the subsequent frames are sequentially read based on the detection timing. Then, when every nth m bits of the read head bits match the synchronization pattern, the head timing of the multi-frame is detected based on the matched timing.

That is, conventionally, from serial data,
Bit information of at least one multi-frame is read, and bit information at a constant bit interval is simply extracted from the read data to detect a synchronization detection pattern. Storage means capable of storing information was required. Therefore, in the present invention, before reading the bit information from the serial data,
First, specific pattern data is detected. In the case where there is no control signal, the specific pattern is at a predetermined specific position in the frame, so that the leading bit position (ie, the leading timing) of the subsequent frame can be derived based on the detection timing. That is, based on the detection timing of the specific pattern data, only the first bit of the subsequent frame is read, the synchronization detection pattern is detected from the read first bit, and the first timing of the multi-frame is detected. .

Therefore, according to the multi-frame synchronization detecting method of the present invention, instead of reading the bit information of the entire multi-frame, only the first bit of each frame is read.
Since the synchronization pattern is detected from the read bit information and the multi-frame synchronization is detected, the bit information to be read is small, and the storage capacity for storing the bit information is small. Since it is good, it is possible to suppress the scale of an apparatus for performing multi-frame synchronization detection.

The reason why the first bit can be selectively read is that the specific pattern data is located at a predetermined specific position in each frame. The same pattern as the specific pattern data may appear. In this case, a bit other than the first bit is stored as the first bit, and there is a possibility that an incorrect synchronization is detected.

Therefore, as described in the second aspect, the reading of the leading bit may be performed when a plurality of specific pattern data are detected at the same time interval as the frame transmission cycle. Then, the possibility of erroneous synchronization detection can be suppressed. That is, since the specific pattern data is located at a specific position in the frame, if it is true specific pattern data, it should be detected at the same time interval as the transmission cycle of the frame. It is unlikely to be detected at the same time interval as the frame transmission cycle. Therefore, according to the second aspect, the leading bit can be more reliably captured, and as a result, highly reliable synchronization detection can be performed.

Such a multi-frame synchronization detecting method is as follows.
This can be realized by the multi-frame synchronization detecting device according to the third aspect. That is, in the multi-frame synchronization detecting device according to the third aspect, the specific pattern detecting means detects the specific pattern data from the serial data, and the reading means detects the specific pattern data based on the detection timing of the specific pattern data by the specific pattern detecting means. , And sequentially reads the first bit of the subsequent frame. Then, when every nth m bits of the leading bits read by the reading means match the synchronization pattern, the leading timing detecting means detects the leading timing of the multi-frame based on the matched timing. .

Therefore, according to the multi-frame synchronization detecting device according to the third aspect, the multi-frame synchronization detection is performed by the multi-frame synchronization detecting method according to the first aspect. The storage amount of necessary data may be small, and expansion of the device scale can be suppressed.

According to a fourth aspect of the present invention, the reading means reads the first bit when a plurality of specific pattern data are detected by the specific pattern detecting means at the same time interval as the frame transmission cycle. With this configuration, the multi-frame synchronization detection method according to claim 2 is realized,
Reliable synchronization detection can be performed.

[0019]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an overall configuration of a multi-frame synchronization detection device as one embodiment. This multi-frame synchronization detection device receives serial data generated using a multi-frame having a configuration defined by a 1.544 Mbps interface among primary group interfaces of ISDN, and performs multi-frame processing from the received serial data. This is a device for detecting the head timing of a frame. In this figure, only the receiving side that receives data from the communication network side is shown, and the transmitting side is omitted.

In the multi-frame configuration, the description of the portion performed in the section of the prior art will be omitted, but the above interface further defines the following for the multi-frame configuration. That is, in this interface, although it is specified that control information and the like of the device are to be inserted in the 24th time slot of each frame, there is no control information to be transmitted (for example, the communication terminal side and the communication network side). In the case where synchronization is not established, etc.), “0111111” is set in the 24th time slot.
0 "(HDLC pattern data).

As shown in FIG. 1, the multi-frame synchronization detecting device includes a receiving unit 2, a synchronization detecting unit 4, a synchronization determining unit 6, a CRC checking unit 8, a channel decomposing unit 10, and a clock generating unit 12. Have been. The receiving unit 2 has three values of “0”, “+1”, and “−1” transmitted from the communication network side via a two-wire metallic balanced pair.
The signal of the 8ZS code format is converted into a binary signal of “0” and “1” (hereinafter, referred to as “bit stream signal”).
Convert to

As will be described in detail later, the synchronization detector 4 detects a synchronization pattern by comparing the FAS included in the bit stream signal with the synchronization pattern. The detection result by the synchronization detection unit 4 is judged by the synchronization judgment unit 6 to be correct. That is, the synchronization determination unit 6
Receives information indicating that a synchronization pattern has been detected from the synchronization detection unit 4, generates a multi-frame synchronization signal (hereinafter, simply referred to as a “synchronization signal”) based on the detection timing, and sends it to the CRC check unit 8. Output.

The CRC check unit 8 performs a CRC check on the bit stream signal (ie, detects a transmission error by the CRC-6 procedure) in synchronization with the synchronization signal from the synchronization determination unit 6, and transmits the bit stream signal by the CRC check. If no error is detected, information to that effect is transferred to the synchronization determination unit 6. The fact that no transmission error is detected by the CRC check means that the synchronization signal output from the synchronization determination unit 6 to the CRC check unit 8 is correct.
That is, the CRC check unit 8 not only checks for the presence or absence of a transmission error, but also determines whether or not the result of synchronization detection by the synchronization detection unit 4 is correct, thereby preventing pseudo synchronization.

Upon receiving information from the CRC checking section 8 that no transmission error has been detected, the synchronization determining section 6 determines that multi-frame synchronization has been established, and outputs a synchronization signal to the channel decomposing section 10. I do. Channel decomposition unit 1
At 0, the bit stream signal that has passed through the CRC check unit 8 is decomposed into frame bits and first to twenty-fourth time slots based on the synchronization signal from the synchronization determination unit 6 and transmitted to a communication terminal device (not shown). .

The clock generator 12 extracts a 1-bit cycle clock signal (hereinafter, "bit clock signal") of the bit stream signal from the received signal in the B8ZS code format, and transfers it to each of the above units. I have. Next, the synchronization detection unit 4 and the synchronization determination unit 6 will be described with reference to FIG. As shown in FIG. 2, the synchronization detection unit 4 includes an 8-bit serial / parallel conversion unit 22 (S / P conversion unit), a specific pattern storage unit 24, a specific pattern comparison unit 26, a first shift register 28, a memory circuit 32, a second shift register, a synchronous pattern comparing unit and a cycle counter 38,
A synchronization detection control unit 40 is provided. A bit clock signal generated by the clock generator 12 is input to each of these units.

The S / P converter 22 takes in and shifts the bit stream signal transmitted serially from the receiver 2 in synchronization with the bit clock signal, and shifts the bit stream signal to output it in parallel as 8-bit data. On the other hand, the specific pattern storage unit 24 stores HD as specific pattern data.
LC pattern data “01111110” is stored. The specific pattern comparison unit 26 compares the 8-bit bit string output from the S / P conversion unit 22 with the HDLC pattern data stored in the specific pattern storage unit 24, and when all eight bits match, “ "1" is output, and if they do not match, "0" is output.

The first shift register 28 stores the number of bits of “(number of bits for one frame) +1” (that is, 193 + 1).
= 194 bits), which takes in and shifts the output from the specific pattern comparing section 26 in synchronization with the bit clock signal, and outputs the values of the least significant bit and the most significant bit. That is, the first shift register 28
Is whether the HDLC pattern data is detected at the same position in two consecutive frames (that is, if the HDLC pattern data is detected at the same time interval as the frame transmission cycle).
Times have been detected).
If detected, both "1" are output as the values of the least significant bit and the most significant bit.

The S / P converter 22, specific pattern comparator 26, specific pattern storage 24, and first shift register 28 described above serve as specific pattern detection means for detecting specific pattern data from serial data. Function. The memory circuit 32 functions as a part of reading means for sequentially reading the first bit of the frame from the serial data. As shown in FIG. 3A, the memory circuit 32 has a 4 × 6 bit memory array. It is configured. When the address Cadd and the bit number Cn are specified together with the write signal from the outside, the memory circuit 32 stores the bit stream signal in the specified bit. When an address Cadd is specified together with a read signal from the outside, a 6-bit bit string stored at the specified address is output in parallel. Note that bit number C
The smaller the value of n, the higher the bit.

The second shift register 34 is a 6-bit shift register in which "001011", which is one of the synchronization patterns, is stored in advance, in which the most significant bit and the least significant bit are connected (a so-called "shift"). Circular register). The second shift register 34 internally generates a clock signal that is six times the bit clock signal, and circulates and shifts the synchronization pattern “001011” at a clock timing that is six times the bit clock signal, and generates 6 bits. Are output in parallel. That is, the second shift register 34 outputs “001011”, “100101”, and “11001” during one cycle of the bit clock signal.
0 "," 011001 "," 101100 "," 010 "
The bit strings of the six sync patterns of “110” (hereinafter, “sync pattern A” to “sync pattern F”, respectively) are sequentially output.

The cycle counter 38 synchronizes with the shift timing of the second shift register 34 from “0” to “0”.
The count is repeated between “5” (that is, the value Csi
ft is incremented by 1 from “0” and returned to “0” after “5”). Therefore, the value Cshift of the cycle counter 38
"0" to "5" that can be taken are "synchronization pattern A", respectively.
~ "Synchronization pattern F".

The synchronization pattern comparing section 36 is a memory circuit 3
2 is compared with the 6-bit bit string output from the second shift register 34 (that is, the synchronization pattern of the patterns A to F). As a result of the comparison, all 6 bits are compared. If they match, "1" is output, and if they do not match, "0" is output.

The synchronization determination section 6 is provided with a bit position counter 6a that operates in synchronization with the bit clock signal. The bit position counter 6a is a down counter for counting the number of bits (4632) of one multi-frame, and repeatedly counts down from "0" to "4631" (that is, the value is changed from "0" to 1). Each time the value becomes "0", a synchronization pulse indicating the start timing of the multi-frame data is output.

The synchronization determining unit 6 includes a synchronization pattern comparing unit 36
When "1" is output as a comparison result from the synchronization detection control unit 40, the bit number C
Based on n and the value Cshift of the cycle counter 38, the head timing of the multiframe is calculated. Then, the bit position counter 6a is set so that the value of the bit position counter 6a becomes 0 at the calculated timing, thereby causing the bit position counter 6a to output a multi-frame synchronization signal.

In the multi-frame synchronization detecting device thus configured, the synchronization detection control section 40 controls the input / output of the memory circuit by the processing shown in FIGS. FIG.
This is a bit clock synchronization process started in synchronization with a bit clock signal generated by the clock generation unit 12.

When the bit clock synchronization process is started, first, it is determined whether or not it is out of synchronization (step 10; hereinafter, "step" is simply referred to as "S"). Whether the synchronization is lost or not is determined based on whether or not a transmission error is detected by the CRC check unit 8. If it is determined that the state is not out of synchronization (a transmission error has not been detected) (S1)
0: NO), the bit clock synchronization processing is immediately terminated, but if it is determined that the state is out of synchronization (a transmission error has been detected) (S10: YES), the HDLC pattern data continues for two consecutive frames. It is determined whether or not HDLC pattern data has been detected (ie, whether or not HDLC pattern data has been detected twice at the same time interval as the frame transmission period) (S
20). This determination is made based on the output (the value of the most significant bit and the least significant bit) of the first shift register 28.
As described above, the fact that the values of both the most significant bit and the least significant bit of the first shift register 28 are “1” indicates that the HDLC pattern data has been detected at the same bit position in two consecutive frames. It is.

If it is not determined that the HDLC pattern data has been continuously detected (S20: NO), the process immediately proceeds to S30, but if it is determined that the HDLC pattern data has been continuously detected (S20: YES). In
After setting the counter Cout = “1” (S25), S30
Move to Here, the counter Cout is defined inside the synchronization detection control unit 40, and is set to “0” to “19” for the purpose of counting the number of bits (193) for one frame.
The counter takes a value of "2", and the maximum value "192" is set when the multi-frame synchronization detection circuit is activated.

In S30, it is determined whether or not the counter Cout = "0". If the counter Cout is not "0" (S30: NO), the process immediately proceeds to S40, but if the counter Cout is "0" (S30: Y).
ES), the bit stream extraction process described below is started, and after the process is completed, the process of S40 is performed.

When the signal extraction and transfer process is started, first,
A write signal is input to the memory circuit 32 and the address C
The add and the bit number Cn are designated, and one bit of the bit stream signal transferred to the memory circuit 32 at that time is stored in the designated position (S110).
Next, the address Cadd is designated together with the input of the read signal, and the 6-bit bit string of the address Cadd including the bit written in S110 is synchronized with the synchronous pattern comparison unit 3.
6 (S120). Here, the address Cad
The d and the bit number Cn are counters defined inside the synchronization detection control unit 40, and are both initialized to “0” when the multi-frame synchronization detection device is started.

After S120, the address Cadd is set to “1”.
(S130), and as a result, the address Cadd becomes 4
It is determined whether or not the above has been achieved (S140). Address C
When it is determined that add is less than 4 (S140: N
In O), the signal extraction and transfer process is immediately terminated, but if it is determined that the number is 4 or more (S140: YES), the address Cadd is returned to “0” (S150). That is,
By the processing of S130 to S150, the address Cadd
Take values from “0” to “3” sequentially.

After the end of S150, the bit number Cn
Is increased by “1” (S160), and as a result, the bit number C
It is determined whether or not n is 6 or more (S170). When it is determined that the bit number Cn is less than 6 (S170:
(NO), the signal extraction / transfer processing is immediately terminated.
If it is determined that this is the case (S170: YES),
The bit number Cn is returned to “0” (S180). That is,
By the processing of S130 to S150, the address Cadd
Take values from “0” to “3” sequentially.

After the end of S30 or S35, the value of the counter Cout is reduced by "1" (S40), and it is determined whether or not the value of the counter Cout has become "-1" or less as a result (SS50). When the value of the counter Cout is "-
If it is not equal to or less than "1" (S50), the bit clock synchronization process is immediately terminated. If it is equal to or less than "-1", the value of the counter Cout is set to "192" (S5).
5) End later.

That is, according to the bit clock synchronization processing and the signal extraction transfer processing, for example, the following processing is performed. That is, the HDLC pattern data is detected at the same period (ie, at the same time interval) as the frame transmission period (S
20: YES), “1” is stored in the counter Cout (S25), and the value is reduced by “1” (ie,
After that, the bit clock processing is temporarily terminated (S40). Then, when the bit clock processing is started again at the timing of the next bit clock signal, the counter Cout is "0", so that YES is determined in S30, and the signal extraction transfer processing is started ( S
35) Therefore, when the HDLC pattern data is detected twice at the same time interval as the frame transmission cycle, the bit information of the bit stream signal is stored in the memory circuit 32 at the timing of the next bit clock signal, and the synchronization pattern comparison is performed. In the section 36, the detection of the synchronization pattern is performed.

The value of the counter Cout is "0" to "1" regardless of whether the HDLC pattern data is detected or not.
The signal extraction and transfer process is started every time the count value becomes "0". Therefore, once it is determined that at least two HDLC pattern data have been detected at the same time interval as the frame period, the frame bits of the subsequent frames are stored in the memory circuit 32 even if they no longer appear. , And the synchronization pattern are compared by the synchronization pattern comparison unit 36.

The synchronization detection control unit for executing the bit clock synchronization processing and the signal extraction and transfer processing described above, together with the memory circuit 32, uses the specific pattern detection means so that the specific pattern data is transmitted at the same time interval as the frame transmission cycle. It functions as reading means for sequentially reading the first bit when a plurality of bits are detected.

As a result of the above processing performed by the synchronization detection control section 40, when the synchronization pattern comparison section 36 outputs "1" as a comparison result, the synchronization determination section 6 causes the synchronization signal setting processing shown in FIG. Is performed. That is, the current timing is calculated based on the bit number Cn designated by the synchronization detection control unit 40 and the value Cshift of the cycle counter 38 (S210). For example, cycle counter 3
If the value Cshift of 8 is “5”, the memory circuit 3
2, the synchronization pattern F “0” is assigned to any of the addresses Cadd.
10110 ”, that is, the bit numbers“ 0 ”to“ 5 ”are sequentially stored in the eighth, twelfth, sixteenth, and second bit numbers.
It can be seen that frame bits 0, 24, and 4 are stored. If the bit number Cn specified by the synchronization detection control unit 40 is, for example, “2”, it is understood that the bit number is the frame bit of the 16th frame stored in the memory circuit 32. That is, it can be seen that the current timing is the head timing of the 16th frame. FIG. 3B illustrates this.
“F1” to “F24” indicate frame bits of the first to 24th frames, respectively.

Based on the current timing thus calculated, how many bits later (ie, how many clocks after) is the start timing of the multiframe, and the value of the bit position counter 6a is set ( S220).
For example, if it is calculated that the frame bit is the 16th frame, the timing at the beginning of the multiframe is
It is calculated that it is 1737 (= 9 × 193) bits later, and “1737” is set in the bit position counter 6a. Here, “9” means that the first frame of the next multiframe is nine frames later. After S220, the synchronization signal setting process ends. Thus, after the synchronization signal setting processing, the synchronization signal at the head timing of the multi-frame is generated from the bit position counter 6a. That is, if every nth m bits of the read start bits match the synchronization pattern, the synchronization determination unit 6 detects the start timing of the multiframe based on the matched timing. Functions as a means.

The synchronization determining unit 6 first outputs to the CRC checking unit 8 to perform a CRC check based on the synchronization signal generated by the bit position counter 6a. If no transmission error is detected by the CRC check, it is determined that multiframe synchronization has been established, and a synchronization signal is output to the channel decomposing unit 10 or the communication terminal side.

As described above, in the multiframe synchronization detecting apparatus according to the present embodiment, the characteristics of the multiframe having the configuration defined by the above-mentioned interface, that is, in the state where there is no control information to be transmitted, the 24th time slot Pays attention to the feature that the HDLC pattern data can be inserted into, and when the HDLC pattern data is detected, the bit of the next bit clock timing is determined to be the frame bit of each frame. Then, the memory circuit 32
Instead of taking in the bit information of the entire multi-frame, only the bits determined to be the frame bits are taken in, and the leading timing of the multi-frame is detected based on the taken-in contents. Therefore, the storage capacity of the memory circuit 32 for storing the bit stream signal (serial data) may be small, and the circuit scale of the device can be reduced.

When HDLC pattern data is detected at the same position in two consecutive frames (that is, when HDLC pattern data is detected).
When the pattern data is detected twice at the same time interval as the transmission period of the frame), the first bit of the subsequent frame is read into the memory circuit 32 based on the detection timing, so that the frame bit can be captured more reliably. As a result, more reliable synchronization detection can be performed.

Conventionally, in order to suppress occurrence of erroneous synchronization detection, the memory circuit 32 had to store bit information for several multi-frames.
It may be determined whether the C pattern data has been detected twice at the same time interval as the frame transmission cycle. In order to determine whether or not detection has been performed twice at the same time interval as the frame transmission cycle, the number of bits that can be stored in the first shift register 28 is “(the number of bits in one frame) +1.
Bits only suffice, and the occurrence of erroneous synchronization detection can be suppressed without requiring large-capacity storage means.

As described above, one embodiment of the present invention has been described. However, the present invention is not limited to the above-described embodiment, and can take various aspects. For example, in the above embodiment,
The first shift register 28 is set to "(bit number of one frame)
Although the description has been made with reference to “+1 bit”, the present invention is not limited to this. For example, the number of bits of the first shift register 28 may be “(the number of bits of two frames) +1 bit”. In this case, the least significant bit (first bit), the middle bit (194th bit) and the most significant bit (38th bit)
5 bits) are all “1” (that is, whether HDLC pattern data is detected at the same position for three consecutive frames), and when all are “1”, at a predetermined timing. If the bit stream signal is stored in the memory circuit 32, the frame bits can be extracted more accurately, and the reliability of the synchronization detection can be improved.

Further, the multi-frame synchronization detecting apparatus of the above embodiment detects the synchronization of a multi-frame configured so that the HDLC pattern data as the specific pattern data is included at the end of each frame, and detects the specific pattern data. Although it has been described that the bit stream signal is stored in the memory circuit 32 at the next bit clock timing, the present invention is not limited to this. If the position of the specific pattern data in the frame is specified,
From the positional relationship between the position and the frame bit which is the leading bit, based on the timing at which the specific pattern data is detected (that is, the position at which the specific pattern data is detected),
What is necessary is just to read a frame bit.

Further, the multi-frame synchronization detecting apparatus of the above-described embodiment uses “every four frames as a multi-frame in which bit data constituting an m-bit synchronization pattern is set at the head bit of every nth frame”. It has been described that the synchronization detection of the "multi-frame in which the bit data constituting the 6-bit synchronization pattern is set in the first bit of the frame" is performed, but the present invention is not limited to this.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a multi-frame synchronization detection device according to an embodiment.

FIG. 2 is an explanatory diagram showing a synchronization detection unit and a synchronization determination unit in detail.

FIG. 3 is an explanatory diagram illustrating a configuration of a memory circuit.

FIG. 4 is a flowchart illustrating a bit clock synchronization process performed by the multi-frame synchronization detection device according to the embodiment;

FIG. 5 is a flowchart showing a signal extraction and transfer process.

FIG. 6 is a flowchart showing a synchronization signal setting process.

FIG. 7 is an explanatory diagram showing a configuration of a multi-frame.

FIG. 8 is an explanatory diagram showing the assignment of each frame bit.

[Explanation of symbols]

2 ... receiving unit, 4 ... synchronization detecting unit, 6 ... synchronization determining unit, 6a ...
Bit position counter, 22 S / P converter, 22 serial / parallel converter, 24 specific pattern storage unit, 2
6 specific pattern comparing section 28 first shift register
32 memory circuit, 34 second shift register, 36
Synchronization pattern comparison unit, 38: cycle counter, 40:
Synchronization detection control unit.

Claims (4)

[Claims] 1. A multi-frame in which m × n frames composed of a bit string of a fixed length and having specific pattern data set at a specific position of the bit string are arranged in chronological order, wherein the m × n frames Of the n-th frame, bit data constituting an m-bit synchronization pattern is set in the first bit, and the first timing of the multiframe can be detected by detecting the synchronization pattern when data is received. A multi-frame synchronization detection method of receiving serial data generated using the obtained multi-frame and detecting a start timing of the multi-frame from the received serial data, wherein the identification is performed from the serial data. When the pattern data is detected, and the specific pattern data is detected, Then, the head bits of the subsequent frame are sequentially read, and if every mth leading bit of the read n bits matches the synchronization pattern, the head of the multi-frame is read based on the matching timing. A multi-frame synchronization detection method comprising detecting timing. 2. The multi-frame synchronization detection method according to claim 1, wherein the reading of the first bit is performed when a plurality of the specific pattern data are detected at the same time interval as a transmission cycle of the frame. Multi-frame synchronization detection method. 3. A multi-frame in which a specific pattern data is set at a specific position of a bit string of a fixed length in a m × n number of frames in a time-series order, wherein the m × n frames Of the n-th frame, bit data constituting an m-bit synchronization pattern is set in the first bit, and the first timing of the multiframe can be detected by detecting the synchronization pattern when data is received. A multi-frame synchronization detection device for receiving serial data generated using the generated multi-frame, and detecting a start timing of the multi-frame from the received serial data, wherein the identification is performed from the serial data. A specific pattern detecting means for detecting pattern data, and the specific pattern detecting means When the specific pattern data is detected, reading means for sequentially reading the leading bits of the subsequent frame based on the detection timing, and every n leading m bits among the read leading bits are synchronized with the synchronous bits. A multi-frame synchronization detecting device, comprising: when the pattern matches, a head timing detecting means for detecting a head timing of the multi-frame based on the matched timing. 4. The multi-frame synchronization detecting device according to claim 3, wherein said reading means reads said first bit by means of said specific pattern detecting means so that said specific pattern data has a time interval equal to a transmission cycle of said frame. A multi-frame synchronization detecting device, which is performed when a plurality of frames are detected.