JPH0279631A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by reading out a signal accumulated in a buffer circuit by a microprocessor according to a program stored in a memory circuit, and detecting the establishment of synchronism and step out. CONSTITUTION:A write control circuit 5 writes all reception signals including header areas on the buffer circuit 4. The microprocessor 6 reads data stored in the buffer circuit 4 according to a synchronism detecting program stored in the memory circuit 7a, and also, detects the establishment of the synchronism of a frame. Also, the microprocessor 6 reads the data stored in the buffer circuit 4 according to a step out detecting program stored in the memory circuit 7a, and also, detects the step out of the frame. In such a way, since it is possible to eliminate a synchronism establishment sequence circuit and a step out detection circuit, the circuit constitution can be simplified.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a communication device that performs communication in a communication format of a fixed-length header area and that synchronizes sequentially according to a predetermined pattern based on the timing of the header area. This relates to a frame synchronization circuit.

(Prior Art) Fig. 4 is a block diagram showing the configuration of this type of conventional frame synchronization circuit. Register circuits (2a) to (2d) convert the 8-bit parallel signal (513) and output the parallel signal (513), respectively.
The decoding circuit (3) decodes 13) to detect a header with a predetermined pattern, and the decoding circuit (3) stops operating while a window open signal (515), which will be described later, is applied, and the decoding circuit (2a) detects the header. When the signal (st4a) is generated, counting of the clock signal (511) is started, and 8
Bit timing signal (S16), address signal (
S1? ) and a bit count circuit that outputs a header timing signal (518), (4) is a buffer circuit for accumulating the received parallel signal (S13), and (5) is a bit count circuit that outputs a header timing signal (518) based on the timing signal of bit count circuit (3). , a write control circuit that stores parallel signals in a buffer circuit (4), (6) a microprocessor circuit that processes received data and outputs a wind oven signal (515), and (7) a program that processes received data. (8) is the decoding circuit (2a) ~
When any of (2d) outputs a header detection signal,
a synchronization establishment sequence circuit that detects synchronization establishment by determining whether or not the same header appears multiple times consecutively in the header area;
Similarly, in (9), when any of the decoding circuits (2a) to (2d) outputs a header detection signal, out-of-synchronization is detected by determining whether an undefined header appears in the header area multiple times in succession. This is an out-of-sync detection circuit.

Note that among these, a buffer circuit (4), a write control circuit (5), a microprocessor circuit (6), and a memory circuit (7) are commonly connected by a pass line (10).

Next, the operation of this frame synchronization circuit will be explained separately for the case of detecting establishment of frame synchronization and the case of detecting loss of synchronization.

a. When detecting the establishment of frame synchronization, the transmitter and receiver receive a serial signal with a frame structure as shown in Figure 5, that is, one frame has a header area (8 bits long).
30) and a 384-bit data area (31).
The transmitting side uses the header area (30) to transmit a header pattern determined in advance with the receiving side, and also transmits the same frame multiple times.

On the receiving side, the microprocessor circuit (6) receives the wind oven signal (
515), and this wind oven signal (
515), the bit count circuit (3) stops counting the clock signal (Sll). In this state, the register circuit (1) converts the received serial signal (512) into a parallel signal (513), and decodes the circuit (2a) to
(2d) and the write control circuit (4). Among these, the decoding circuits (2a) to (2d) decode the parallel signal (S13) and determine whether or not each has a predetermined header pattern. And the decoding circuit (
2a) found this, the header detection signal (
When S14a) is applied to the bit count circuit (3), this bit count circuit (3) receives the clock signal (Sll).
starts counting the timing signal (51B) every 8 bits.
), the address signal (51
7) and a per-frame header timing signal (518
). The synchronization establishment sequence circuit (8) is
Header timing signal (5) of bit count circuit (3)
The header timing is known from 18), and it is determined whether or not a predetermined header pattern has been sent at that timing. Then, using the same method, it is determined whether or not the header pattern exists in the header area of several consecutive frames, and if so, a synchronization establishment signal (S19) is output.

Through the above operations, frame synchronization has been achieved between the transmitting side and the receiving side, and after synchronization is established, data is transmitted and received using header patterns that indicate data transmission and reception. For received data, decode circuit (2a)
When it is determined that ~(2d) has operated and received the received data, the write control circuit (5) writes the receive buffer y(4)e
The microprocessor (6) stores the received data and processes the received data based on the program stored in the memory circuit (7).

b. When detecting out-of-synchronization, the out-of-synchronization detection circuit (9) detects the header detection signal (S1) of the decoding circuits (2a) to (2d) every time the header timing signal (518) is output from the bit count circuit (3).
4a) to (S15d) to determine whether any one of the predefined header patterns has been received.

If it has not been received, and if there are undefined header patterns in a plurality of consecutive frame header areas using the same method, an out-of-synchronization signal (520) is sent.

(Problem to be solved by the invention) Since the conventional frame synchronization circuit was configured as described above, there was a problem that the scale of the circuit increased in direct proportion to the protection of the synchronization establishment and synchronization loss sequences. .

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a frame synchronization circuit that can greatly simplify the circuit configuration for detecting synchronization establishment and synchronization loss.

(Means for Solving the Problems) A frame synchronization circuit according to the present invention performs synchronization establishment and synchronization loss of serial signals among buffer circuits, write control circuits, microprocessor circuits, and memory circuits that are commonly connected by a pass line. A program for detection is stored in the memory circuit, and when the write control C circuit stores the parallel signal in the buffer circuit at a predetermined timing, the microprocessor circuit reads this parallel signal and establishes and synchronizes the frame. It is designed to detect deviations.

[Effect]

In this invention, a program stored in a memory circuit causes a microprocessor circuit to read out parallel signals stored in a buffer circuit, and detect synchronization establishment and synchronization loss, which eliminates the need for multiple signals in conventional devices. In addition to requiring only one decoding circuit, a synchronization establishment sequence circuit and an out-of-synchronization detection circuit are no longer necessary, thereby making it possible to greatly simplify the circuit configuration.

【Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 4 indicate the same elements. Here, the decoding circuit (2) has the same function as the decoding circuit (2a) shown in FIG. 4, and the memory circuit (7a) is stored in the memory circuit (7) shown in FIG. In addition to the above programs, this program stores a program for detecting establishment of synchronization and a program for detecting loss of synchronization. With this configuration, the fourth
The configuration is such that the decoding circuits (2b) to (2d), the synchronization establishment sequence circuit (8), and the out-of-synchronization detection circuit (9) shown in the figure are removed.

The operation of the present embodiment configured as described above will be explained below, focusing in particular on the conventional device and structural components shown in FIG.

First, the decoding circuit (2) searches for a header pattern of a signal sent from the transmitting side, and if a predetermined header pattern is found, sends a header detection signal (S14) to the bit counting circuit (3). Bit count circuit (3)
When the header detection signal is input, it starts counting the clock signal (511), generates an 8-bit timing signal (516), an address signal (Si2) and a header timing signal (S18), and performs write control. Add to circuit (5).

Also, the write control circuit (5) based on these signals,
Buffer circuit (4) for all received signals including the header area
write to.

Therefore, the microprocessor (6) has a memory circuit (7a).
) According to the synchronization detection program stored in the buffer circuit (4), the data stored in the buffer circuit (4) is read and establishment of frame synchronization is detected. In this case, detection is performed according to the processing procedure shown in FIG.

That is, in step (101), the bit count circuit (3) or the write control circuit (5) reports
Determine whether a frame has been received. in this case,
Assuming that the transmission speed is 64 [kbps] and one frame consists of 384 bits as shown in FIG. 5, notification will be made every 6.125 [msl]. In step (102), it is determined whether the header pattern of the first byte of one frame is one that has been attached in advance. Here, if the header pattern has been agreed upon in advance, it is determined again in step (103) whether or not one frame has been received; if the header pattern has not been agreed in advance, it is determined again in step (104). Send the wind oven signal to the count circuit (3) to resynchronize. Also, step (10
If it is determined in step 3) that one frame has been received, it is determined again in step (105) whether or not the header pattern of the first byte of one frame is the one determined in advance. Here, if the pattern has been agreed upon in advance, it is determined that synchronization has been established in step (106), and if it is not a pattern that has been agreed upon in advance, the process returns to step (104) and the synchronization is re-established. .

In this way, after detecting the establishment of synchronization, the microprocessor circuit (6) processes the received data in the same manner as described for the conventional device.

The microprocessor (6) also has a memory circuit (7a).
According to the program that detects out-of-sync stored in
The data stored in the buffer circuit (4) is read and frame out-of-synchronization is detected. In this case, detection is performed according to the processing procedure shown in FIG. That is, in step (111) it is determined whether or not one frame of signal has been received, and if so, in step (112) it is determined whether the header pattern of the first byte of one frame is undefined. . In this case, if there are multiple types of defined patterns, the header pattern written in the buffer (4) is compared with these defined patterns in order. If it does not match any of the defined patterns, remember that the synchronization has occurred in step (113), and then repeat step (111) and step (115). Exactly the same processing as (112) is performed. If it is determined in step (115) that it does not match any of the defined patterns, it is stored in step (117) that the synchronization has occurred twice, and further, in step (11B)
), similar processing is performed in (119). If it is determined in steps (115) and (119) that it is not undefined, in step (116), the storage of the occurrence of synchronization is stopped, and step (116) is performed.
Return to step 11). On the other hand, in step (119), if it is determined that the header pattern written in the reception buffer (4) and the definition pattern do not match, that is, if out-of-synchronization occurs three times in a row, The process of detecting the establishment of synchronization described above is executed.

Thus, according to this embodiment, although an extra program for detecting synchronization establishment and synchronization loss is stored in the memory circuit (7a), the number of four decoding circuits required in the conventional device can be reduced to one. At the same time, the synchronization sequence circuit (8) and the out-of-synchronization detection circuit (9)
This makes it possible to simplify the circuit configuration and provide an inexpensive and highly accurate frame synchronization circuit.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a microprocessor reads parallel signals stored in a buffer circuit based on a program stored in a memory circuit, and detects synchronization establishment and synchronization loss. As a result, only one decoding circuit is required compared to multiple signals in conventional equipment, and the synchronization establishment sequence circuit and synchronization loss detection circuit are no longer required, which has the effect of greatly simplifying the circuit configuration. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIGS. 2 and 3 are flowcharts for explaining the operation of the same embodiment, FIG. 4 is a block diagram showing the configuration of a conventional frame synchronization circuit, and FIG. 5 is for explaining the operation of this frame synchronization circuit. (1)...Register circuit, (2)...Decode circuit, (3)...Bit count circuit, (4)...Reception buffer circuit, (5)...・Write control circuit, (6)・
...Microprocessor circuit, (7a)...Memory circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A serial signal sent in frame units is converted into a parallel signal, this parallel signal is decoded to detect a predetermined pattern of headers, and the header detection signal is used to create a predetermined timing signal. A frame synchronization circuit detects synchronization establishment and synchronization loss of frames based on a parallel signal, which includes a buffer circuit, a write control circuit that controls writing to the buffer circuit, a microprocessor circuit, and a frame synchronization circuit that detects synchronization establishment and synchronization loss of frames based on a parallel signal. a memory circuit storing a program for detecting synchronization loss, wherein the write control circuit stores the parallel signal in the buffer circuit based on the timing signal, and the microprocessor circuit stores the parallel signal in accordance with the program of the memory circuit. A frame synchronization circuit characterized by reading parallel signals accumulated in a buffer circuit and detecting establishment and loss of frame synchronization.