JP2005050153A - Method of clock synchronized serial data transfer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate the need to add a signal line for the transfer of variable-length data when a device using a method of clock synchronized serial data transfer is used for the transfer of variable-length data and to keep the numbers of added circuits and software processes as few as possible. <P>SOLUTION: A data sending part 1 sends N data sampling indication signals 13 to a data receiving part 2 in synchronization with data for indicating to the data receiving part 2 that data are sent for each sending of data composed of predetermined bits. If there are no data transferred from the data sending part 1 and if no transfer unit data sampling indication signal 13 sent from the data sending part 1 in synchronism with data reception are detected, the data receiving part 2 determines that the data transfer of data signals 12 has ended. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a clock synchronous serial data transfer system, and more particularly to a clock synchronous serial data transfer system capable of performing variable length data transfer.

  In the conventional clock synchronous serial data transfer method, when byte (byte) or word (word) data is transferred successively and sequentially, the number of data transferred continuously is variable length data transfer that can be changed on the transmission side. As a method of notifying the end of data transfer from the data transmission side to the data reception side, information indicating the amount of transfer data is added to the data to be transferred on the transmission side, and the data is transferred on the reception side. A method for identifying the number of incoming data (see Japanese Patent Laid-Open No. 5-63755) and a signal for notifying the end of data transfer from the transmission side to the reception side are provided, and this signal is used when the data transfer is completed. In this method, the end of data transfer is notified from the receiver to the receiver.

  In the former method, a code circuit and a software process for giving information indicating the amount of transfer data are required on the transmission side, and the amount of transfer data is identified on the reception side based on the information indicating the amount of transfer data. Therefore, there is a problem that the number of circuits and the number of software processes increase.

  In the latter method, in addition to the signal line necessary for normal clock synchronous serial data transfer, another signal line must be added in the case of variable-length data transfer for the signal to notify the end of data transfer. There was a problem that had to be done.

  As described above, when variable length data transfer is performed by the conventional method, it is necessary to add a circuit, process software, or add a signal line. The variable length data transfer in the clock synchronous serial data transfer method is a portable device. It was not a transfer method suitable for devices that required space saving and power saving.

  Therefore, it is necessary to add a signal line for variable length data transfer when variable length data transfer is performed in a device that requires space saving and power saving such as a portable device using a clock synchronous serial data transfer method. There is also a demand for a clock synchronous serial data transfer system that can realize variable length data transfer by a method that minimizes the addition of circuits and software processing.

JP-A-5-63755 (page 1-2, FIGS. 2, 17, and 18)

  In the conventional clock synchronous serial data transfer system described above, as a method for notifying the end of data transfer from the transmission side to the reception side, information indicating the amount of transfer data is added to the data transferred on the transmission side of the data transfer, and reception is performed. There is a method of identifying the number of data transferred based on this information on the side, but in this method, a code circuit or software processing for giving information indicating the amount of transferred data is provided on the transmission side. It is necessary, and the receiving side requires a decoding circuit for determining the transfer data amount from the above information indicating the transfer data amount and software processing for analyzing the transfer data amount. It has the disadvantage of increasing processing.

  There is also a method of newly providing a signal for notifying the end of data transfer from the transmitting side to the receiving side, and using this signal to notify the end of data transfer from the transmitting side to the receiving side when the data transfer ends. In the case of this method, there is a disadvantage that another signal line must be added in addition to the signal line necessary for clock synchronous serial data transfer for the signal notifying the end of data transfer. .

  An object of the present invention is to provide a signal for performing variable length data transfer when performing variable length data transfer in a device that requires space saving and power saving, such as a portable device using a clock synchronous serial data transfer method. It is an object of the present invention to provide a clock synchronous serial data transfer method that can realize variable-length data transfer by a method that does not require the addition of a line and suppresses addition of circuits and software processing as much as possible.

  In the clock synchronous serial data transfer system according to the first aspect of the present invention, N (N is a positive integer of at least 1) pieces of data having a predetermined bit structure are transmitted from the data transmission side to the data reception side. The data receiving side is transmitted from the data transmitting side to the data receiving side in synchronization with the data, and the data receiving side When the data transmission from the data transmission side is lost, and the data take-in instruction signal transmitted from the data transmission side in synchronization with reception of the data is not detected, the data transmission side It is characterized by determining that the data transfer to the data receiving side has been completed.

  The clock-synchronized serial data transfer system according to the second invention is for each transmission of N (N is a positive integer of at least 1) pieces of data having a predetermined bit structure from the data transmission side to the data reception side. In addition, the data transmission instruction signal for instructing the data reception side of the timing of the individual data acquisition is transmitted from the data transmission side to the data reception side in synchronization with the data, and the data transmission The side further continues to transmit the same number of clock pulses as the number of clock pulses necessary for the transmission of one data for the clock signal even after the transmission of the last data transferred from the data transmission side is completed. The transmission of the clock signal is continued, and the data receiving side has no transfer of the unit data from the data transmitting side and is based on the clock signal. The data transfer from the data transmission side to the data reception side is completed when the data capture instruction signal transmitted from the data transmission side is not detected in synchronization with the reception of the transfer unit data. It is characterized by determining.

  In the clock synchronous serial data transfer system according to the third aspect of the invention, N (N is at least 1) constituting transfer data transmitted for data transfer in synchronization with a clock signal from the data transmission side to the data reception side. Each time a positive integer) data is transmitted, a data acquisition instruction signal for instructing the data reception side of the timing of acquisition of each data is synchronized with the data from the data transmission side. The data transmission side transmits the same number of clock pulses as the number of clock pulses necessary for transmission of one transfer unit data after the transmission of the last data transferred from the data transmission side is completed. The clock signal is further transmitted until the transmission of the clock pulse is completed, and the data receiving side transmits the data from the data transmitting side. When the transmission data end signal is detected without the transmission, and based on the clock signal, the data capture instruction signal transmitted from the data transmission side in synchronization with the reception of the data is not detected, It is characterized in that it is determined that the data transfer from the data transmitting side to the data receiving side has been completed.

  A clock-synchronized serial data transfer system according to a fourth aspect of the present invention is characterized in that, in the clock-synchronized serial data transfer system according to the first, second or third invention, the data is byte-structured data.

  According to a fifth aspect of the present invention, there is provided a clock synchronous serial data transfer system according to the first, second or third aspect of the invention, wherein the data is word-structured data.

According to a sixth aspect of the present invention, a clock synchronous serial data transfer system receives a first system as a CPU system that transmits data to be transferred, and receives the data transmitted from the first system as transfer data. A second system, wherein the first system comprises:
(A) a memory in which the data is stored in units of bytes;
(B) a serial data transmission unit for inputting the data as parallel data in units of bytes and transmitting the data as serial data to the second system;
(C) sequentially reading the data, which is the parallel data in byte units, from the memory in byte units, outputting the read transfer data to the serial data transmission unit, and controlling the transfer data transmission operation of the serial data transmission unit A first CPU that performs
The second system comprises:
(D) a serial data receiving unit that receives the data transmitted as serial data from the first system and outputs the data as parallel data in units of bytes;
(E) a second memory for storing the data in bytes transmitted from the first system;
(F) a second CPU that controls a transfer data reception operation of the serial data reception unit, inputs the data in byte units output from the serial data reception unit, and sequentially writes the data in the memory;
Comprising the serial data receiving unit,
(G) a shift register for storing the received 1-byte serial data;
(H) a counter that counts the number of clock pulses of the clock signal output from the serial data transmission unit;
(I) a data capture instruction signal detector for detecting a data capture instruction signal;
It is characterized by having.

  As described above, the clock synchronous serial data transfer system of the present invention has N (N is a positive integer of at least 1) pieces of data having a predetermined bit configuration from the data transmission side to the data reception side. Data transmission instruction signal for indicating to the data reception side that each data has been transmitted is transmitted from the data transmission side to the data reception side in synchronization with the data. Data transfer from the data transmission side to the data reception side is completed when there is no data transfer from the data transmission side and no data capture instruction signal transmitted from the data transmission side is detected in synchronization with the data reception. With this configuration, it is possible to use variable length data in devices that require space and power saving, such as portable devices that use the clock synchronous serial data transfer method. When transferring data, there is no need to add signal lines for variable-length data transfer, and variable-length data transfer can be realized in a way that minimizes the addition of circuits and software processing. Have.

  The present invention uses a clock signal to synchronize the timing of serial data transfer between a data transmission side and a data reception side, and data having a predetermined bit structure such as a byte or a word, for example, In the case of bytes, a data acquisition instruction signal for instructing the reception side to take in each piece of continuously transferred data when 1 byte (8 bits) of data is continuously transferred from the transmission side to the reception side. The clock transmission serial data transfer system using the data transmission side when performing variable length data transfer in which the number of data transferred from the data transmission side to the data reception side is not necessarily constant and may vary The data capture instruction signal is further detected at a predetermined timing after the transfer of the last data transferred continuously from When not detected examine whether Luke is a configuration clock synchronous serial data transfer method to be determined that the data transfer from the data transmission side is terminated.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of the clock synchronous serial data transfer system of the present invention.

  The clock-synchronized serial data transfer system of the present embodiment shown in FIG. 1 handles a bit string transmitted as bit data to the receiving side in a bit-serial manner in byte units, and handles 8-bit data divided in byte units. A data signal 12 including N (N is a positive integer of at least 1) pieces of data composed of bit strings is transmitted together with the clock signal 11 in synchronization with the clock signal 11, and each data constituting the data signal 12 is transmitted. The data transmission unit 1 that outputs a data capture instruction signal 13 for instructing the reception process to the reception side, and the data signal 12 transmitted from the data transmission unit 1 are received in synchronization with the clock signal 11. Each data constituting the data signal 12 transmitted from the data transmitter 1 is received by receiving the data capture instruction signal 13. By sequentially capturing data, and a data reception unit 2 which receive the data transferred from the data transmitter 1.

  Next, the operation will be described.

  FIG. 2 is a waveform diagram showing an example of a signal waveform for explaining the operation of the clock synchronous serial data transfer system of the present invention. 2A is connected to the dotted line portion shown in FIG. 2B, and is shown in FIGS. 2A and 2B. The overall waveform of the signal is shown.

  In FIG. 1, when the data transmission unit 1 transmits the transfer data transmitted to the data reception unit 2 for data transfer in bit serial, the data transmission unit 1 divides the bit string transmitted in bit serial in units of bytes, as shown in FIG. In addition, the data signal 12 including N pieces of data composed of bit strings divided into byte units is transmitted to the data receiving unit 2 in synchronization with the clock signal 11.

  That is, the data transmitting unit 1 sequentially synchronizes N pieces of data composed of 8 bits (1 byte), which is the minimum data transfer unit, with the clock signal 11 and transmits the data signal 12 to the data receiving unit 2. To do.

  At this time, the data transmission unit 1 outputs a data capture instruction signal 13 to the data reception unit 2 at the timing of the last 8 bits of each 1-byte bit string constituting each data. The data capture instruction signal 13 is used to instruct the reception side from the transmission side to receive each data that constitutes the transfer data transmitted by the data signal 12 and is continuously transferred. Is output to the data receiving unit 2 in order to instruct the timing.

  On the other hand, the data receiving unit 2 receives the data signal 12 transmitted from the data transmitting unit 1 in synchronization with the clock signal 11, but 8 bits of each data constituting the data signal 12 transmitted from the data transmitting unit 1. By detecting the data capture instruction signal 13 at the eye timing, the data receiving unit 2 includes the data bit of the data signal 12 received at the same timing as the data capture instruction signal 13 in the data signal 12. It is determined that the bit is the eighth bit of the bit string constituting each data, and the data including the bit can be distinguished from the other data immediately before, and the data can be captured.

As described above, the transfer operation from the data transmission unit 1 to the data reception unit 2 is repeated N times until all the N data scheduled to be transferred from the data transmission unit 1 to the data reception unit 2 are transferred.
When the transfer of the Nth byte of data is completed, the transmission operation of the data signal 12 is stopped. However, for the clock signal 11, the data transmission unit 1 further continues with eight clock pulses as shown in FIG. After sending, stop sending clock pulses.

  On the other hand, the data receiving unit 2 sequentially receives the eight clock pulses of the clock signal 11, but at this time the clock pulse of the clock signal 11 is counted and the data signal 12 is not transmitted. If it is recognized that the data capture instruction signal 13 is not detected at the timing when the last eighth clock pulse is input, it is determined that reception of all the data included in the data signal 12 has been completed.

Next, an embodiment of the clock synchronous serial data transfer system of the present invention will be described.

  FIG. 3 is a block diagram showing an embodiment of the clock synchronous serial data transfer system of the present invention.

  The clock-synchronized serial data transfer system of the present invention shown in FIG. 3 includes a transmission system 100 that is a CPU (Central Processing Unit) system that transmits data to be transferred and a CPU system that receives data to be transferred. A receiving system 200 is included.

  The transmission system 100 has the same data transmission function as the data transmission unit 1 shown in FIG. 1 and the memory 102 in which each data to be transferred to the reception system 200 by the data signal 12 is stored in byte units (8 bits). A serial data transmission unit 103 that sequentially inputs the 8-bit parallel data stored in the memory 102 and sequentially transmits the 8-bit parallel bits of the input data to the reception system 200 as serial data; The CPU 101 sequentially reads each 8-bit parallel data from the byte 102, outputs the read data to the serial data transmission unit 103, and controls the transmission operation of the transfer data of the serial data transmission unit 103. .

  The reception system 200 has the same data reception function as that of the data reception unit 2 shown in FIG. 1, receives the data signal 12 transmitted as serial data from the transmission system 100, and sets each data constituting the data signal 12. Serial data receiving unit 203 that sequentially outputs as parallel data in units of bytes, memory 202 that sequentially inputs each of the data output from serial data receiving unit 203 and stores the data as a data signal from transmission system 100, and serial data From the CPU 201 that controls the receiving operation of the transfer data of the receiving unit 203, sequentially inputs the above data output from the serial data receiving unit 203 in bit parallel, and sequentially writes the input data in the memory 202 in bit parallel Composed.

  The serial data receiving unit 203 of the receiving system 200 receives the data signal 12 and sequentially stores 1-byte serial data of each data constituting transfer data included in the data signal 12, and a transmission system. A counter 205 that counts the number of clock pulses of the clock signal 11 output from the serial data transmission unit 103 of 100, a data acquisition instruction signal detection unit 206 that detects the data acquisition instruction signal 13 from the transmission system 100, and Consists of

  Next, the operation will be described.

  In FIG. 3, when transferring N bytes of data from the transmission system 100 to the reception system 200, the CPU 101 sequentially reads N pieces of byte data composed of 8 bits constituting the transfer data from the memory 102 in bit parallel. The data for transfer is sequentially input to the serial data transmission unit 103 in bit parallel.

  The serial data transmission unit 103 sequentially converts each 8-bit parallel data input by the CPU 101 into 8-bit serial data for data transfer, and divides the obtained bit string in units of bytes. As shown, the data signal 12 including N pieces of data composed of bit strings divided into byte units is sequentially transmitted to the serial data receiving unit 203 of the receiving system 200 in synchronization with the clock signal 11.

  As shown in FIG. 2, the timing at the time of transfer of each byte of data included in the data signal 12 from the serial data transmission unit 103 is transferred in synchronization with the clock pulse of the clock signal 11, and the data signal 12 is The data acquisition instruction signal 13 transmitted from the serial data transmission unit 103 to the serial data reception unit 203 is also used as a clock signal 11 in order to instruct from the transmission side to the reception side of each configured data that is continuously transferred. In synchronization with the data, the data is transmitted from the serial data transmission unit 103 to the serial data reception unit 203 at the timing of the eighth bit counted from the first bit of each data of the data signal 12.

  On the other hand, the serial data receiving unit 203 that has received the data signal 12 sequentially fetches a bit string of each data of the data signal 12 into the shift register 204 at a timing synchronized with the clock signal 11. At this time, the counter 205 counts the clock pulses of the clock signal 11 and notifies the data capture instruction signal detection unit 206 of the timing at which the eighth clock of each data constituting the data signal 12 is input.

  When the data capture instruction signal detection unit 206 detects the data capture instruction signal 13 notified from the counter 205 at the timing when the eighth clock of each data is input, the data capture instruction signal 13 is detected at the same timing as the data capture instruction signal 13. It is determined that the received bit of the data signal 12 is the eighth bit of the constituent bits of each data constituting the data signal 12, and the data including the bit as the eighth bit is used as the immediately preceding data. Identify and capture as subsequent data. Then, a data capture completion notification signal 303 indicating that reception of the data has been completed is output to the CPU 201.

  In response to the data capture completion notification signal 303, the CPU 201 reads 1-byte data transferred from the transmission system 100 and stored in the shift register 204 and writes it into the memory 202.

  As described above, the transfer operation from the transmission system 100 to the reception system 200 is repeated N times until all the N pieces of data scheduled to be transferred from the transmission system 100 to the reception system 200 are transferred.

  When the transfer of the Nth byte data is completed, the CPU 101 of the transmission system 100 instructs the transmission operation of the data signal 12 to the serial data transmission unit 103 to be terminated. By this instruction, the transmission operation of the data signal 12 from the serial data transmission unit 103 is stopped. However, for the clock signal 11, the serial data transmission unit 103 continues the eight clock pulses as shown in FIG. After sending, stop sending clock pulses. The serial data transmission unit 103 terminates transmission to the serial data reception unit 203 with transmission of the eight clock pulses transmitted to the serial data reception unit 203 as described above in a state where transmission of the data signal 12 is not performed. To do.

  On the other hand, the counter 205 of the serial data receiving unit 203 sequentially receives the eight clock pulses of the clock signal 11. At this time, the counter 205 also counts the clock pulses of the clock signal 11 and transmits the data signal 12. The data fetch instruction signal detection unit 206 is notified of the timing at which the eighth clock pulse of the clock pulse that has been transmitted without being transmitted is input.

  When the data capture instruction signal detection unit 206 notified of the timing from the counter 205 recognizes that the data capture instruction signal 13 is not detected at the timing at which the last eighth clock pulse is input, the data signal 12 outputs to the CPU 201 a data transfer end notification signal 304 indicating that the transfer of the data signal 12 has been completed after reception of all the data included in the data 12 is completed. In FIG. 2B, there is no signal pulse of the data fetch instruction signal 13 in the elliptical line surrounding the last eighth clock pulse, and the last eighth clock pulse is input. In this timing, the state in which the data take-in instruction signal 13 is not detected is shown.

  The CPU 201 receives the data transfer end notification signal 304 from the data take-in instruction signal detection unit 206 and determines that the data transfer from the serial data transmission unit 103 has ended.

  This is the end of the detailed operation of the clock synchronous serial data transfer method of the present invention shown in FIG.

  In the above description, the bit string transmitted serially for data transfer has been described as being divided and handled in units of bytes. However, the bit string is not divided in units of bytes but is divided in units of words. Also good.

  In the above description, the data acquisition instruction signal is transmitted to the data receiving side at the timing of the 8th bit of each 1 byte constituting the transfer data transmitted from the data transmitting side, and the data receiving side transmits from the data transmitting side. As described above, the boundary of each byte is identified by receiving the data capture instruction signal at the timing of the eighth bit of each 1 byte constituting the transferred data. A data capture instruction signal is output to the data receiving side at the transmission timing of a specific bit determined in advance in the byte, and the data reception side also receives the data capture instruction signal at the transmission timing of the specific bit. You may make it identify a boundary.

  In the above description, a predetermined number (8 bits) of clocks are used as the clock signal 11 even after the data transmission side finishes transmitting the last data (Nth byte) of the data signal 12 transferred from the data transmission side to the data reception side. The pulse is continuously transmitted, and the data receiving side receives the 8-bit clock pulse of the clock signal 11 that is continuously transmitted after the last data is received from the data transmitting side, and receives the data. The detection operation of the signal 13 is performed, and when the data capture instruction signal 13 is not detected, it has been described that the data transfer from the data transmission side to the data reception side is completed, as shown in FIG. As described above, the transfer data end signal 14 transmitted from the data transmission side is not detected and the timings of the seventh and eighth clock pulses are not detected. When it is detected by the grayed, data transfer from the data transmission side to the data receiving side may be determined as ended. In addition, the dotted line part of the line which shows the waveform of each signal shown by Fig.4 (a) is connected to the dotted line part shown by FIG.4 (b), and FIG.4 (a) and FIG.4 (b) are. The overall waveform of the signal is shown.

It is a block diagram which shows one Embodiment of the clock synchronous serial data transfer system of this invention. It is a wave form diagram which shows an example of the waveform of the signal for demonstrating operation | movement of the clock synchronous serial data transfer system of this invention. It is a block diagram which shows the Example of the clock synchronous serial data transfer system of this invention. It is a wave form diagram which shows another example of the waveform of the signal for demonstrating operation | movement of the clock synchronous serial data transfer system of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data transmission part 2 Data reception part 11 Clock signal 12 Data signal 13 Data taking instruction signal 14 Transfer data end signal 100 Transmission system 101 CPU
102 Memory 103 Serial Data Transmitter 200 Receiving System 201 CPU
202 Memory 203 Serial Data Receiving Unit 204 Shift Register 205 Counter 206 Data Acquisition Instruction Signal Detection Unit 303 Data Acquisition Completion Notification Signal 304 Data Transfer End Notification Signal

Claims (6)

Each time N data (N is a positive integer of at least 1) pieces of data having a predetermined bit structure are transmitted from the data transmission side to the data reception side, the data reception side receives the data. A data capture instruction signal for instructing the timing of the data is transmitted from the data transmission side to the data reception side in synchronization with the data, and the data reception side eliminates the transfer of the data from the data transmission side. And when the data capture instruction signal transmitted from the data transmission side in synchronization with the reception of the data is not detected, it is determined that the data transfer from the data transmission side to the data reception side is completed. A clock-synchronized serial data transfer system. Each time the N (N is a positive integer of at least 1) pieces of data having a predetermined bit configuration is transmitted from the data transmission side to the data reception side, the individual data is captured by the data reception side. A data capture instruction signal for instructing the timing of the data is transmitted from the data transmission side to the data reception side in synchronization with the data, and the data transmission side transmits the last data to be transferred from the data transmission side. Even after the end of transmission, the clock signal continues to be transmitted until the transmission of the same number of clock pulses as the number of clock pulses necessary for the transmission of one data is completed. Transfer of the unit data from the data transmission side is eliminated, and the data transmission side is synchronized with reception of the transfer unit data based on the clock signal If the data taking instruction signal et transmitted is not detected, the clock synchronous serial data transfer method, characterized in that determines that data transfer from the data transmission side to the data receiving side has been completed. The data reception is performed every time N (N is a positive integer of at least 1) pieces of data constituting transfer data transmitted for data transfer from the data transmission side to the data reception side in synchronization with the clock signal. A data capture instruction signal for instructing the data capture timing to each side is transmitted from the data transmission side to the data reception side in synchronization with the data, and the data transmission side transmits the data transmission The transmission of the clock signal is further continued until the transmission of the same number of clock pulses as the number of clock pulses necessary for transmission of one transfer unit data is completed even after the transmission of the last data transferred from the side is completed. The data receiving side stops transferring the data from the data transmitting side, and based on the clock signal, the data receiving side When the data capture instruction signal transmitted from the data transmission side is not detected in synchronization with the reception of the data and the transfer data end signal is detected, the data transfer from the data transmission side to the data reception side is completed. A clock-synchronized serial data transfer system characterized by determining that the 4. The clock synchronous serial data transfer system according to claim 1, wherein the data is byte-structured data. 4. The clock synchronous serial data transfer system according to claim 1, wherein the data is word-structured data. A first system that is a CPU system that transmits data to be transferred, and a second system that receives the data transmitted from the first system as transfer data, the first system comprising: ,
(A) a memory in which the data is stored in units of bytes;
(B) a serial data transmission unit for inputting the data as parallel data in units of bytes and transmitting the data as serial data to the second system;
(C) sequentially reading the data, which is the parallel data in byte units, from the memory in byte units, outputting the read transfer data to the serial data transmission unit, and controlling the transfer data transmission operation of the serial data transmission unit A first CPU that performs
The second system comprises:
(D) a serial data receiving unit that receives the data transmitted as serial data from the first system and outputs parallel data in units of bytes;
(E) a second memory for storing the data in bytes transmitted from the first system;
(F) a second CPU that controls a transfer data reception operation of the serial data reception unit, inputs the data in byte units output from the serial data reception unit, and sequentially writes the data in the memory;
Comprising the serial data receiving unit,
(G) a shift register for storing the received 1-byte serial data;
(H) a counter that counts the number of clock pulses of the clock signal output from the serial data transmission unit;
(I) a data capture instruction signal detector for detecting a data capture instruction signal;
A clock-synchronized serial data transfer system characterized by comprising:

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