JP2000232371A - Serial/parallel conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a parallel data synchronized with its own device clock and also to reduce delay time by converting the clock frequency of a serial data transmitter into a clock frequency of its own device at a serial data transmission rate. SOLUTION: This circuit is provided with a 1st register 2 which writes and stores output data of a clock/data recovery circuit 1 in turn and reads the data in the writing order and a 2nd register 3 which writes data read from the register 2 in a clock obtained by multiplying the clock of its own device by one bit at a time and collectively reads n bits in the clock of the self-device. It is further provided with a multiplication circuit 9 which inputs the clock of the its own device, multiplies it by n times and outputs it, and a frequency dividing circuit 8 which inputs a timing signal outputted from a read control circuit 7 generates a clock to the register 3 and the clock of its own device multiplied by (n) times, and performs frequency division of the multiplied clock into 1/n and generates the clock of the register 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a serial / parallel conversion circuit for converting serial data synchronized with an input clock into parallel data synchronized with an output clock.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional serial / parallel conversion circuit. The serial / parallel conversion circuit of this example is a circuit that converts serial data into n-bit parallel data. Also, assume that n bits are 1 byte.

The conventional serial / parallel conversion circuit extracts a clock component from serial data, synchronizes the extracted clock with data, and outputs the clock in synchronization with the extracted clock. From the first register 202 which stores n bits or more and outputs n-bit parallel data, the second register 203 which stores n-bit data, and the data stored in the first register 202. A synchronization detection circuit 204 for detecting a synchronization signal and determining the start of byte data is provided, and a frequency division circuit 205 for dividing the clock extracted by the clock / data recovery circuit 201 into 1 / n.

The transmitted serial data is first
Input to the clock / data recovery circuit 201. The clock / data recovery circuit 201 extracts a clock component of the input serial data from the input serial data, synchronizes the input serial data with the serial data, and synchronizes the extracted clock with the clock synchronized with the clock. Output.

[0005] The serial data output from the clock / data recovery circuit 201 is written into a first register 202.

[0006] The synchronization signal detection circuit 204 detects a predetermined specific n-bit synchronization signal from the data written in the first register 202 in order to detect a byte break from the arrangement of bit strings. First register 20
If a synchronization signal is detected from the two, the first register 202 is controlled so as to output n-bit data every n bits based on the synchronization signal. In terms of time, parallel data is output from n bits of the serial data to the n bits at a time.

[0007] Further, the synchronization detection is performed, and the n-bit data output from the first register 202 is stored in the second register 203.

The clock extracted by the clock / data recovery circuit 201 is divided by the frequency dividing circuit 205 into 1 / n. The clock divided by the dividing circuit 205 is used as a clock of the second register. Second register 2
The output 03 is parallel-converted data and is output in synchronization with the clock of the serial data transmission source device.

As described above, the conventional serial / parallel conversion circuit is composed of one LSI, and the data output from the LSI is the clock frequency of the device that transmitted the serial data. There has been a problem that a means for converting the clock into its own device is required.

FIG. 5 shows a method of synchronizing output data of the serial / parallel conversion circuit shown in FIG. 4 with its own clock.

FIG. 5 includes the serial / parallel conversion circuit 206 and the FIFO 207 shown in FIG.

The serial / parallel conversion circuit 206 receives serial data and outputs parallel data and a clock synchronized therewith. The output data and clock operate at the frequency of the clock of the device that transmitted the serial data.

The data output from the serial / parallel conversion circuit 206 is
Is written into the FIFO 207 with the clock output from the. The FIFO 207 stores its own clock in FIFO2.
07 as a read clock. FIFO2
In step 07, after the data is sufficiently written, the data is read out with the clock of the own device, and the parallel data frequency is converted from the clock frequency of the device that transmitted the serial data to the clock frequency of the own device.

As described above, in the conventional serial / parallel conversion circuit, since the clock frequency of the device that transmitted the serial data at the frequency of the parallel data was converted into the frequency of the device itself, the conversion from the clock frequency of the device to the frequency of the device itself was performed. There is a problem that time is several times longer than the cycle of parallel data.

Let T be the time of one bit of parallel data, that is, the machine cycle of the apparatus. The delay time in the clock / data recovery circuit 201 is tCDR, and the delay time in the first register 202 is T + T / n (where T / n is
Time from when the synchronization signal is completely written to the first register 202 to when writing to the second register 203 is started. The delay time in the second register 203 is T, and the delay time in the FIFO 207 is 2T (provided that the accuracy of the clock frequency of the device transmitting the serial data and that of the device itself are ± 100 ppm, respectively).
In this case, since two FIFO stages are required), the time from when the serial data is input to the serial / parallel conversion circuit until it is converted into the clock of the own device is tCDR + T + T / n + T + 2T (Equation 2) Become.

[0016]

The serial / parallel conversion circuit of the prior art described above is composed of one LSI, and the parallel data output from the LSI is the clock frequency of the device that transmitted the serial data. A means for converting the clock to its own device outside the serial / parallel conversion LSI is required. Further, since a delay time shown in Expression 2 is required to obtain parallel data synchronized with the clock of the own device, it is necessary to reduce this delay time.

Accordingly, it is an object of the present invention to obtain parallel data synchronized with the clock of the own device and to reduce the delay time shown in Expression 2.

[0018]

According to the present invention, a serial / parallel converter for converting serial data synchronized with an input clock into parallel data synchronized with an output clock extracts a clock component from the input serial data. A clock / data recovery circuit, a delimiter detection circuit that recognizes from the beginning to the end of the serial data packet, and a shift register function of sequentially writing the serial data with the input clock;
A first register for reading the output clock sequentially from the first data to which the writing has been performed by a clock obtained by multiplying the output clock by the transmission speed of the serial data, a write control circuit for writing to the first register, A read control circuit that performs read control from a register, a second register that stores data read from the first register, and outputs the data as parallel data;
A multiplying circuit for multiplying the output clock to a speed responsive to the transmission speed of the serial data, and a frequency dividing circuit for dividing the clock multiplied by the multiplying circuit to the output clock; Are parallelized at a low speed, and parallel data synchronized with an output clock is output.

In the above serial / parallel conversion circuit, the serial data is sequentially transmitted as one packet including a start delimiter, a data part, and an end delimiter in units of n (n is a positive integer) bits. The input delimiter detection circuit detects the start delimiter and the end delimiter.

Referring to FIG. 1, the serial / parallel conversion circuit according to the present invention employs a clock / clock converter for extracting a clock component from input serial data.
The data recovery circuit 1, the delimiter detection circuit 5 for recognizing the entire packet from the beginning to the end, the function of a shift register for sequentially writing the input serial data with the clock of the input serial data, and the writing were performed. A first register capable of reading the clock of its own device in order from the first data with a clock multiplied by the transmission speed of the serial data, a write control circuit 6 of means for writing to the register, and read control from the register A read control circuit 7, a second register for storing data read from the first register and outputting the data as parallel data, and a means for multiplying the clock of its own device to the transmission speed of serial data. The multiplication circuit 9 and the multiplied clock are used as the original frequency. And a frequency divider 8 means returning,
It is characterized in that input serial data is parallelized with low latency, output at the clock frequency of its own device.

In particular, the present invention is characterized in that the clock frequency of the serial data transmitting device is converted into the clock frequency of the own device at the transmission speed of the serial data.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.

[Configuration of this Embodiment] FIG. 1 is a configuration diagram showing an embodiment of the present invention. Here, it is assumed that serial data obtained by serializing data in units of n bits into 1-bit data that is n times faster is input to the serial / parallel conversion circuit. The serial / parallel conversion circuit is a circuit that converts serial data into n-bit parallel data at 1 / n the speed of serial data.
Also, a description will be given assuming that n bits are 8 bits of 1 byte.

The data to be transmitted is in a packet format as shown in FIG. 2, and a start delimiter of a delimiter indicating the head of the packet is added to the head of the packet. At the end of the packet, an end delimiter of a delimiter indicating the end of the packet is added. These delimiters are as long as one byte of data, ie, n
It shall consist of bits.

Referring to FIG. 1, the serial / parallel conversion circuit according to the present embodiment extracts a clock component from serial data, synchronizes the extracted clock with data, and outputs the clock and data. A first register 2, which is a shift register capable of writing and storing output data of the data recovery circuit 1 in order and reading data in the order in which the data was written, and data read from the first register 2 by 1 bit in the own device. F which writes with a clock multiplied by the clock and reads out with the clock of its own device (output) collectively for n bits
A second register 3 which is an IFO.

Further, a delimiter detection circuit 5 for detecting a start delimiter and an end delimiter indicating the beginning and end of a packet from the data stored in the first register 2, and a start delimiter detected by the delimiter detection circuit 5 Thus, writing of data of n bits or more to the first register 2 is permitted, and the delimiter circuit 5
The end delimiter is detected in step (1), so that the writing of data to the first register 2 is stopped, and the signal indicating the state of packet writing to the first register 2 is output. And a control circuit 6.

Also, upon receiving a signal from the write control circuit 6 indicating that the writing of the packet to the first register has started, the difference between the clock frequency of the device that transmitted the serial data and the clock frequency of the device itself is sufficiently absorbed. And a read control circuit 7 that adjusts the timing of reading data from the first register 2 and outputs a timing signal for generating a clock to the second register 3.

Further, a multiplying circuit 9 for inputting the clock of its own device, multiplying the input clock by n times and outputting the same.
And a timing signal output from the read control circuit 7 for generating a clock to the second register 3 and a clock of the own device multiplied by n by the multiplication circuit 9 and input n A frequency dividing circuit 8 for dividing the frequency of the doubled clock by 1 / n and generating a clock for the second register 3;

The parallel data is signal-processed by the signal processing circuit shown in the apparatus itself, and also outputs the clock output of the frequency dividing circuit 8 synchronized with the clock of the apparatus and is supplied to the signal processing circuit. You.

[Operation of this Embodiment] The operation of the embodiment shown in FIG. 1 will be described below. As described in the configuration of the present embodiment, here, serial data obtained by serializing n-bit data into 1-bit data which is n times faster than the output parallel data is subjected to this serial / parallel conversion. It shall be input to the circuit. The serial / parallel conversion circuit is a circuit that converts serial data into n-bit parallel data at 1 / n the speed of serial data. Also, assume that n bits are 1 byte.

The data to be transmitted has a packet format as shown in FIG. 2, and a delimiter indicating the head of the packet and a start delimiter are added to the head of the packet.
A delimiter indicating the end of the packet and an end delimiter are added to the end of the packet. These delimiters have the same length as one byte of data, that is, have n bits.

Serial data obtained by serializing n-bit data into 1-bit data which is n-times faster and transmitted is first input to the clock / data recovery circuit 1. The clock / data recovery circuit 1 extracts a clock component of the input serial data, and synchronizes the input serial data with the extracted input clock and outputs it. The serial data output from the clock / data recovery circuit 1 is input to the first register 2. The input clock is output to the first register 2, the delimiter detection circuit 5, and the write control circuit 6.

The serial data from the clock / data recovery circuit 1 is written into the first register 1 by an input clock output from the clock / data recovery circuit 1 in synchronization with the serial data. The first register 2 is a shift register, and writes and stores serial data in order.

The number of stages of the shift register of the first register 2 is determined as follows. For example, assuming that the system clock including the transmitting device and the own device is 100 MHz, the frequency difference between the input clock and the own device clock is generally ± 10%.
Since it is 0 ppm, the frequency difference between the clock of the transmitting apparatus and the clock of its own apparatus is ± 200 ppm, and the maximum value of one clock, that is, 10 ns, between the clocks of the transmitting apparatus and its own apparatus is 2 ps. Assuming that the number n of parallel bits is 10, the frequency of serial data is 1 GHz, that is, 1 ns. One bit of serial data is shifted when 500 bits of serial data are read. 500 bits of serial data correspond to a time of 50 bytes of parallel data.

If the packet length shown in FIG. 2 is limited to 500 bytes or less, the number of stages of the first shift register 2 is required to be 22 and reading of data is started when data is written to the eleventh stage. . It is assumed that the number of write stages of the shift register from which data reading is started is r (r = 11 in this example). The packet length can be increased by 50 bytes by increasing the number of stages of the shift register by two and delaying the data read start point by one stage.

The number of data bits to be written into the first register 2 is limited to n bits, which is the length of the delimiter, until the delimiter detection circuit 5 detects the start delimiter. The serial data written in the first register 2 is checked by the delimiter detection circuit 5 to determine whether the data is a delimiter. There are two types of delimiters, a start delimiter that indicates the beginning of a packet and an end delimiter that indicates the end of the packet, and has a bit pattern configuration that is distinguished from data. Confirmation of the delimiter
For example, each time one bit of serial data written in the first register 2 is written, the serial data is checked against a delimiter pattern. At the beginning of serial data transmission, the function of detecting the start delimiter works first. When the delimiter detection circuit 5 recognizes that the start delimiter has been written to the first register 2, it reports to the write control circuit 6 that the start delimiter has been detected.

The write control circuit 6, which has been notified that the start delimiter has been written to the first register 2,
Writing of serial data of n bits or more to the first register 2 is permitted, that is, writing of a packet is permitted.

The write control circuit 6 includes the first register 2
When the writing of the packet is permitted, the reading control circuit 7 is notified that the packet has been written.

The read control circuit 7 having received a report that writing of a packet to the first register 2 is permitted.
Performs control to read out data written in the first register 2 in the order in which the data is written, with a clock which is n times the clock of the own device. A clock that is n times as large as the clock of the own device is generated by multiplying the clock of the own device by n by the multiplier circuit 9.

As shown in FIG. 3, the serial data read from the first register 2 is: (a) the first register 2 has b1-br bit registers, and the second register 3 has bit There are 1 to n parallel output registers,
(B) includes bits 1 to n of the second register 3
2 shows how the data is written in order. The second register 3 is an n-bit FIFO having a depth of 3 bits or more.

The serial data written in the second register 3 is read from the time when the n-bit serial data is written until the time when the next n-bit serial data is written. The generation of this read clock
A control signal in consideration of the write timing to the second register 3 is output from the read control circuit 7 to the frequency dividing circuit 8, and the clock of the own device multiplied by n by the frequency multiplying circuit 9 is divided by 1 / n. It is made.

The second register 3 outputs n-bit parallel data. Further, a clock having the same frequency as that of the own device synchronized with the parallel data is output from the frequency dividing circuit 8.

The first register 2 in the delimiter detection circuit 5
Detects that the end delimiter indicating the end of the packet has been written to the write control circuit 6, the delimiter detection circuit 5 reports the detection of the end delimiter to the write control circuit 6.

The write control circuit 6, which has been notified of the detection of the end delimiter, permits the first register 2 to write data up to the end delimiter, and thereafter performs control to limit writing to n bits. The write control circuit 6 requests the read control circuit 7 to stop reading.

When the read control circuit 7 receives the read stop request and reads the end delimiter,
The read operation from the first register 2 is stopped. After reading the end delimiter from the second register 3, the output of the control signal to the frequency divider 8 is stopped.

The delimiter detection circuit 5 that has detected the end delimiter from the first register 2 waits for the start delimiter of the next packet to be written in the first register 2. When it is detected that the start delimiter of the next packet has been written, the above-described operation is performed to convert serial data into parallel data.

[Effect of this Embodiment] The time of one bit of parallel data, that is, the machine cycle of the apparatus is T.
The delay time in the clock / data recovery circuit 1 is tCD
R, the delay time in the first register 2 is r = T + T / n
Assuming that the delay time in the second register 3 is r and the delay time in the second register 3 is 1.5T (when the packet length is 500 bytes), serial data is input to the serial / parallel conversion circuit. The time from when the clock is converted to the clock of the own device is tCDR + T + T / n + 1.5T (Equation 1).

In a conventional parallel / serial conversion circuit,
The time from the conversion of the serial data into the parallel data and the synchronization with the clock of the own device is tCDR + T + T / n + T + 2T (Equation 2) as shown in (Equation 2).

Therefore, according to the present invention, there is an effect that 1.5T can be reduced.

This effect is obtained because the FIFO control is performed at the transmission speed of the serial data in the first register 2, so that the input clock of the device that transmitted the serial data at high speed is converted into the clock of the device itself. is there.

Since the parallel data output from the serial / parallel conversion circuit of the present invention is output at the clock frequency of its own device, the clock frequency required as an external circuit in a conventional serial / parallel conversion LSI is required. There is an effect that a circuit for conversion is not required.

The effect is that the output from the first register 2 is n times the clock frequency of its own device,
This is because the register 3 performs parallelization and outputs data at the clock frequency of the own device.

[0053]

According to the present invention, when the input clock is converted into parallel data synchronized with the clock of the own device, the data can be read with the delay time of the serial / parallel conversion circuit reduced. In particular, using a FIFO that can write and read data at high speed to and from a second register that converts serial data into parallel data and its driving circuit, the delay time due to parallelization is compressed, and the parallel data synchronized with the clock of the own device is compressed. Obtainable.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a serial / parallel conversion circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a structure of serial data input to a serial / parallel conversion circuit according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of an operation of a FIFO according to the embodiment of the present invention.

FIG. 4 is a configuration block diagram of a conventional serial / parallel conversion circuit.

FIG. 5 is a configuration block diagram of a conventional serial / parallel conversion circuit.

[Explanation of symbols]

 1,201 Clock / data recovery circuit 2,202 First register 3,203 Second register 5 Delimiter detection circuit 6 Write control circuit 7 Read control circuit 8 Divider circuit 9 Multiplier circuit 204 Synchronous circuit 205 Divider circuit 206 Serial / Parallel conversion circuit 207 FIFO

Claims (4)

[Claims] 1. A serial / parallel conversion circuit for converting serial data synchronized with an input clock into parallel data synchronized with an output clock, comprising: a clock / data recovery circuit for extracting a clock component from input serial data; A delimiter detection circuit for recognizing from the beginning to the end of the packet of the serial data, a function of a shift register for sequentially writing the serial data with the input clock, and serially outputting the output clock from the first data on which the writing is performed. A first register that reads with a clock multiplied by the transmission speed of the first register, a write control circuit that writes to the first register, a read control circuit that performs read control from the first register, and the first register Data read from A second register for storing the output clock as parallel data, a multiplying circuit for multiplying the output clock to a speed responsive to the transmission speed of the serial data, and dividing the clock multiplied by the multiplying circuit into the output clock. A serial / parallel conversion circuit, comprising: a frequency dividing circuit that converts input serial data into parallel data at a low speed and outputs parallel data synchronized with an output clock. 2. The serial / parallel conversion circuit according to claim 1, wherein the serial data includes one packet of a start delimiter, a data part, and an end delimiter in units of n bits (n is a positive integer). A serial / parallel conversion circuit, wherein the delimiter detection circuit detects the start delimiter and the end delimiter. 3. The serial / parallel conversion circuit according to claim 1, wherein said second register comprises a FIFO, and stores a unit bit of said parallel data from said first register and said frequency dividing circuit. A serial / parallel conversion circuit for reading in accordance with a clock which is reduced to the unit bit of the output clock. 4. The serial / parallel conversion circuit according to claim 2, wherein said start delimiter and said end delimiter are composed of said n bits and have a predetermined pattern. circuit.