JP2007329670A - Data receiving device and data receiving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data receiving device that needs to have its hardware less corrected for format change of serial data to be transmitted. <P>SOLUTION: The data receiving device comprises a serial/parallel converting circuit 19 which converts the serial data into parallel data and outputs them; a flag bit adding circuit 20 which adds the value of a data effective/ineffective decision signal as a flag bit when the parallel data are input; and passes parallel data with a flag bit as they are when the parallel data with the flag bit are input to output the parallel data with the flag bit; a parallel data latch circuit 21 which inputs the parallel data with the flag bit; and a data output/discarding decision circuit 22 which inputs the parallel data with the flag bit from the parallel data latch circuit 21, and outputs or discards the data based upon the value of the flag bit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data receiving apparatus and a data receiving method.

  Data transfer methods are roughly classified into parallel transfer using a parallel data bus and serial transfer using a serial data bus. Parallel transfer is suitable for high-speed data transfer, but leads to an increase in the number of pins of devices such as microcomputers and ICs. One serial data transfer that leads to a reduction in the number of pins is one that uses a 5-wire serial interface. Data transfer between a data transmission device and a data reception device using a 5-wire system will be described by taking audio data as an example. First, the data receiving device outputs a data request signal to the data transmitting device. Based on the data request signal, the data transmitting device outputs an audio data (serial data) signal, a valid / invalid data determination signal, a clock signal, and a data / word boundary determination clock signal. The data receiving device takes in the audio data into the device, converts it into a parallel format, determines the validity / invalidity of the data from the level of the valid / invalid data decision signal, and takes in / discards in units of double words. The word unit of data is obtained from the data / word boundary determination clock signal. After the capturing / discarding process is performed, the data is stored in a data storage memory inside the data receiving apparatus.

  Some serial data transfer uses a three-wire serial interface (see, for example, Patent Document 1). In data transfer using the three-wire system, a serial data signal, a data / word boundary determination clock signal, and a transfer clock signal are output from the data transmission device. In this case, it is necessary to perform data processing by changing the data format, such as embedding information for determining the validity / invalidity of data in a serial data signal.

However, the conventional data receiving device in serial data transfer as described above cannot flexibly cope with the format change of the transmitted data, and the hardware of the data receiving device every time the specification of the data transmitting device is changed. There was a problem that it was necessary to fix the wear.
JP-A-8-251228

  Therefore, an object of the present invention is to provide a data receiving apparatus that can flexibly cope with a change in data format accompanying a change in specifications of the data transmitting apparatus and can reduce hardware modification.

  A data receiving apparatus according to an aspect of the present invention includes a first, second, third, fourth, and fifth external terminals and a request signal that is connected to the first external terminals and that can output a data transfer request signal A data acquisition timing generation circuit that is connected to the generation circuit and the second and third external terminals and that receives the clock signal and the data / word boundary determination signal to generate and output the first and second data acquisition timing signals. Serial data connected to a circuit and the fourth external terminal, given the first data capture timing signal, and capturing the serial data signal and converting it into parallel data, or including a first flag bit A serial parameter with a first flag bit, which is a signal, is converted into parallel data with a first flag bit and output. When the parallel data is output from the serial conversion circuit and the serial / parallel conversion circuit, a data valid / invalid determination signal is given via the fifth external terminal and added as a second flag bit, 2 flag bit-added parallel data, and when the first flag bit-added parallel data is output, the flag bit addition circuit for outputting the first flag bit-attached parallel data, and the second data fetching A parallel data latch circuit that captures the first or second flag bit-attached parallel data based on a timing signal; and the parallel data latch circuit that captures the first or second flag bit-attached parallel data; Based on the value of the second flag bit, the parallel data with the first or second flag bit is output. Or discard the data output and discarding decision circuit, in which comprises a.

  The data receiving apparatus according to one aspect of the present invention is connected to the first, second, third, fourth, and fifth external terminals and the first external terminal, and can output a data transfer request signal. A data acquisition unit which is connected to the request signal generation circuit and the second and third external terminals, and receives the clock signal and the data / word boundary determination signal to generate and output the first and second data acquisition timing signals. A timing generation circuit, connected to the fourth external terminal, provided with the first data capture timing signal, captures a serial data signal and converts it into parallel data, or includes a first flag bit; A serial data signal which is a serial data signal with a first flag bit taken in, converted into parallel data with a first flag bit and output A parallel conversion circuit; a first register circuit capable of outputting a first control signal based on set information; a fixed value output circuit capable of outputting a fixed value; and a plurality of signals based on the first control signal. A selector capable of selecting and outputting one signal from the input signal, and when the parallel data is output from the serial-parallel conversion circuit, the selector is connected to the fixed value and the fifth external terminal. The data valid / invalid determination signal is given, the second flag bit having the selected value is added to the parallel data, and the second flag bit parallel data is output, and the first flag bit parallel data is output. Is output based on a flag bit addition circuit for outputting the first flag bit-attached parallel data and the second data fetch timing signal. A parallel data latch circuit that takes in the parallel data with 1 or 2 flag bits, a second register circuit that outputs a second control signal based on the set information, a buffer unit, a buffer data cancel flag generation unit, A data output / discard determination unit that fetches the parallel data with the first or second flag bit from the parallel data latch circuit into the buffer unit, and the buffer data cancel flag generation unit receives the second control signal Based on the given first or second flag bit, it is determined whether or not to set a buffer data cancel flag. When the buffer data cancel flag is set, the data output / discard determination unit The second parallel data with flag bit is discarded and the buffer data can When the cell flag is not set, the data output / discard determination unit includes a data output / discard determination circuit that outputs the first or second parallel data with flag bits.

  A data reception method according to an aspect of the present invention includes a request signal generation circuit, a data capture timing generation circuit, a serial / parallel conversion circuit, a flag bit addition circuit, a parallel data latch circuit, a buffer unit, a buffer data cancel flag generation unit, and a data output A data reception method using a data output / discard determination circuit including a discard determination unit, a data storage memory, and a data reception device having first, second, third, fourth, and fifth external terminals, The data fetch timing generation circuit generates and outputs the first and second data fetch timing signals from the clock signal and the data / word boundary determination signal supplied via the second and third external terminals, and the request A data transfer request signal is generated by a signal generation circuit, and the signal is generated via the first external terminal. When outputting, the serial / parallel conversion circuit to which the first data capture timing signal is applied captures a serial data signal via the fourth external terminal, converts it into parallel data, outputs it, and outputs the request When the data transfer request signal is not generated by the signal generation circuit, the serial data including the first flag bit via the fourth external terminal by the serial / parallel conversion circuit to which the first data capture timing signal is applied When a serial data signal with a first flag bit, which is a signal, is taken in, converted into parallel data with a first flag bit and output, and the serial / parallel conversion circuit outputs the parallel data, the flag bit addition circuit The data given through the fifth external terminal The value of the validity / invalidity determination signal is added as a second flag bit, parallel data with a second flag bit is output, and the parallel data latch circuit to which the second data fetch timing signal is applied provides the first or The parallel data with the second flag bit is taken in, the parallel data with the first or second flag bit is taken into the buffer unit from the parallel data latch circuit by the data output / discard judgment circuit, and the buffer data cancel flag generation The unit determines whether to set the buffer data cancel flag to the first or second parallel data with the flag bit based on the first or second flag bit, and sets the buffer data cancel flag. The data output / discard determination unit performs the first control. Alternatively, when the second parallel data with flag bit is discarded and the buffer data cancel flag is not set, the data output / discard determination unit outputs the first or second parallel data with flag bit, and the data Storing the parallel data with the first or second flag bit output from the output / discard determination unit by a storage memory.

  ADVANTAGE OF THE INVENTION According to this invention, it can respond flexibly to the change of the data format accompanying the specification change of a data transmission apparatus, and can reduce hardware correction.

  Embodiments of a data receiving apparatus according to the present invention will be described below with reference to the drawings.

  FIG. 1 shows a schematic configuration of a data receiving apparatus according to an embodiment of the present invention. The data receiving apparatus 10 includes a request signal generation circuit 17 that outputs a data transfer request signal, a data storage timing generation circuit 18 that outputs a timing signal for capturing data, and a serial / parallel conversion circuit 19 that converts serial data into parallel data. , A flag bit adding circuit 20 for adding a flag bit, a parallel data latch circuit 21 for fetching parallel data to which a flag bit is added, a data output / discard determination circuit 22, a data storage memory 23, internal registers 24 and 25, an external terminal T1 To T5.

  First, data transfer through a 5-wire interface using this data receiving apparatus will be described. The data receiving device 10 and the data transmitting device 11 have five signal lines: a data transfer request signal line 12, a data / word boundary determination clock signal line 13, a clock signal line 14, a data signal line 15, and a valid / invalid data determination signal line 16. Are connected via a serial bus.

  The request signal generation circuit 17 outputs a data transfer request signal to the data transmission device 11 via the external terminal T1 and the data transfer request signal line 12 when the data reception device 10 is ready to receive data. As shown in FIG. 2, when a data transfer request signal is input, the data transmission device 11 outputs a data / word boundary determination clock signal, a clock signal, a data signal, and a valid / invalid data determination signal.

  Each signal passes through the data / word boundary determination clock signal line 13 and the external terminal T2, the clock signal line 14 and the external terminal T3, the data signal line 15 and the external terminal T4, the valid / invalid data determination signal line 16 and the external terminal T5. Input to the data receiving apparatus 10. The data / word boundary determination clock signal transitions from 0 to 1 or from 1 to 0 for each word of serial data. The data signal to be transmitted is invalid data when the value of the valid / invalid data determination signal is 0, and is valid data when the value is 1.

  Data signal processing in the data receiving apparatus 10 will be described with reference to FIG. Based on the timing signal generated by the data storage timing generation circuit 18, one word 26 of the data signal (serial data) output from the data transmission device 11 is taken into the serial / parallel conversion circuit 19 and converted into parallel data 27. Converted. The flag bit 28 is added to the parallel data 27 by the flag bit addition circuit 20. As the value of the flag bit 28, either the value of the valid / invalid data determination signal or the output value of the fixed value output circuit 30 is selected by the switch (multiplexer) 34 according to the setting of the internal register 24. For example, when the internal register 24 is set to 0, the output value of the fixed value output circuit 30 is selected, and when it is set to 1, the value of the valid / invalid data determination signal is selected. In the present embodiment, the fixed value is 0. The internal register 24 can be set by the user.

  The parallel data to which the flag bit 28 is added (parallel data 29 with flag bit) is stored in the parallel data latch circuit 21 based on the timing signal generated by the data storage timing generation circuit 18.

  The processing of the parallel data 29 with flag bits will be described with reference to FIG. In the data output / discard determination circuit 22, parallel data 29 with flag bits is taken into the data buffer 31. Here, when the internal register 25 is set to determine whether the data fetched into the data buffer 31 is valid or invalid and the flag bit 28 indicates invalid data (the value of the flag bit is 0), In the cancel flag generation circuit 32, a buffer data cancel flag 33 is generated and set. When the internal register 25 is not set to determine whether the data fetched into the data buffer 31 is valid or invalid, or when the flag bit 28 indicates valid data (the value of the flag bit is 1), the buffer data The cancel flag 33 is not generated.

  The data output / discard determination unit 34 determines whether or not the buffer data cancel flag 33 is set. If not, the data in the data buffer 31 is output to the data storage memory 23 in units of double words, as shown in FIG. Stored in the format shown. If the buffer data cancel flag 33 is set, the data in the data buffer 31 is discarded. Data is discarded by advancing the pointer value of the data buffer without outputting data. After the data output or data discard is completed, the buffer data cancel flag 33 is cleared.

  For example, when the internal register 25 is set to 1, the validity / invalidity of the data fetched into the data buffer 31 is determined, and when it is set to 0, it is not determined. When the internal register 25 is set to 0, the buffer data cancel flag 33 is not generated, so that the data 29 captured in the data buffer 31 is output to the data storage memory 23 without being discarded. become.

  Next, data transfer via a three-wire serial interface using the data receiving apparatus according to the above embodiment will be described. A schematic configuration of the data receiving apparatus is shown in FIG. The data receiving device 10 and the data transmitting device 11 are connected via a serial bus including three signal lines: a data / word boundary determination clock signal line 13, a clock signal line 14, and a data signal line 15. A bus is not connected to the external terminals T1 and T5, and the data receiving apparatus 10 includes the request signal generation circuit 17, but does not generate or output a data transfer request signal.

  As shown in FIG. 7, the data transmission device 11 adds a flag bit to each word data and outputs the data. This flag bit has data valid / invalid information. Data signal processing in the data receiving apparatus 10 will be described with reference to FIG. A data signal (serial data with flag bits) 40 having a data part 41 and a flag bit part 42 output from the data transmitting apparatus 11 is serially parallel based on the timing signal generated by the data storage timing generation circuit 18. The data is taken into the conversion circuit 19 and converted into parallel data 43 with flag bits. The parallel data 43 with flag bits passes through the flag bit addition circuit 20 and is stored in the parallel data latch circuit 21 based on the timing signal generated by the data storage timing generation circuit 18.

  The processing of the parallel data 43 with flag bits will be described with reference to FIG. In the data output / discard determination circuit 22, the parallel data 43 with flag bits is taken into the data buffer 31. When the internal register 25 is set to determine whether the data 43 fetched into the data buffer 31 is valid / invalid and the flag bit 42 indicates invalid data, the cancel flag generation circuit 30 uses the buffer data cancel flag. 33 is generated and set. When the internal register 25 is not set to determine whether the data fetched into the data buffer 31 is valid or invalid, or when the flag bit 42 indicates valid data, the buffer data cancel flag 33 is not generated.

  The data output / discard determination unit determines whether or not the buffer data cancel flag 33 is set. If it is set, the data in the data buffer 31 is discarded. If the buffer data cancel flag 33 is not set, the data in the data buffer 31 is output to the data storage memory 23 in units of double words and has the same format as in the case of data transfer through a 5-wire serial interface as shown in FIG. Stored in After the data output or data discard is completed, the buffer data cancel flag 33 is cleared.

  Use a data receiving device having the same configuration as the data receiving device for data transfer using a 5-wire serial interface, and set the data output from the serial / parallel conversion circuit 19 to pass through the flag bit adding circuit 20. Thus, data transfer can be performed via a three-wire serial interface.

  As described above, the data receiving apparatus according to the embodiment of the present invention can flexibly cope with a change in the specification of the data transmitting apparatus and a change in the format of the data to be transmitted without performing a large hardware correction of the data receiving apparatus.

  The above-described embodiments are examples and should not be considered as limiting. For example, in the above-described embodiment, the validity / invalidity of data is determined by the lower 1 bit of the flag bits, but may be 2 bits or more. Further, when data transfer is performed using a 3-wire serial interface, as shown in FIG. 10, the output data of the serial / parallel conversion circuit is directly input to the parallel data latch circuit without passing through the flag bit addition circuit. Such a configuration may be adopted. Further, data transfer to the data storage memory may not be performed in units of double words.

  The data receiving apparatus according to the above embodiment can be used for receiving various data transferred serially, and can be used for transferring audio data, for example. In this case, the data / word boundary determination signal is a signal for identifying the L channel signal and the R channel signal. The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic block diagram of the data receiver by embodiment of this invention. It is a figure which shows an example of the state transition of each signal. It is a schematic block diagram of the data receiver by the same embodiment. It is a schematic block diagram of the data receiver by the same embodiment. It is a figure which shows the data storage format by the embodiment. It is a schematic block diagram of the data receiver by the same embodiment. It is a figure which shows an example of the state transition of each signal. It is a schematic block diagram of the data receiver by the same embodiment. It is a schematic block diagram of the data receiver by the same embodiment. It is a schematic block diagram of the data receiver by a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Data receiver 11 Data transmitter 12 Data transfer request signal line 13 Data word boundary determination clock signal line 14 Clock signal line 15 Data signal line 16 Data transfer start signal line 17 Request signal generation circuit 18 Data storage timing generation circuit 19 Serial Parallel conversion circuit 20 Flag bit addition circuit 21 Parallel data latch circuit 22 Data output / discard determination circuit 23 Data storage memory 24, 25 Internal register 30 Cancel flag generation circuit 31 Data buffer

Claims (5)

First, second, third, fourth and fifth external terminals;
A request signal generation circuit connected to the first external terminal and capable of outputting a data transfer request signal;
A data capture timing generation circuit connected to the second and third external terminals, and supplied with a clock signal and a data / word boundary determination signal to generate and output first and second data capture timing signals;
A serial data signal connected to the fourth external terminal and provided with the first data capture timing signal to capture the serial data signal and convert it into parallel data, or includes a first flag bit A serial-parallel conversion circuit that takes in a serial data signal with a first flag bit, converts it into parallel data with a first flag bit, and outputs it;
When the parallel data is output from the serial / parallel conversion circuit, a data valid / invalid determination signal is given via the fifth external terminal and added as a second flag bit, with a second flag bit. A flag bit adding circuit that outputs parallel data and outputs the first flag bit parallel data when the first flag bit parallel data is output;
A parallel data latch circuit for fetching the parallel data with the first or second flag bit based on the second data fetch timing signal;
The parallel data with the first or second flag bit is fetched from the parallel data latch circuit, and the parallel data with the first or second flag bit is output or discarded based on the value of the first or second flag bit. Data output / discard judgment circuit
A data receiving apparatus comprising: First, second, third, fourth and fifth external terminals;
A request signal generation circuit connected to the first external terminal and capable of outputting a data transfer request signal;
A data capture timing generation circuit connected to the second and third external terminals, and supplied with a clock signal and a data / word boundary determination signal to generate and output first and second data capture timing signals;
A serial data signal connected to the fourth external terminal and provided with the first data capture timing signal to capture the serial data signal and convert it into parallel data for output, or includes a first flag bit A serial-parallel conversion circuit that takes in a serial data signal with a first flag bit, converts it into parallel data with a first flag bit, and outputs it;
A first register circuit capable of outputting a first control signal based on the set information;
A fixed value output circuit capable of outputting a fixed value; and a selector capable of selecting and outputting one signal from a plurality of input signals based on the first control signal, and the parallel data from the serial / parallel conversion circuit. Is output to the selector via the fixed value and the fifth external terminal, and a second flag bit, which is the selected value, is added to the parallel data. A flag bit adding circuit for outputting the second flag bit parallel data, and outputting the first flag bit parallel data when the first flag bit parallel data is output;
A parallel data latch circuit for fetching the parallel data with the first or second flag bit based on the second data fetch timing signal;
A second register circuit for outputting a second control signal based on the set information;
A buffer unit, a buffer data cancel flag generation unit, and a data output / discard determination unit; fetch the parallel data with the first or second flag bit from the parallel data latch circuit into the buffer unit; The generation unit determines whether or not to set a buffer data cancel flag based on the first or second flag bit when the second control signal is given, and when the buffer data cancel flag is set, the data When the output / discard determination unit discards the parallel data with the first or second flag bit and the buffer data cancel flag is not set, the data output / discard determination unit adds the first or second flag bit. A data output / discard determination circuit for outputting parallel data;
A data receiving apparatus comprising: A data storage memory for storing the parallel data with the first or second flag bit output from the data output / discard determination circuit;
3. The data receiving apparatus according to claim 1, wherein the first or second parallel data with flag bits is stored in the data storage memory in units of double words.   The serial data signal is an audio serial data signal in which an L channel signal and an R channel signal are alternately arranged, and the data word boundary determination signal is a clock signal for identifying the L channel signal and the R channel signal. The data receiving apparatus according to claim 1, wherein the data receiving apparatus is provided. Data output / discard including request signal generation circuit, data fetch timing generation circuit, serial / parallel conversion circuit, flag bit addition circuit, parallel data latch circuit, buffer unit, buffer data cancel flag generation unit and data output / discard determination unit A data receiving method using a data receiving device having a determination circuit, a data storage memory, first, second, third, fourth and fifth external terminals,
Generating and outputting first and second data capture timing signals by the data capture timing generation circuit from the clock signal and the data / word boundary determination signal applied via the second and third external terminals;
When the data transfer request signal is generated by the request signal generation circuit and is output through the first external terminal, the fourth parallel circuit is supplied with the first data capture timing signal. When the serial data signal is taken in via an external terminal, converted into parallel data and output, and when the data transfer request signal is not generated by the request signal generation circuit, the serial data to which the first data acquisition timing signal is given A first serial data signal with a flag bit, which is a serial data signal including a first flag bit, is captured by the parallel conversion circuit via the fourth external terminal, and converted into parallel data with the first flag bit. Output,
When the serial / parallel conversion circuit outputs the parallel data, the flag bit adding circuit adds the value of the data validity / invalidity determination signal given through the fifth external terminal as the second flag bit. , Output the parallel data with the second flag bit,
The parallel data latch circuit to which the second data capture timing signal is applied captures the parallel data with the first or second flag bit,
The data output / discard determination circuit fetches the parallel data with the first or second flag bit from the parallel data latch circuit into the buffer unit, and the buffer data cancel flag generation unit generates the first or second flag bit. Whether or not to set the buffer data cancel flag to the first or second parallel data with flag bits, and when the buffer data cancel flag is set, the data output / discard determination unit performs the first Alternatively, when the second flag bit parallel data is discarded and the buffer data cancel flag is not set, the first or second flag bit parallel data is output by the data output / discard determination unit,
Storing the first or second parallel data with flag bits output from the output / discard determination unit by the data storage memory.

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