JP5111020B2 - Image processing apparatus and control method thereof - Google Patents

Description

  The present invention relates to an image processing apparatus that converts register data or image data into a command and transfers the data through a transmission path that connects a plurality of image processing modules in series, and a control method thereof.

  Conventionally, an image processing apparatus having a configuration in which a plurality of image processing modules are connected in series via a data transmission path is known (Patent Document 1). As shown in FIG. 6, this type of image processing apparatus has a configuration in which image processing modules 601 to 604 are connected in series via a data transmission path 605. The register data and image data are converted into commands, flow on the data transmission path 605, and sequentially provided to the image processing modules 601 to 604.

Each image processing module determines whether or not it is a command to be processed by referring to the module ID described in the sent command. Only when it is determined that the command is to be processed, the command is processed, and after the image processing, the command is transmitted to the subsequent image processing module. If the command is not to be processed, the command is transferred to the subsequent image processing module without doing anything.
JP 2001-162894 A

  However, in the above-described prior art, commands corresponding to the number of image processing modules are required even when reading / writing the registers common to all the image processing modules. In particular, in the case of register reading, since the read result data is described in the command, it is necessary to prepare a command corresponding to each image processing module and to send the command to the data transmission path 605.

  The present invention has been made in view of the above problems, and an object of the present invention is to enable register read processing in all image processing modules with one register command.

In order to achieve the above object, an image processing apparatus according to an aspect of the present invention has the following arrangement. That is,
An image processing apparatus in which a plurality of processing modules that process commands including command identification information, module identification information, and command content information are connected in series,
Each of the plurality of processing modules is
Determining means for determining whether the command identification information of the input command indicates reading of data from the register and whether the module identification information of the command specifies a plurality of processing modules;
When the determination means determines that the command indicates reading of data from a register and designates a plurality of processing modules, the transfer means transfers the command as it is downstream;
Wherein said command by judging means indicates the reading of data from the register, when it is determined that specifies a plurality of processing modules, replace the module identification information of the command identification information of the processing module, the content information Generating means for describing the data read from the register and generating a new command;
Transmitting means for transmitting a new command generated by the generating means downstream.

A method for controlling an image processing apparatus according to an aspect of the present invention for achieving the above-described object is as follows:
A method for controlling an image processing apparatus in which a plurality of processing modules for processing a command including command identification information, module identification information, and command content information are connected in series.
Determination judging means of the processing module, and whether to show the reading of data from the command identification information of the inputted command register, and whether the module identification information of the command specifies a plurality of processing modules, the A determination step to
When the front Symbol said command determination step it is determined that specifies a plurality of processing modules indicate the reading of data from the register, a transfer step of transferring the command directly to the downstream,
When the previous SL determination process command is determined that specifies a plurality of processing modules indicate the reading of data from the register, replacing the module identification information of the command identification information of the processing module, the content information Generating a new command by describing the data read from the register; and
The transmission means of the said processing module is provided with the transmission process which transmits the new command produced | generated by the said production | generation process downstream.

  According to the present invention, register read processing in all image processing modules can be executed with a single register command, and the system can be expected to speed up by saving the command.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus according to the present embodiment.

  In FIG. 1, 101 is a CPU, 102 is a RAM, and 103 is a ROM. Reference numeral 104 denotes a first image processing module, 105 denotes a second image processing module, 106 denotes a third image processing module, and 107 denotes a fourth image processing module. Further, 108 is a first direct memory access controller (hereinafter referred to as DMAC 108), and 109 is a second direct memory access controller (hereinafter referred to as DMAC 108).

  The image processing modules 104 to 107 and the DMACs 108 and 109 are connected in series by a single transmission path 111, and the DMACs 108 and 109 are connected to the CPU 101, the RAM 102, and the ROM 103 via the general-purpose bus 112. The image processing modules 104 to 107 are connected from the upstream side to the downstream side in the illustrated order.

  Image processing modules 104 to 107 are image processing modules such as a shading correction circuit, a γ correction circuit, a color conversion circuit, and an enlargement / reduction circuit, for example. Each of the image processing modules 104 to 107 includes a register as shown in FIG. The register has a register address area (register address area a, b, c, d) for each image processing module and a register address area (broadcast address area) common to the image processing modules 104 to 107. As shown in FIG. 1, the image processing modules 104 to 107 are circuits that perform image processing by transferring data through the same path (transmission path 111), and are connected to the general-purpose bus 112 via the DMACs 108 and 109. . The CPU 101, RAM 102, and ROM 103 are connected to the general-purpose bus 112.

  Next, the operation of the image processing apparatus according to the first embodiment will be described.

  The CPU 101 converts the register data or image data into a command for each determined processing unit before starting the image processing, and writes the command to the RAM 102. Alternatively, a command obtained by converting register data or image data into a command may be written in the ROM 103 in advance. The DMAC 108 sequentially provides the above-described command group stored in the RAM 102 or the ROM 103 to the image processing module 104 located upstream.

  The above commands are roughly divided into two commands. The first is a register command for reading and writing the registers of each image processing module. The second is an image command including image data for performing image processing.

  As shown in FIG. 3A, the register command is composed of header information and data. The header information includes a command ID indicating a register command and a module ID as module identification information indicating an image processing module to which the register command is transmitted. For example, as shown in FIG. 4, the image processing module 104 is “001”, the image processing module 105 is “010”, the image processing module 106 is “011”, and the image processing module 107 is “100”. It is assigned as an ID. Further, “000” is assigned as the module ID corresponding to all the processing modules, and this module ID is hereinafter referred to as a broadcast ID.

  The data is composed of a read / write ID for identifying a command to be read from or written to a register of the image processing module, register data, and a register address. The combination of the command ID and the read / write ID described above constitutes command identification information that specifies the type of command such as register read or register write. The register data stores data to be written at a position specified by a register address in the case of a write command, and data read from a position specified by a register address in the case of a read command. That is, the register address and the register data constitute content information representing the read address and write content of the register command.

  On the other hand, the image command is composed of header information and data as shown in FIG. The header information is composed of a command ID indicating an image command. Since the image command is processed by all image processing modules, the module ID does not exist in the image command. The data is composed of attribute data and image data. The attribute data indicates position information of the image data, valid bits of the image data, other control signals, and the like. The image data of the image command is image data to be processed in the image processing module, and after being processed in the image processing module, it is overwritten with the image data obtained as a result of the processing.

  As described above, the DMAC 108 reads a command from the RAM 102 or the ROM 103 and transfers the read command to the image processing module 104. The image processing module 104 recognizes a register command or an image command from the command ID of the command, and performs processing according to the command.

  First, the operation of the image processing module 104 when the command is a register command will be described with reference to the flowchart of FIG. FIG. 5 is a flowchart for explaining processing executed for a command received by the image processing module of this embodiment.

  In step S501, the image processing module 104 refers to the module ID of the sent command. If the module ID is neither a broadcast ID nor a module ID of its own image processing module, the command is not necessary for the image processing module 104. Accordingly, in step S502, the image processing module 104 does not do anything with the command and transfers the command to the subsequent image processing module.

  On the other hand, when the module ID indicates its own image processing module, in step S503, the image processing module 104 refers to the read / write ID of the command. If the read / write ID indicates register write, the process proceeds from step S503 to step S504. In step S504, the image processing module 104 writes the register data of the command to the address indicated by the register address of the command in its own register. In step S505, the image processing module 104 transfers the command to the subsequent image processing module 105.

  On the other hand, if the read / write ID indicates register read, the process proceeds from step S503 to step S506. In step S506, the image processing module 104 reads the data stored in the position indicated by the register address of the command in its own register. In step S507, the image processing module 104 writes the value read from the register into the register data of the command to convert it into a command, and transmits this to the subsequent image processing module 105.

  If the module ID indicates a broadcast ID, the process proceeds from step S501 to step S508. In step S508, the image processing module 104 refers to the read / write ID. If the read / write ID indicates register write, the process proceeds to step S509. In step S509, the image processing module 104 writes the register data of the command at the position indicated by the register address of the command in its own register. In step S510, the image processing module 104 transmits the command to the subsequent image processing module 105.

  On the other hand, if it is determined in step S508 that the read / write ID indicates register read, the process proceeds to step S511. In step S511, the image processing module 104 transmits a busy signal to the preceding (upstream) module so as not to receive the next command. In the case of the image processing module 104, the previous module is the DMAC. Then, the image processing module 104 transfers the received command to the subsequent (downstream) image processing module 105 as it is.

In step S512, the image processing module 104 issues a new command having the following configuration based on the command. The new command can be generated by updating the module ID of the command to the module ID of the image processing module 104 and updating the register data of the command with the register value read from the register data. That is, in the new command,
・ In command ID, ID indicating register command is
The module ID includes an ID indicating its own image processing module (using FIG. 4, the module ID is “001”),
・ The read / write ID and register address contain the value of the input command.
In the register data, data at the position indicated by the register address of the input command of the register of the image processing module 104 is described.

  In step S513, the image processing module 104 transmits the new command to the subsequent image processing module 105, and cancels the busy signal transmitted to the previous image processing module in step S511. Since the module ID of the new command is different from any of the subsequent image processing modules 105 to 107, the new command is not processed by the subsequent image processing modules 105 to 107.

  As described above, according to the present embodiment, when the image processing module issues and transmits a command by itself, the register values common to all the image processing modules interfere with each other by one register command. It can be read without doing.

  If the command is an image command, the image processing module 104 receives the command data and performs image processing. Then, the image processing module 104 converts the output data of the image processing into a command and transmits it to the subsequent image processing module 105.

  Although the processing of the image processing module 104 for register commands and image commands has been described above, similar processing is performed in the other image processing modules 105 to 107. Finally, the DMAC 109 receives the command output from the most downstream image processing module 107, and sequentially writes the command to the address of the RAM 102 designated in advance in the direct memory access. In this embodiment, when a register read is performed by the image processing module, a new command is generated. Therefore, the number of commands read by the DMAC 108 is different from the number of commands written by the DMAC 109. For example, when there are four image processing modules and one read command having a broadcast ID is sent from the DMAC 108, the DMAC 109 receives five read commands. The DMAC 109 stores the command received from the image processing module 107 at the final stage in the RAM 102 while sequentially increasing the address counter of the RAM 102. Alternatively, since it is known that four commands follow the broadcast read register command, the DMAC 109 may be configured so that each of the addresses to be stored is determined in advance and stored at that address. Is possible. The determination of the read register command by the DMAC 109 can be realized by analyzing the header of the received command. Alternatively, if the sequence is such that a broadcast register read is always performed after the end of the image command, the DMAC 109 can determine the read register command only with the count value of the received command. However, this control is premised on that a read register command or the like does not enter between image commands.

  In the above description, the four image processing modules (image processing modules 104 to 107) have been described, but it goes without saying that the number does not depend on the number of image processing modules.

  When writing to registers in all image processing modules, as described above, write is set to the read / write ID of the register command, and broadcast ID is set to the module ID. Each image processing module writes the register data of the register command to the address specified by the register address of the register command, and transfers the register command as it is downstream (S509, S510).

  As described above, according to the image processing apparatus of this embodiment, it is possible to read / write data from / to a register common to all image processing modules with one register command. As a result, it is expected that the system will be speeded up by saving the command.

  In addition, when reading / writing a register common to a plurality of image processing modules, a predetermined address range common to each image processing module may be used instead of the broadcast ID. In this case, the identification of the register command in each image processing module is determined by both its own module ID or the special address range. That is, when the address matches with its own module identification ID or the address is in the special address range, reading / writing to the register is performed. For example, even in the case where a specific range of addresses is specified in step S501, the process branches to step S508. When a plurality of processing modules are specified by an address range in this way, a specific address range can be set on the image processing module side, so that a register command can be issued to a part of a plurality of image processing modules instead of all of them. Can be executed.

It is a block diagram which shows the structural example of the image processing apparatus by embodiment. It is a figure explaining the register address of the image processing module by embodiment. It is a figure which shows the data structural example of the command of embodiment. It is a figure which shows the example of module ID of embodiment. It is a flowchart explaining the process at the time of register command reception of the image processing module by embodiment. It is a figure explaining the general image processing apparatus to which the several image processing module was connected.

Claims (10)

An image processing apparatus in which a plurality of processing modules that process commands including command identification information, module identification information, and command content information are connected in series,
Each of the plurality of processing modules is
Determining means for determining whether the command identification information of the input command indicates reading of data from the register and whether the module identification information of the command specifies a plurality of processing modules;
When the determination means determines that the command indicates reading of data from a register and designates a plurality of processing modules, the transfer means transfers the command as it is downstream;
Wherein said command by judging means indicates the reading of data from the register, when it is determined that specifies a plurality of processing modules, replace the module identification information of the command identification information of the processing module, the content information Generating means for describing the data read from the register and generating a new command;
An image processing apparatus comprising: a transmission unit that transmits a new command generated by the generation unit downstream.   The determination unit determines that the command specifies a plurality of processing modules when the module identification information of the command is a specific value specifying all the processing modules. The image processing apparatus according to 1.   2. The determination unit according to claim 1, wherein when the read address specified by the content information of the command is within a predetermined address range, it is determined that the command specifies a plurality of processing modules. The image processing apparatus described. Providing means for sequentially reading a command group stored in a memory and providing the command group to a processing module upstream of the plurality of processing modules;
4. The image processing apparatus according to claim 1, further comprising: a storage unit that sequentially stores, in a memory, commands output from a processing module that is the most downstream of the plurality of processing modules. 5. .   When it is determined by the determination means that the command indicates reading of data from the register and designates a plurality of processing modules, the processing module transmits a busy signal to the upstream processing module and outputs the next command. 5. The image processing apparatus according to claim 1, wherein the image processing apparatus is configured not to receive the image.   When the determination unit determines that the command indicates reading of data from the register and designates a plurality of processing modules, and the transmission unit transmits the new command, the processing module determines that the upstream The image processing apparatus according to claim 5, wherein the busy signal transmitted to the processing module is canceled. A method for controlling an image processing apparatus in which a plurality of processing modules for processing a command including command identification information, module identification information, and command content information are connected in series.
Determination judging means of the processing module, and whether to show the reading of data from the command identification information of the inputted command register, and whether the module identification information of the command specifies a plurality of processing modules, the A determination step to
When the front Symbol said command determination step it is determined that specifies a plurality of processing modules indicate the reading of data from the register, a transfer step of transferring the command directly to the downstream,
When the previous SL determination process command is determined that specifies a plurality of processing modules indicate the reading of data from the register, replacing the module identification information of the command identification information of the processing module, the content information Generating a new command by describing the data read from the register; and
A method for controlling an image processing apparatus, comprising: a transmission step of transmitting a new command generated in the generation step to a downstream side. The determination step is characterized in that, when the module identification information of the command is a specific value that specifies all the processing modules, it is determined that the command specifies a plurality of processing modules. 8. A method for controlling the image processing apparatus according to 7 . Wherein in the determination step, the read address content information of the command is designated, when in a predetermined address range, in claim 7, wherein determining that the command specifies a plurality of processing modules A control method of the image processing apparatus described. A providing step in which the providing means of the image processing apparatus sequentially reads out a command group stored in a memory and provides the command group to the processing module upstream of the plurality of processing modules;
Any storage means of the image processing apparatus, according to claim 7 to 9, further comprising a storage step of sequentially storing the most downstream processing command outputted from the module of the plurality of processing modules in the memory A method for controlling the image processing apparatus according to claim 1.

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