JP7269610B2 - Slave side device - Google Patents

Description

The present invention has at least three signal inputs, a serial data signal, a serial clock signal, and a select signal, and while the select signal is active, the serial data signal is captured at the change timing of the serial clock signal, The present invention relates to a clock synchronous serial data receiving circuit that shifts 1-bit data each time it is received and converts it into parallel data of a reference number of bits, and a bus system that actively connects a plurality of clock synchronous serial data receiving circuits.

2. Description of the Related Art A clock synchronous serial data transfer method is widely used for data transfer between parts or between boards in mechanical devices such as various computer systems and game machines. In this clock-synchronous serial data transfer method, data is received one bit at a time from serial data transmitted through a data signal line in synchronization with the clock (for example, rise timing) of a clock signal.

In the clock-synchronous serial data transfer system, handling of data transmission errors that occur accidentally due to the influence of noise or the like is determined according to the design policy of the entire system. In general, when a transmission error occurs, a process of notifying the other party of the occurrence of the transmission error and requesting retransmission is performed. However, in the case of a machine that operates in a poor noise environment such as amusement machines, communication errors often occur. This is not preferable as it may interfere with the progress of the game.

When data is transferred regularly at short intervals, even if some of the received data contains errors, do not request retransmission, simply ignore the erroneous data and receive it. The same effect as resending can be obtained by simply waiting for the data. For example, in the gaming machine described in Patent Document 1, in order to repeatedly drive N×M lamps at high speed, drawing data is transmitted from the effect control board to the lamp connection board at a short cycle of about 2 ms. If there is garbled bits in the drawing data, the drawing data is discarded and the lamp is not driven. In this way, even if the lamp driving due to the abnormal drawing data is discarded, there is no problem as a whole from the relationship between human vision and the lamp lighting cycle.

JP 2009-279252 A

However, in the invention described in Patent Document 1, the basis for the abnormality detection circuit to detect an abnormality in the received data is the content of the received data (one bit of common data COM1 to COM4 is normal and only one bit is 1; Other than that is abnormal), it is difficult to apply to a general-purpose clock synchronous serial data transfer circuit. That is, unless an abnormality can be detected based on such a simple determination condition, it is difficult to properly discard drawing data periodically transmitted in a short period of time.

Also, in general, bit corruption due to noise means that the serial data signal is perceived as being at the H level due to noise added to the serial data signal at the rise or fall (hereafter referred to as "edge") of the clock signal. It should be erroneously recognized as L level (or vice versa), but since noise is generally a voltage change in a very short period of time, noise is present in the serial data signal just at the timing of the edge of the clock signal. Ride is rare.

On the other hand, when noise is added to the clock signal, even a short voltage change is recognized as an edge by the electronic circuit, resulting in a data anomaly in which the serial data bit position shifts. . Moreover, data anomalies occur no matter what part of the clock signal has noise, so this occurs more frequently.

If the bit position shifts due to such noise, it cannot be detected by the abnormality detection circuit in the invention described in Patent Document 1, and the ramp effect is executed with the bit position shifted from the original position, resulting in an undesirable situation. There is a risk of executing a natural ramp effect.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances. It is an object of the present invention to provide a bus system that actively connects a plurality of clock synchronous serial data receiving circuits.

In order to solve the above problems, the invention according to claim 1 has at least three signal input terminals of a serial data signal, a serial clock signal, and a select signal, and while the select signal is active, a clock synchronous serial data receiving circuit of a modular structure which captures the serial data signal at a change timing of the serial clock signal, shifts each time 1-bit data is received, and converts the serial data signal into parallel data of a reference number of bits; The number of the serial clock signals detected while the select signal is active is counted, and when the counted value becomes a natural number multiple of the reference number of bits, an acquisition timing determination signal is output, and the counted value is When the number of bits becomes a natural number times +1, the capture timing determination means stops outputting the capture timing determination signal; and reception data determination means for determining the parallel data as reception data only when the select signal becomes inactive.

According to a second aspect of the invention, in the clock synchronous serial data receiving circuit according to the first aspect, it is possible to output a next-stage serial data signal obtained by shifting the serial data signal by the reference number of bits. It is characterized by

In the invention according to claim 3, at least the reference bit number×M (M is a natural number of 2 or more) of the serial data signal, the serial clock signal, and the select signal are supplied from the master device, and the 3. The clock synchronous serial data receiving circuit according to claim 2 is provided in a slave side device that is cascade-connected in M stages, and from the received data determined by the clock synchronous serial data receiving circuits in the M stages, " A bus system for actively connecting the clock synchronous serial data receiving circuits of the M stages so as to obtain parallel data of a reference number of bits×M, wherein the serial data signal is a pre-determined first stage of the bus system. a serial data signal line supplied only to serial data signal input terminals in a clock synchronous serial data receiving circuit; and a serial clock signal supplying the serial clock signal to serial clock signal input terminals in all the clock synchronous serial data receiving circuits. a select signal line for supplying the select signal to select signal input terminals in all of the clock-synchronous serial data receiving circuits; A serial data signal output terminal for the next stage and a serial data signal line for the next stage connecting the serial data signal input terminal of the clock synchronous serial data receiving circuit of the (n+1)th stage are included.

According to the clock synchronous serial data receiving circuit of the present invention, when a clock signal is erroneously recognized due to noise, the transmission error can be easily detected and the data can be ignored. Further, according to the bus system of the present invention, by cascade-connecting M clock-synchronous serial data receiving circuits, it is possible to realize a clock-synchronous serial data receiving function corresponding to the number of bits M times the number of reference bits. .

1 is a schematic configuration diagram of a game machine provided with a clock synchronous serial data receiving circuit according to the present invention; FIG. 1 is a circuit configuration diagram showing an embodiment of a clock synchronous serial data receiving circuit according to the present invention; FIG. 4 is a timing chart when normal communication data is received by the clock-synchronous serial data receiving circuit of the present embodiment; 4 is a timing chart when abnormal communication data is received by the clock synchronous serial data receiving circuit of the present embodiment; FIG. 2 is a schematic configuration diagram of a slave-side device having a bus structure in which four clock-synchronous serial data receiving circuits can be cascaded;

DETAILED DESCRIPTION OF THE INVENTION Embodiments of a clock synchronous serial data receiving circuit according to the present invention will be described in detail below with reference to the accompanying drawings.

A gaming machine 100 illustrated in FIG. 1 is a pachinko-type gaming machine capable of performing a pinball game using game balls. The main control board 200, which mainly controls the progress of the game in the game machine 100, controls various game function devices. The sub-control board 300, which is provided at an appropriate place in the game machine 100 and mainly performs effect control by means of a liquid crystal display device, decorative lamps, etc., transmits a command signal for driving the lamp to the lamp connection board 400, for example, and receives the received lamp signal. A drive signal is output from the connection board 400 to various lamps 110, and a lamp effect is executed.

Here, the sub-control board 300 is a master-side device that transmits clock-synchronous serial data, and the lamp connection board 400 is a slave-side device that receives clock-synchronous serial data. The lamp connection board 400 is provided with a clock synchronous serial data receiving circuit 1 that converts the received clock synchronous serial data into parallel data and outputs the parallel data. This clock-synchronous serial data receiving circuit 1 is not limited to a pachinko game machine, and even in a reel-type game machine, when clock-synchronous serial data is transmitted from a master-side device to a slave-side device, the slave It can be used for side devices.

FIG. 2 is a circuit configuration diagram showing an embodiment of the clock synchronous serial data receiving circuit 1 described above. This clock synchronous serial data receiving circuit 1 mainly comprises a shift register 11, a latch 12 and a counter 13, and also uses an AND circuit 14, a negative logic OR circuit 15a and a NOT circuit 15b. Input signals to the clock synchronous serial data receiving circuit 1 are a serial data signal SD, a serial clock signal SCK, a select signal SEL, and a clear signal CLR.

The clear signal CLR is normally an H level negative logic signal, and is input to the CLR terminal of the latch 12 and the CLR terminals of the shift register 11 and the counter 13 via the OR circuit 15a. Therefore, when the clear signal CLR becomes L level, the shift register 11, the latch 12 and the counter 13 are initialized.

The select signal SEL is normally an H level negative logic signal, and is input to the CLR terminals of the shift register 11 and the counter 13 via the NOT circuit 15b and the OR circuit 15a, respectively. Normally, when the select signal SEL is at H level, the shift register 11 and the counter 13 remain in the initial state and stop operating. On the other hand, when the select signal SEL becomes L level, the CLR terminals of the shift register 11 and the counter 13 become H level and are ready for operation.

The output of the AND circuit 14, to which the select signal SEL is applied to one input terminal, remains at L level until the Q3 output of the counter 13, which will be described later, is inverted to H level and the select signal SEL becomes H level. No change. Therefore, until the output of the AND circuit 14 changes to H level and is input to the CK terminal of the latch 12, the output (for example, 8 bits) of the latch 12 holds the previously latched output.

The shift register 11 outputs the signal level of the serial data signal SD input to the D terminal to the QA terminal at the rising timing of the serial clock signal SCK input to the CK terminal. At the same timing, the signal level output to the QA terminal is output to the QB terminal. Similarly, the signal of the adjacent terminal is shifted up to the QH terminal.

The reception timing of the serial clock signal by the shift register 11 will be described with reference to FIGS. 3 and 4. FIG. First, based on FIG. 3, the case where the serial data signal is normally received will be described.

Since the shift register 11 becomes operable while the select signal SEL is at L level, the serial data signal is output at the timing of the rising edge of each clock pulse in the serial clock signal SCK (including eight clock pulse signals from T1 to T8). Take in SD data and shift from QA to QH. Specifically, the first bit data "1" from the serial data signal SD is registered in QA at the rising edge of the first clock pulse T1. Subsequently, at the rising edge of the second clock pulse T2, the second bit data "1" from the serial data SD is registered in QA, and the first bit data "1" already registered in QA is shifted to QB. . Similarly, the third to eighth bit data "0" "0" "1" "0" "1" "0" are received from the third clock pulse T3 to the eighth clock pulse T8, and from QA to QH. Store 8-bit data.

The bit data stored in QA to QH of the shift register 11 are supplied to the data input terminals D0 to D7 of the latch 12, and the output signal of the AND circuit 14 (described in detail later) is applied to the CK terminal of the latch 12. It is not latched by the output terminals Q0-Q7 of the latch 12 until it is input. QH of the shift register 11 can be taken out of the clock synchronous serial data receiving circuit 1 . A signal obtained from this QH is a serial data signal obtained by shifting the serial data signal SD by 8 bits, and can be used as a serial data signal for the next stage (detailed later).

On the other hand, when the select signal SEL becomes L level and the counter 13 starts operating, it is in the initial state, so the outputs of the terminals Q0 to Q3 remain at L level. The count value is incremented at the timing of the rise of the serial clock signal SCK that is input thereafter, and the result is output in binary from Q0 to Q3. In this counter 13, the output signal TP1 of the Q3 terminal corresponding to bit 3 becomes H level at the rise timing of the eighth pulse (eighth clock pulse T8) of the serial clock signal SCK.

Also, the output signal TP1 from the Q3 terminal of the counter 13 is input to its own LD terminal. Input signals D0 to D3 are output to Q0 to Q3 at the rising timing of the CK terminal input when the LD terminal is at H level. In the counter 13 of this configuration example, D0 is connected to H level, and D1 to D3 are all connected to L level, so the count value of Q0 to Q3 outputs returns to "1" again. That is, the output signal TP1 from the Q3 terminal changes from the L level to the H level at the 8nth rising edge of the CK terminal (n is an arbitrary natural number) after the CLR terminal goes H level, and at the 8n+1th rising edge. It becomes L level again.

Therefore, this counter 13 "counts the number of serial clock signals detected while the select signal is active, and when the counted value becomes a natural number multiple of the reference bit number (e.g., 8), the It functions as a capture timing determination means for outputting a timing determination signal. In the clock-synchronous serial data receiving circuit 1 of the present embodiment, the number of reference bits to be output as parallel data is set to 8. Therefore, the timing at which the number of bits of data to be transferred becomes 8 (serial clock signal SCK 8 clock pulses are counted), the output signal TP1 from the Q3 terminal, which is the output of the counter 13, is set to H level. The output signal TP1 of the Q3 terminal may be set to H level at the timing when the clock pulse is counted up to 16 or 32.

The Q3 output TP1 of the counter 13 described above is ANDed with the select signal SEL by the AND circuit 14 and input to the CK terminal of the latch 12 . Therefore, only when the select signal SEL becomes H level after the number of clock pulses of the serial clock signal SCK input to the clock synchronous serial data receiving circuit 1 reaches 8n and before it reaches 8n+1, AND The output signal TP2 of the circuit 14 becomes H level and is input to the CK terminal of the latch 12. FIG. When a rising signal (the rising edge of the output signal TP2 of the AND circuit 14) is input to the CK terminal, the latch 12 latches the input signals D0 to D7 and outputs them to terminals Q0 to Q7. That is, the first transmitted bit (least significant bit LSB) is sent to the Q7 terminal, the second bit to the Q6 terminal, the third bit to the Q5 terminal, the fourth bit to the Q4 terminal, and the fifth bit to the Q3 terminal. The 6th bit is latched at the Q2 terminal, the 7th bit is latched at the Q1 terminal, and the last transmitted 8th bit (most significant bit MSB) is latched at the Q0 terminal to obtain an 8-bit parallel signal. can be done.

Therefore, when the select signal SEL becomes inactive within the period in which the capture timing determination signal (output signal TP1 of the Q3 terminal) is output by the capture timing determination means (counter 13), the AND circuit 14 only, it functions as "received data determining means for determining parallel data as received data". When the select signal SEL becomes H level, the input to the CLR terminal of the counter 13 becomes L level and operation stops, so the output signal TP1 of the Q3 terminal becomes L level. Therefore, the period during which the output signal TP2 of the AND circuit 14 is at H level is short (see FIG. 3), but the latch operation to the terminals Q0 to Q7 by the latch 12 is performed at the rising edge detection timing to the CK terminal. so there is no problem.

Next, based on FIG. 4, the case where the serial data signal cannot be received normally will be described.

Since the serial clock signal SCK contains noise, and this noise is erroneously recognized as the clock pulse T5, the fifth pulse should be the clock pulse T6, the sixth pulse should be the clock pulse T7, and the seventh pulse should be the clock pulse. At T8, the eighth clock pulse is counted as T9. Noise is often a signal with a very narrow width, as shown in FIG. It is misidentified as a signal.

As described above, if a clock pulse is erroneously detected due to noise, an erroneous signal "01011001" is output from the output terminals QA to QH of the shift register 11 at the timing when the select signal SEL becomes inactive H level. If data is output and the latch 12 fetches it into the output terminals Q0 to Q7, a communication error will occur, and there is a danger that the device will operate with an erroneous parallel signal, and the reliability of the device itself will be impaired.

Since the clock synchronous serial data receiving circuit 1 according to the present embodiment is provided with the counter 13 as fetching timing determination means and the AND circuit 14 as reception data determining means, the latch 12 detects erroneous data. can be prevented from being taken into the output terminals Q0 to Q7. That is, since the seventh pulse would normally be counted as the clock pulse T8, the output signal TP1 from the Q3 terminal of the counter 13 becomes H level upon detection of the rising edge of the clock pulse T8, and then clock pulse T9. Therefore, even if the select signal SEL subsequently rises to H level, the output signal TP2 of the AND circuit 14 does not go to H level, and the CK terminal of the latch 12 remains at L level. Therefore, erroneous data will not be latched at the output terminals Q0-Q7 of the latch 12. FIG.

As described above, even if noise is added to the serial clock signal SCK at any timing while the select signal SEL is at the L level, there is a risk of causing an error such as erroneously detecting the noise as a clock pulse. In the clock synchronous serial data receiving circuit 1, erroneous data can be prevented from being latched to the output terminals Q0 to Q7 of the latch 12, regardless of the timing of erroneous detection of the clock pulse. Incidentally, while the select signal SEL is at the L level, there is a possibility that noise may be added to the serial data signal SD and an error may occur in the content of the data itself. However, since it is extremely unlikely that noise with an extremely short time width will occur at exactly the same timing as the rising edge of the clock pulse of the serial clock signal SCK, there is no practical problem.

As described above, according to the clock synchronous serial data receiving circuit 1 according to the present embodiment, when the clock signal is erroneously recognized due to the influence of noise, the transmission error can be easily detected and the data can be ignored. , it is possible to prevent the device operation from being executed due to the erroneous data, and to avoid the risk of impairing the reliability of the device itself.

It should be noted that the clock-synchronous serial data receiving circuit 1 alone according to the present embodiment can only handle parallel signal output of a predetermined reference number of bits. However, by functionally connecting a plurality of clock-synchronous serial data receiving circuits 1, it is possible to deal with the number of bits that is a natural number multiple of the reference number of bits. A bus system 2 for functionally connecting a plurality of clock synchronous serial data receiving circuits 1 will be described with reference to FIG.

The master-side device 301 is a source of clock-synchronous serial data, and supplies a serial data signal SD, a serial clock signal SCK, a select signal SEL, and a clear signal CLR to the slave-side device 401 via a wire harness or the like. . A bus system 2 is provided on the input side of the slave side device 401 that receives these signals. In addition, the bus system 2 shown in this embodiment has a structure in which up to four clock-synchronous serial data receiving circuits 1 can be functionally connected. A socket 21 , a second socket 22 , a third socket 23 and a fourth socket 24 are provided.

Note that when a plurality of clock-synchronous serial data receiving circuits 1 are attached, they must be attached in order from the first socket 21 . The number of sockets to which the clock-synchronous serial data receiving circuit 1 is attached is not particularly limited, and M sockets should be provided for M-stage (M is a natural number equal to or greater than 2) cascade connection. Good luck. In the bus system 2 shown in FIG. 5, only the first socket 21 and the second socket 22 are equipped with the clock synchronous serial data receiving circuits 1, and the third socket 23 and the fourth socket 24 are left empty. It shall be used. In this case, there is no need to attach dummy modules or the like to the empty third and fourth sockets 23 and 24, and the two clock synchronous serial data receiving circuits 1 attached to the first and second sockets 21 and 22 can It can function as a receiving port for serial data.

A serial data signal line L1 that receives a serial data signal from the master side device 301 is connected only to the serial data signal input terminal of the first clock synchronous serial data receiving circuit 1A attached to the first socket 21 of the first stage.

On the other hand, the serial clock signal line L2 which receives the serial clock signal SCK from the master side device 301 is connected to the first to fourth clock synchronous serial data receiving circuits 1A to 1D attached to the first to fourth sockets 12 to 24. Connect to each serial clock signal input pin. A select signal line L3 for receiving a select signal SEL from the master side device 301 is input to each select signal of the first to fourth clock synchronous serial data receiving circuits 1A to 1D mounted on the first to fourth sockets 12 to 24. terminal. A clear signal line L4 which receives a clear signal CLR from the master side device 301 is input to each of the first to fourth clock synchronous serial data receiving circuits 1A to 1D mounted on the first to fourth sockets 12 to 24. terminal. That is, the serial clock signal SCK, select signal SEL and clear signal CLR are supplied to the first to fourth clock synchronous serial data receiving circuits 1A to 1D at the same timing.

The next stage serial data signal output terminal QH in the first stage first clock synchronous serial data receiving circuit 1A is connected to the second stage second clock synchronous serial data receiving circuit 1B by the second stage serial data signal line L51. It is connected to the serial data signal input terminal, and the next stage serial data signal is supplied from the first clock synchronous serial data receiving circuit 1A to the second clock synchronous serial data receiving circuit 1B. This serial data signal for the next stage is a serial data signal obtained by shifting the serial data signal SD from the master side device 301 by 8 bits. It is supplied to the serial data signal input terminal of the 2-clock synchronous serial data receiving circuit 1B, and upon detection of the rising edge of the ninth clock pulse, the output of the shift register 11 in the 2-clock synchronous serial data receiving circuit 1B. A first bit of serial data signal SD is registered to terminal QA.

That is, while the select signal SEL is at L level, 16-bit serial data is transmitted by the serial data signal SD, and 16-bit data is captured by 16 clock pulses of the serial clock signal SCK. Bits to 8th are output from the output signal line L6B of the second clock-synchronous serial data receiving circuit 1B, and bits 9 to 16 are output from the output signal line L6A of the first clock-synchronous serial data receiving circuit 1A. Therefore, when the first clock-synchronous serial data receiving circuit 1A and the second clock-synchronous serial data receiving circuit 1B are cascade-connected, it is possible to handle serial data with the number of bits (16), which is twice the reference number of bits (8). can be made

Similarly, when the third clock-synchronous serial data receiving circuit 1C is set in the third socket 23, the serial data for the next stage in the second clock-synchronous serial data receiving circuit 1B is transmitted by the third stage serial data signal line L52. The signal output terminal QH is connected to the serial data signal input terminal of the third clock-synchronous serial data receiving circuit 1C, and the first to eighth bits are supplied from the output signal line L6C of the third clock-synchronous serial data receiving circuit 1C. The 9th to 16th bits are output from the output signal line L6B of the second clock synchronous serial data receiving circuit 1B, and the 17th to 24th bits are the output of the first clock synchronous serial data receiving circuit 1A. Since it is output from the signal line L6A, if the first to third clock-synchronous serial data receiving circuits 1A to 1C are cascade-connected, the number of bits (24), which is three times the number of reference bits (8), can be handled. be able to.

Further, when the fourth clock-synchronous serial data receiving circuit 1C is set in the fourth socket 24, the serial data signal for the next stage in the third clock-synchronous serial data receiving circuit 1C is transmitted by the fourth stage serial data signal line L53. The output terminal QH is connected to the serial data signal input terminal of the fourth clock-synchronous serial data receiving circuit 1D, and the 1st to 8th bits are output from the output signal line L6D of the second clock-synchronous serial data receiving circuit 1D. The 9th to 16th bits are output from the output signal line L6C of the third clock synchronous serial data receiving circuit 1C, and the 17th to 24th bits are the output signal of the second clock synchronous serial data receiving circuit 1B. Since the 25th to 32nd bits are output from the output signal line L6A of the first clock synchronous serial data receiving circuit 1A, the first to fourth clock synchronous serial data receiving circuits 1A to 1D are output from the line L6B. are cascade-connected, it is possible to support serial data transfer of the number of bits (32) which is four times the number of reference bits (8).

That is, when M clock-synchronous serial data receiving circuits 1 are cascade-connected, the next-stage serial data signal output terminal QH in the n-th stage (1≤n<M) clock-synchronous serial data receiving circuit 1, By connecting the serial data signal input terminals of the clock synchronous serial data receiving circuit 1 at the (n+1)th stage, it is possible to correspond to the serial data transfer of the reference bit number.times.M. According to such a bus system 2, even if the number of driven devices (for example, decorative lamps) connected to the slave side device 401 increases, it can be easily handled by increasing the bit number of the serial data. Therefore, there is no need to change the design to increase the signal from the master-side device 301, the labor for the design is reduced, and the process change in the assembly work is not required.

The embodiments of the clock synchronous serial data receiving circuit and bus system according to the present invention have been described above with reference to the accompanying drawings. It may be implemented by diverting known and existing equivalent technical means within the range of not changing the configuration of .

1 clock synchronous serial data receiving circuit 11 shift register 12 latch 13 counter 14 AND circuit 15a OR circuit 15b NOT circuit

Claims (2)

A master-side device supplies at least a reference bit number×M (M is a natural number equal to or greater than 2) serial data signals, serial clock signals, and select signals. a bus system capable of supplying signals to the clock synchronous serial data receiving circuit and acquiring signals from the M clock synchronous serial data receiving circuits,
The clock-synchronous serial data receiving circuit has at least three signal input terminals of the serial data signal, the serial clock signal, and the select signal, and receives the serial data while the select signal is active. A module structure that takes in a signal at the change timing of the serial clock signal, shifts each time 1-bit data is received, and converts it into parallel data of a reference number of bits, and while the select signal is active. The number of detected serial clock signals is counted, and when the counted value becomes a natural number multiple of the reference bit number, a capture timing determination signal is output, and the counted value becomes a natural number multiple of the reference bit number +1. Then, when the select signal becomes inactive within the period during which the capture timing determination signal is output by the capture timing determination means for stopping the capture timing determination signal, a reception data determination means for determining the parallel data as reception data, and capable of outputting a next-stage serial data signal obtained by shifting the serial data signal by the reference number of bits;
The bus system supplies the serial clock signal and the select signal to respective signal input terminals of the M clock synchronous serial data receiving circuits, and transmits the serial data signal to the first clock synchronous serial data receiving circuit. supplied to the input terminal of the serial data signal, the output terminal of the serial data signal for the next stage in the clock synchronous serial data receiving circuit of the n-th stage (1≤n<M), and the clock synchronization of the n+1 stage connected to the input terminal of the serial data signal in the serial data receiving circuit;
A slave side characterized in that parallel data of "reference bit number x M" is obtained from the sequence of the received data for M stages determined by the clock synchronous serial data receiving circuits of M stages. device. The clock-synchronous serial data receiving circuit is initialized by receiving a clear signal supplied from the master-side device from an input terminal for the clear signal,
wherein the bus system supplies the clear signal supplied from the master-side device to input terminals of the clear signal in the M clock-synchronous serial data receiving circuits;
The slave-side device according to claim 1, characterized by :

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