WO2022041421A1

WO2022041421A1 - Adaptive data decoding circuit and led unit circuit

Info

Publication number: WO2022041421A1
Application number: PCT/CN2020/122135
Authority: WO
Inventors: 周兴安
Original assignee: 无锡德芯微电子有限公司
Priority date: 2020-08-28
Filing date: 2020-10-20
Publication date: 2022-03-03
Also published as: CN111970792A

Abstract

An adaptive data decoding circuit and an LED unit circuit. The adaptive data decoding circuit comprises: a signal edge detection processing circuit (100), a reset code detection circuit (200), a reference code decoding circuit (300) and a data packet decoding circuit (400), wherein the signal edge detection processing circuit (100) is used for outputting a mark signal upon detection of a rising edge or a falling edge of a data code, each frame of data comprises a reset code, a reference code and a data packet which are sequentially connected, the data packet comprises a plurality of data codes, the length of the reference code is N times of the length of one data code in the data packet, and N is a natural number greater than 1; the reset code detection circuit (200) is used for generating a reset signal; the reference code decoding circuit (300) is used for decoding the reference code in each frame of data, so as to obtain a reference code decoding result; and the data packet decoding circuit (400) is used for decoding the data packet. The adaptive data decoding circuit and the LED unit circuit can implement adaptive data decoding.

Description

An adaptive data decoding circuit and LED unit circuit

technical field

The present invention relates to the technical field of LED circuits, in particular to an adaptive data decoding circuit and an LED unit circuit including the adaptive data decoding circuit.

Background technique

At present, LED has been widely used in decoration, lighting, advertising, stage lighting and many other fields. In general, LEDs require a dedicated integrated circuit to drive and control, that is, an LED drive circuit. In the following description, the combination of the LED and its corresponding driving circuit is referred to as an LED unit. In practical applications, multiple LED units are generally connected in parallel or in series to form a larger LED project. In order to make each LED unit work as required, it is necessary to send corresponding data to each LED unit through the controller. In parallel application engineering, the general practice is to set an address for each LED unit, and each LED unit receives the corresponding data from the main controller according to its own address.

The main controller sends data according to the agreed data format, and the LED unit can receive the corresponding data according to its own address. The data transmission rate is generally agreed upon in product design, which is the fixed data transmission rate. The advantage of the fixed data transmission rate is that the data decoding at the receiving end of the LED unit is simple, but the disadvantages of the fixed data transmission rate are also obvious, mainly in the following points:

First, multiple LED units are connected to form a system. If there is a relatively long connection line when connecting these LED units, or when more LED units are used in the same system, the drive output port of the main controller will be used. It is said that the larger the load, the larger the distortion of the data sent to each LED unit, which eventually leads to an increase in the probability of the LED unit decoding failure, and in severe cases it cannot work normally.

The second is the decoding problem of the LED unit, because the data transmission rate is fixed, which requires the LED unit to decode the data at this fixed rate. Generally, there is a fixed frequency clock inside the LED unit for decoding and receiving. Data, but this internal clock frequency is related to application conditions, such as voltage changes, temperature changes, etc., which will cause the internal clock of the LED unit to change. In addition, in the process of integrated circuit processing, process deviation will also lead to clock frequency deviation. Due to the deviation of the clock frequency, the probability of failure of the LED unit to decode the data from the main controller is greatly increased. Therefore, in order to ensure the smooth decoding of the LED unit, the product design and production process requirements are higher.

In addition, in practical applications, the fixed data transmission rate is difficult to meet different applications. For example, sometimes there are fewer LED units in the project, but the customer needs a relatively high data transmission rate to improve the refresh rate. In this case, the fixed data transmission rate rate cannot be achieved.

SUMMARY OF THE INVENTION

The invention provides an adaptive data decoding circuit and an LED unit circuit including the adaptive data decoding circuit, which solves the problem in the related art that the decoding must be performed at a fixed rate when the data transmission rate is fixed, and the process and production requirements are relatively high. question.

As a first aspect of the present invention, an adaptive data decoding circuit is provided, which includes: a signal edge detection processing circuit, a reset code detection circuit, a reference code decoding circuit and a data packet decoding circuit, the signal edge detection processing circuit Both the output end of the reference code decoding circuit and the output end of the reset code detection circuit are connected to the input end of the reference code decoding circuit, and the output end of the reference code decoding circuit is connected to the data packet decoding circuit;

The signal edge detection processing circuit is used to detect the rising edge or falling edge of the data code in each frame of data, and can output a flag signal when the rising edge or falling edge of the data code is detected, wherein each frame of data includes sequential A connected reset code, a reference code and a data packet, the data packet includes a plurality of data codes, the length of the reference code is N times the length of a data code in the data packet, and N is a natural number greater than 1;

The reset code detection circuit is configured to generate a reset signal after recognizing the reset code in each frame of data;

The reference code decoding circuit is configured to decode the reference code in each frame of data according to the flag signal and the reset signal to obtain a reference code decoding result;

The data code decoding circuit is configured to generate a decoding rate of the data packet according to the decoding result of the reference code, and decode the data packet according to the decoding rate of the data code.

Further, the adaptive data decoding circuit includes a first clock signal, and both the input terminal of the signal edge detection processing circuit and the input terminal of the reference code decoding circuit are input with the first clock signal.

Further, the adaptive data decoding circuit includes a counter circuit and a data comparator circuit, the output terminal of the reference code decoding circuit is connected to the first input terminal of the data comparator circuit, and the output terminal of the counter circuit is connected to the first input terminal of the data comparator circuit. The second input end of the data comparator circuit, the output end of the data comparator circuit is connected to the data packet decoding circuit, the counter circuit is used to input the enable signal and the first clock signal, and output the counter result, so The data comparator circuit is used for generating a second clock signal according to the result of the counter and the decoding result of the reference code, and the second clock signal is used for inputting to the data packet decoding circuit.

Further, the adaptive data decoding circuit includes an RS flip-flop, the R terminal of the RS flip-flop is connected to the second clock signal, the S terminal of the RS flip-flop is connected to the flag signal, and the RS flip-flop is connected to the second clock signal. The output terminal Q of the counter circuit is connected to the enable signal terminal of the counter circuit, and the RS flip-flop is used for outputting the enable signal according to the flag signal and the second clock signal.

Further, the adaptive data decoding circuit includes a D flip-flop, the D terminal of the D flip-flop is connected to the output terminal of the data comparator circuit, and the clock signal terminal of the D flip-flop is connected to the first clock signal , the output terminal Q of the D flip-flop outputs a second clock signal.

Further, the length of the reference code is 8 times the length of a data code in the data packet.

As another aspect of the present invention, an LED unit circuit is provided, which includes: a controller and a plurality of LED units, each LED unit is communicatively connected to the controller, and each LED unit includes the aforementioned The controller can send multiple frames of data to each LED unit, and the adaptive data decoding circuit in each LED unit can decode each frame of data received according to the corresponding decoding rate .

Further, each LED unit is connected with the controller through a data line.

Further, each LED unit and the controller are connected in communication with the controller through a power line carrier.

In the adaptive data decoding circuit provided by the embodiment of the present invention, since a reference code is set in each frame of data, the length of the reference code can be customized, and the length of the reference code is equal to the length of a data code in the data packet. Scale setting, when the LED unit receives data, it first decodes the reference code, and the decoding rate of the data packet can be determined according to the length of the reference code. Again subject to the impact of the transmission rate.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification, and together with the following specific embodiments, are used to explain the present invention, but do not constitute a limitation to the present invention.

FIG. 1 is a specific embodiment of the LED unit circuit provided by the present invention.

FIG. 2 is another specific embodiment of the LED unit circuit provided by the present invention.

FIG. 3 is a structural block diagram of an adaptive data decoding circuit provided by the present invention.

FIG. 4 is a schematic diagram of a frame data structure provided by the present invention.

FIG. 5 is a schematic diagram of a reset code, a reference code and a data waveform in a data packet in a frame of data provided by the present invention.

FIG. 6 is a schematic diagram of a specific circuit structure of an adaptive data decoding circuit provided by the present invention.

FIG. 7 is a timing diagram of the decoding waveforms of the data 1 code and the data 0 code provided by the present invention.

FIG. 8 is a schematic diagram of one frame of data in a specific implementation manner provided by the present invention.

FIG. 9 is a circuit schematic diagram of a reference code decoding circuit provided by the present invention.

FIG. 10 is a circuit schematic diagram of a signal edge detection processing circuit provided by the present invention.

detailed description

It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments of some, but not all, of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

In order to solve the problem that the LED units in the prior art must be decoded at a fixed rate, an LED unit circuit provided by an embodiment of the present invention, as shown in FIG. 1 and FIG. 2 , includes a controller and a plurality of LED units, each Each LED unit is connected in communication with the controller, and each LED unit includes an adaptive data decoding circuit, the controller can send multiple frames of data to each LED unit, and the adaptive data decoding in each LED unit decodes The circuits can decode each frame of data received according to the corresponding decoding rate.

It should be understood that the adaptive data decoding circuit provided by the embodiment of the present invention can be set as required within a certain range, so that each LED unit can successfully and accurately complete data decoding without decoding at a fixed rate.

As shown in FIG. 1 , each LED unit is connected with the controller through a data line.

As shown in FIG. 2 , each LED unit and the controller are connected in communication with the controller through a power line carrier.

It can be understood that, each LED unit and the controller can realize data transmission through the power line carrier.

It should be understood that the controller may include an MCU, etc., which may be selected as required, which is not limited here.

It should be noted that all LED units connected to the main controller can receive all data at the same time, and each LED unit decodes the data sent by the main controller and receives its own data according to its own address. The master controller sends data in units of frames.

The adaptive data decoding circuit that enables adaptive rate decoding for each LED unit will be described in detail below.

FIG. 3 is a structural block diagram of an adaptive data decoding circuit provided according to an embodiment of the present invention. As shown in FIG. 3 , it includes: a signal edge detection processing circuit 100, a reset code detection circuit 200, a reference code decoding circuit 300, and a data packet decoding circuit 400. The output end of the signal edge detection processing circuit 100 and the output end of the reset code detection circuit 200 are both connected to the input end of the reference code decoding circuit 300, and the output end of the reference code decoding circuit 300 is connected to the reference code decoding circuit 300. The data packet decoding circuit 400 is connected;

The signal edge detection processing circuit 100 is used to detect the rising edge or falling edge of the data code in each frame of data, and can output a flag signal when the rising edge or falling edge of the data code is detected, wherein each frame of data includes: A reset code, a reference code and a data packet connected in sequence, the data packet includes a plurality of data codes, the length of the reference code is N times the length of a data code in the data packet, and N is a natural number greater than 1 ;

The reset code detection circuit 200 is configured to generate a reset signal after identifying the reset code in each frame of data;

The reference code decoding circuit 300 is configured to decode the reference code in each frame of data according to the flag signal and the reset signal to obtain a reference code decoding result;

The data code decoding circuit 400 is configured to generate a decoding rate of the data packet according to the decoding result of the reference code, and decode the data packet according to the decoding rate of the data code.

It should be noted that, a frame of data in the embodiment of the present invention specifically refers to that a frame of data starts with a reset code, followed by a reference code, and then followed by a data packet. A schematic diagram of a frame of data timing waveform is shown in Figure 4.

Compared with the data frame structure that uses a fixed frequency to transmit data, the data frame structure of the adaptive data decoding circuit provided by the present invention adds a reference code, and the length of the data code at the sending end can be randomly selected within a certain range. The LED unit with the data code length has a wider application range and is more adaptable to the application environment. Because the sender can freely change the length of the data code within the required range, in actual engineering, the sending rate can be changed as needed to obtain better results. For example, the rate of sending data can be increased to increase the display frame rate of the LED unit. It is also possible to reduce the sending rate so that it works properly with a particularly large number of points.

Because the data is transmitted over a single wire, the decoding of the data is done by judging the signal level change and the duration of the high and low levels. The falling edge of the signal is used as the start of all data codes, and the next falling edge is the end of the current data code and the beginning of the next data code, thus connecting all the data codes. The data frames are connected by reset codes. Here, all data codes are started according to the falling edge, and the rising edge can also be used as the start of the data code, as long as the LED unit design specification corresponds to the data specification sent by the main controller. The above-mentioned so-called data code is a general term for the reference code and each bit of data in the data packet.

Each component of one frame of data is described in detail below. Here, it is introduced according to the falling edge of the signal as the start of the data code.

Reset code, which defines the data signal as the reset code if the data signal continues to be at a high level for more than a certain length. The reset code has two functions. The first function is to determine the start of sending a new frame of data. For the LED unit circuit, when the reset code is detected, it must be ready to receive new data, that is, start the reference code and data packets at any time. The second function is to make the data of the previous frame take effect, that is to say, when the LED unit circuit decodes the data packet and receives its own data packet, it is only temporarily stored, and will not be stored until the next reset code. Load data into its working register for use.

Reference code, it is defined that the first data code after the reset code is the reference code. The role of the reference code is to determine the data transfer rate. The length of the reference code code is N times the length of one data code in the data packet.

Data packet, the sum of all data codes after the definition reference code is a data packet. There are two kinds of data codes: data 1 code and data 0 code.

Both the reference code and the data packet start with the falling edge of the data signal, and the low level lasts for a certain period of time and then changes to a high level and ends for a specified time. The schematic diagram of reset code, reference code and data packet waveform is shown in Figure 5, _TD is the high level time length of data 1 code, and the high and low level lengths of all patterns are defined with reference to _TD . In general, the length T _reset of the reset code can be defined as several hundreds of microseconds to several milliseconds. T _D is specifically set according to the actual situation, but it must meet the following requirements, that is, whether it is a reference code or a data code, the length of the high level time cannot be longer than the reset code.

Table 1 Definition of reset code, reference code and data packet in one frame of data

It should be noted that _TD represents the high level time length of data 1 code, and the high and low level lengths of all code patterns are defined with reference to _TD . The length of the reference code is N times the length of a data code in the data packet, usually N≥2.

When the sender sends data, it can be sent in units of frames. The reset code, reference code and data codes in all data packets in one frame of data can be sent continuously. If necessary, a certain high-level idle time can be added between codes, but it is necessary to ensure this high-level The idle time cannot be greater than T _reset , otherwise it may be mistaken as a reset code by the circuit. The idle time between frames can be connected with a high level, and there is no time requirement.

After determining the data structure of a frame, the following describes the specific implementation process of data transmission to the adaptive data decoding circuit for decoding. The so-called data transmission means that under the agreed specifications, the sender sends data as required, and the receiver interprets the input data. decode and get the correct data. The so-called receiving end refers to the LED unit in the present invention. The process of accurately obtaining its own data from the data sent by the LED unit from the sender is called adaptive decoding, and the circuit that completes the adaptive decoding work is called the adaptive decoding circuit. The schematic diagram of the adaptive decoding circuit is as follows: Figure 6 shows. In addition to the adaptive decoding circuit, the LED unit circuit also includes other module circuits, which are not described here, and the present invention only introduces the adaptive decoding circuit.

In the following description, DI represents the data signal; CK1 is the clock signal of the LED unit circuit; DO is the data obtained after the decoding circuit completes the decoding work, generally 8 bits or multi-bit data processed for the convenience of subsequent circuits; 1 represents logic High level, 0 represents logic low level.

The signal edge detection processing circuit 100 is responsible for detecting the falling edge of the DI signal, and the circuit outputs a flag signal DIPL for use by other module circuits at the falling edge of the DI signal, and the DIPL signal is a positive pulse.

It should be understood that the adaptive data decoding circuit includes a first clock signal CK1, and both the input terminal of the signal edge detection processing circuit 100 and the input terminal of the reference code decoding circuit 300 are input with the first clock signal CK1 .

After the reset code detection circuit 200 successfully detects the reset code, a reset signal reset is generated, and the reset signal is a positive pulse. After receiving the reset signal, the reference code decoding circuit 300 first sets the output ED signal to 0, and then prepares to calculate the length of the reference code. The interval between the first two falling edges of DI after the reset signal is the length of the reference code. A clock signal CK1 is counted to calculate the length of the reference code. After the reference code decoding circuit calculates the length of the reference code, it divides the length value by 2N and saves it as Q, and outputs it from its output Q in real time for use by other related circuits, and sets the output signal ED to 1 for use by other circuits. So far, the reference code decoding is completed, and the reference code decoding circuit stops working until the next reset signal to work again according to the above process.

Specifically, as shown in FIG. 6 , the adaptive data decoding circuit includes a counter circuit 500 and a data comparator circuit 600 , and the output terminal of the reference code decoding circuit 300 is connected to the first input terminal of the data comparator circuit 600 . , the output end of the counter circuit 500 is connected to the second input end of the data comparator circuit 600, the output end of the data comparator circuit 600 is connected to the data packet decoding circuit 400, and the counter circuit 500 is used for input The enable signal and the first clock signal, and output the counter result, the data comparator circuit 600 is configured to generate a second clock signal CK2 according to the counter result and the reference code decoding result, and the second clock signal CK2 is used for input to the packet decoding circuit 400 .

Further specifically, as shown in FIG. 6 , the adaptive data decoding circuit includes an RS flip-flop 700, the R terminal of the RS flip-flop 700 is connected to the second clock signal, and the S terminal of the RS flip-flop 700 is connected to the second clock signal. For the flag signal, the output terminal Q of the RS flip-flop 700 is connected to the enable signal terminal of the counter circuit, and the RS flip-flop 700 is configured to output the enable signal according to the flag signal and the second clock signal. energy signal.

Further specifically, as shown in FIG. 6 , the adaptive data decoding circuit includes a D flip-flop 800, the D terminal of the D flip-flop 800 is connected to the output terminal of the data comparator circuit 600, and the D flip-flop 800 The clock signal terminal of the D flip-flop 800 is connected to the first clock signal, and the output terminal Q of the D flip-flop 800 outputs the second clock signal CK2.

Specifically, after the decoding of the reference code is completed, the ED signal is set to 1, and other related circuits start the data packet decoding work when the ED signal is equal to 1. The flag signal DIPL from the signal edge detection processing circuit 100 indicates the beginning of the data code, and the flag signal DIPL makes the output end Q of the RS flip-flop 700 output 1, and the output end Q of the RS flip-flop 700 is connected with the input end EN of the counter circuit 500 , when the input terminal EN of the counter circuit 500 becomes 1, its internal counter starts to work, that is, counts with the clock CK1, and outputs the result Q of the counter in real time. The input terminal A and the input terminal B of the data comparator circuit 600 are connected to the output Q of the reference code decoding circuit 300 and the output Q of the counter circuit 500, respectively. When the input A and the input B of the data comparator circuit 600 are equal, the output terminal Y of the data comparator circuit 600 outputs 1. The input terminal D of the D flip-flop 800 is connected to the output terminal Y of the data comparator circuit 600. When the input terminal D of the D flip-flop 800 becomes 1, the output terminal Q of the D flip-flop 800 outputs 1 under the action of the clock CK. The output terminal Q of the D flip-flop 800 outputs the second clock signal CK2. The second clock signal CK2 is connected to the input port R of the RS flip-flop 700 and is also connected to the clock terminal CK of the data decoding circuit 400 . When the second clock signal CK2 becomes 1, the output terminal Q of the RS flip-flop 700 is set to 0, thus the counter circuit 500 stops working, and at the same time its output Q is set to 0, so that the output Y of the data comparator circuit 600 changes accordingly. is 0, and finally the second clock signal CK2 becomes 0 again.

It can be seen from the working process of the related circuit described above that a pulse signal CK2 is generated from the falling edge of DI to a certain time point. Refer to Figure 7 for specific timing waveforms.

Assuming that the length of a data code in the data packet is _TL , the length of the reference code is N* _TL . After each data code is processed by the above circuit, a second clock signal CK2 will be generated at 1/ _2TL time point. If the high and low level lengths of the data 1 code and the data 0 code are reasonably defined, and the data DI is stored with the second clock signal CK2 as the clock, the data 1 code and the data 0 code can obtain the corresponding values 1 and 0 respectively. . In this way, the decoding of the one-bit data code is completed.

All data in the data packet is decoded in sequence according to the above method, and other related circuits of the LED unit obtain their own data according to their own address according to the specific definition of the data packet in the data frame.

It can be seen from the above data decoding process that, within a certain range, no matter what the length of the data code _TL is, as long as the relationship that the length of the reference code is N times the length of a data code in the data packet is satisfied, the automatic code provided by the embodiment of the present invention is used. Adapted to the data decoding circuit, the LED unit can correctly identify the data 1 code and the data 0 code. Different _TL lengths represent different data transmission rates. That is to say, the rate at which the controller sends data does not need to be fixed to a certain value, but to be set within a certain range, and the LED unit can decode and obtain the data correctly.

In actual product design, the N value is appropriately selected according to the specific application, and the range of the data code length TL is estimated, and the adaptive data transmission can be realized by designing a hardware circuit that satisfies the N value and the TL range.

The LED unit described in the embodiment of the present invention has four outputs. Each output is controlled by 8 bits of data to control its output duty cycle. The main controller sends data, each LED unit decodes according to its own address and obtains its own data, and the data transmission between the main controller and each LED unit adopts the adaptive data decoding circuit provided by the embodiment of the present invention.

Multiple LED units are used in parallel, and the hardware connection is shown in Figure 1 and Figure 2. Each LED unit decodes its own data from the data sent by the main controller according to its own address. The LED unit first converts the data loaded on the power supply line (VDD) into a standard digital signal DI. This part of the work is completed by a special circuit, which will not be described in detail here. The so-called data in the following description refers to DI.

The working process of the adaptive data decoding circuit provided by the present invention will be described in detail below with a specific embodiment.

The definition of the data frame in the embodiment of the present invention is shown in FIG. 8 .

The high level that lasts for more than 120us (us is the time unit: microseconds. The same below) is the reset code.

Preferably, in this embodiment of the present invention, the length of the reference code is 8 times the length of a data code in the data packet.

The multiple N=8 of the length of the reference code and the length of a data code.

A data code length TL ranges from 3 to 30us. The high and low level lengths of the data code meet the requirements shown in Figure 5 and Table 1.

The data packet includes command byte CMD and data D0~Dn. All LED unit circuits will receive the command byte CMD; data D0~Dn are the LED unit circuits corresponding to addresses 0~n used to control the data output by the 4 channels, and the LED unit circuit receives the corresponding data according to its own address.

The principle of adaptive data decoding in the embodiment of the present invention is shown in FIG. 6 . The frequency of the first clock signal CK1 used in the decoding circuit is designed to be 10 MHz, and its period is 0.1 us. According to the definition of the data frame, the reference code is up to 240us, so the counter used to detect the length of the reference code in the reference code decoding circuit 300 is designed to be 12 bits to meet the requirements. The result of the 12-bit counter divided by 2N is the reference code decoding circuit. The output Q, because N=8, so Q is obtained by dividing the 12-bit counter by 16, so Q is an 8-bit data. The range that the counter circuit 500 needs to be able to measure in actual work is half of the data code, that is, 1.5us to 15us. Here, it is designed as an 8-bit counter, and the maximum measurable range is 0.1us*256=25.6us, which fully satisfies the requirements of this embodiment. Require. Therefore, the data comparator circuit 600 may also be designed to be 8 bits.

The signal edge detection and processing circuit 100 works in real time, and generates a signal DIPL when the DI signal falls on the falling edge for use by other circuits, as shown in FIG. 7 .

It should be noted that, as shown in FIG. 10 , it is a circuit schematic diagram of a specific implementation of the signal edge detection processing circuit 100 , which is specifically composed of three D flip-flops, a NOT gate, an AND gate, and a NOR gate. It should be understood that the circuit structure shown in FIG. 10 is only an example, and the signal edge detection processing circuit 100 in the embodiment of the present invention is not limited to the structure of FIG. 10 .

The reset code detection circuit 200 generates a reset signal reset after recognizing the reset code. According to the data frame definition, it is known that the reference code is after the reset. The reset causes the reference code decoding circuit 300 to enter the working state, firstly, the output ED is set to 0, and then the DIPL signal is set to 0. Under the action, the reference code length calculation is completed and the final output result Q is obtained, and the output signal ED is set to 1 at the same time. The specific work flow is as follows. The first DIPL signal after the reset signal represents the start of the reference code. At this time, the internal counter of the reference code decoding circuit starts to work, that is, counting with CK1 as the clock. When the next DIPL signal appears, it represents the end of the reference code. When the circuit does the following two tasks, the first is to suspend the counter work, divide the result by 16 and store it in the output register Q and output it in real time; the second is to set the circuit output signal ED to 1. The decoding of the reference code ends here, and the above working process is repeated again when the next frame of data arrives.

After the decoding of the reference code is completed, the decoding of the data code will be performed. The data code decoding process is as follows: when the ED signal is 1, all data code decoding related circuits start to work, the data code starts at the falling edge of DI, and the DIPL signal is generated. The DIPL signal sets the output Q of the RS flip-flop 700 to 1. When the counter When the input terminal EN of the circuit 500 receives the output Q of the RS flip-flop 700 and becomes 1, it starts to work, that is, counts with the clock signal CK as the clock, and the counter result Q is output in real time. When the count result Q and the reference code decoding circuit 300 When the output Q is equal, the output Y of the data comparator circuit 600 becomes 1, and the output Y of the data comparator circuit 600 is connected to the input terminal D of the D flip-flop 800. When the D flip-flop 800 detects that the input D becomes 1, in the first Its output Q becomes 1 under the action of the clock signal CK1. The output terminal Q of the D flip-flop 800 drives the second clock signal CK2. When the second clock signal CK2 changes to 1, it acts on the RS flip-flop 700 and makes its output Q change to 0. When the EN terminal of the counter circuit 500 changes to 0, its output Q changes to 0. After passing through the data comparator circuit After 600 and the D flip-flop 800 act, the second clock signal CK2 becomes 0 again under the action of the first clock signal CK1. As a result of the above process, the second clock signal CK2 is generated at half the length of the data code, and its timing waveform is shown in FIG. 7 . The data decoding circuit 400 uses the second clock signal CK2 as a clock to store the DI data and output it to the DO signal for use by other module circuits. So far, the decoding of the one-bit data code is completed.

As shown in Figure 9, it is a circuit schematic diagram of the reference code decoding circuit 300 in the embodiment of the present invention, and is specifically composed of three RS flip-flops, a NAND gate, an OR gate and a counter 310, wherein the upper 8 bits Q[11: 4] represents the output Q of the reference code decoding circuit 300 .

It should be noted that the specific implementation circuit diagrams of the reset code detection circuit 200 , the data packet decoding circuit 400 , the counter circuit 500 and the data comparator circuit 600 are well known to those skilled in the art and will not be repeated here.

The LED unit circuit will sequentially decode all data codes as described above.

Other module circuits of the LED unit use the second clock signal CK2 and the DO data signal to use the data in groups of 8. The first 8 bits of a frame of data are the command byte CMD, and all LED units receive the CMD byte. Afterwards, it receives its own data according to the CMD requirements and the current LED unit circuit address and stores it for backup. When the next reset code flag signal is reset, the received data is acted on the output module, so as to complete the task of the main controller sending data to control the four outputs of each LED unit circuit.

From the perspective of the adaptive decoding process in the embodiment, as long as a frame of data sent by the main controller meets the requirements that the reset code is greater than 120us, the length of the data code is 3us to 30us, and the length of the reference code is 8 times that of the data code, the LED unit circuit Both instructions and data can be decoded normally.

To sum up, the adaptive data decoding circuit and LED unit circuit provided by the present invention can accept the data code length of the transmitting end to be randomly selected within a certain range. Compared with the LED unit that can only accept a fixed data code length, the application range is wider. The application environment is more adaptable. Because the sender can freely change the length of the data code within the required range, in actual engineering, the sending rate can be changed as needed to obtain better results. For example, the rate of sending data can be increased to increase the display frame rate of the LED unit. It is also possible to reduce the sending rate so that it works properly with a particularly large number of points.

It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, without departing from the spirit and essence of the present invention, various modifications and improvements can be made, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

An adaptive data decoding circuit, characterized in that it comprises: a signal edge detection processing circuit, a reset code detection circuit, a reference code decoding circuit and a data packet decoding circuit, an output end of the signal edge detection processing circuit and the reset code The output ends of the detection circuit are all connected to the input end of the reference code decoding circuit, and the output end of the reference code decoding circuit is connected to the data packet decoding circuit;

The signal edge detection processing circuit is used to detect the rising edge or falling edge of the data code in each frame of data, and can output a flag signal when the rising edge or falling edge of the data code is detected, wherein each frame of data includes sequential A connected reset code, a reference code and a data packet, the data packet includes a plurality of data codes, the length of the reference code is N times the length of a data code in the data packet, and N is a natural number greater than 1;

The reset code detection circuit is configured to generate a reset signal after recognizing the reset code in each frame of data;

The reference code decoding circuit is configured to decode the reference code in each frame of data according to the flag signal and the reset signal to obtain a reference code decoding result;

The data code decoding circuit is configured to generate a decoding rate of the data packet according to the decoding result of the reference code, and decode the data packet according to the decoding rate of the data code.
The adaptive data decoding circuit according to claim 1, wherein the adaptive data decoding circuit comprises a first clock signal, an input terminal of the signal edge detection processing circuit and an input terminal of the reference code decoding circuit Both input the first clock signal.
The adaptive data decoding circuit according to claim 2, wherein the adaptive data decoding circuit comprises a counter circuit and a data comparator circuit, and an output end of the reference code decoding circuit is connected to an output terminal of the data comparator circuit. The first input terminal, the output terminal of the counter circuit is connected to the second input terminal of the data comparator circuit, the output terminal of the data comparator circuit is connected to the data packet decoding circuit, and the counter circuit is used for inputting The power signal and the first clock signal, and output the counter result, the data comparator circuit is used for generating a second clock signal according to the counter result and the reference code decoding result, and the second clock signal is used for input to the Describe the packet decoding circuit.
The adaptive data decoding circuit according to claim 3, wherein the adaptive data decoding circuit comprises an RS flip-flop, the R terminal of the RS flip-flop is connected to the second clock signal, and the RS flip-flop is connected to the second clock signal. The S end is connected to the flag signal, the output end Q of the RS flip-flop is connected to the enable signal end of the counter circuit, and the RS flip-flop is used to output the signal according to the flag signal and the second clock signal. enable signal.
The adaptive data decoding circuit according to claim 3, wherein the adaptive data decoding circuit comprises a D flip-flop, the D terminal of the D flip-flop is connected to the output terminal of the data comparator circuit, and the The clock signal terminal of the D flip-flop is connected to the first clock signal, and the output terminal Q of the D flip-flop outputs the second clock signal.
The adaptive data decoding circuit according to claim 1, wherein the length of the reference code is 8 times the length of a data code in the data packet.
An LED unit circuit, characterized in that it includes: a controller and a plurality of LED units, each LED unit is connected to the controller in communication, and each LED unit includes any one of claims 1 to 6. The adaptive data decoding circuit described above, the controller can send multiple frames of data to each LED unit, and the adaptive data decoding circuit in each LED unit can decode each frame of data received according to the corresponding decoding rate. decoding.
The LED unit circuit according to claim 7, wherein each LED unit is connected to the controller through a data line.
The LED unit circuit according to claim 7, wherein each LED unit and the controller are communicatively connected through a power line carrier.