TWI447691B - Method for triggering source drivers - Google Patents

Description

Method of triggering a source driver

The present invention relates to a method of triggering a source driver, and more particularly to a method of sequentially triggering a source driver by counting a counter in a source driver.

In the current liquid crystal display (LCD), data transmission methods of point-to-point or bus (BUS) have been widely used, so that the liquid crystal display can generate a picture according to the received data. Please refer to FIG. 1 , which is a schematic diagram of signal transmission by a conventional liquid crystal display 100 . As shown in FIG. 1, the liquid crystal display 100 includes a timing controller 140 and source drivers SD ₁ , SD ₂ , SD _{3 ,} and SD ₄ . The timing controller 140 is coupled to a source line driver the SD ₁ to SD _4, SD ₄ to ₁ to provide information on the Data Clock and clock signal to the source driver SD. When the source driver SD ₁ receives the high-level initial pulse signal DIO, the source driver SD ₁ starts to receive the data transmitted from the timing controller 140. When the source driver SD ₁ receives the data, it transmits a high-level initial pulse signal DIO to the source driver SD ₂ to cause the source driver SD _{2 to} start receiving data. Through the above method, the source drivers SD ₁ to SD _{4 can} sequentially receive data.

However, when the initial pulse signal DIO is transmitted between the source drivers, the initial pulse signal DIO is easily coupled to the signal of the external circuit to generate noise, causing the waveform of the initial pulse signal DIO to ripple. . When the above fluctuation phenomenon is serious, the source driver may make an erroneous logical judgment on the initial pulse wave signal DIO, and the data cannot be correctly received, so that the picture of the liquid crystal display 100 is distorted. For example, when the potential of the initial pulse signal DIO transmitted to the next-level source driver is at a low level, if the signal of the external circuit has a serious interference phenomenon, the next-level source driver may start from a low level. The initial pulse signal DIO was mistakenly judged as a high level, and the data was received erroneously. Please refer to FIG. 2, FIG. 2 is a system source drivers SD _{2 is} a schematic misjudged start pulse signal DIO source _{driver. 1} SD of the came. The waveform 10 is the control signal of the external circuit, the waveform 20 is the initial pulse signal DIO outputted by the source driver SD ₁ , and the waveform 30 is the initial pulse signal DIO received by the source driver SD ₂ , such as the waveform 20 The initial pulse signal DIO outputted by the source driver SD ₁ is a partial wave. However, the initial pulse signal DIO is affected by the control signal of the external circuit during the transmission to the source driver SD ₂ , and the source is made. The initial pulse signal DIO received by the driver SD ₂ has the noise 40, and the source driver SD ₂ erroneously receives the data again due to the noise 40 being too large, causing distortion of the picture of the liquid crystal display 100.

One embodiment of the present invention provides a method of triggering N source drivers, each source driver including a counter and an identification unit. The method includes setting the identification unit such that the source driver has a specific set of codes; triggering a first source driver and the counter according to a trigger signal; and counting the counter of a Kth source driver The Kth source driver is triggered when the set of specific codes of the Kth source driver match. Where K≦N.

Another embodiment of the present invention provides a display including a display panel and N source drivers. The N source drivers are coupled to the display panel for providing data signals to the display panel. Each of the source drivers includes a counter and an identification unit. The counter is used for counting, and the identification unit is used to set a specific set of codes. When a first source driver and the counter are triggered by a trigger signal, the counter starts counting, and when the counter of a Kth source driver counts and the group specific of the Kth source driver The Kth source driver will be triggered when the code matches. Where K≦N.

Through the device and method provided by the invention, the trigger signal received by the source driver in the display will not be coupled to the noise of the external circuit, and the situation of logical misjudgment is avoided, so that the data can be accurately received. The picture produced by the display panel will not be distorted.

Please refer to FIG. 3, which is a schematic diagram of signal transmission by the display 200 of the present invention. As shown in FIG. 2, the display 200 includes a display panel 220, the source drivers SD ₁ to SD _N and a timing controller 240. The source drivers SD ₁ to SD _N are coupled to the display panel 220 for providing data signals to the display panel 220. Each source driver includes a counter 250 for counting, and an identification unit 260 is used to set a particular set of codes. The setting method of the identification unit 260 can adopt a pin setting, that is, a so-called binary setting mode. For example, if it is set to 00, it is the first one, and if it is set to 01, it is the second one or the like, or can be adopted. If the memory is pre-written, the first address is written to 00 at a specific address in the memory, the second is 01, and so on. The setting method is known to those familiar with the technology. Setting method. The timing controller 240 is coupled to the source drivers SD ₁ to SD _N and includes a trigger signal generator 242, a clock signal generator 244, and a frequency divider 246. The trigger signal generator 242 is used to generate the trigger signal DIO_TRIGGER. The clock signal generator 244 is configured to generate the second clock signal CLK2. When the source drivers SD ₁ to SD _N counter 250 is triggered when a trigger signal DIO_TRIGGER, the counter 250 starts counting, and when the K-th source driver the SD _K counter 250 counts the K-th source driver the SD _K When the specific code set by the recognition unit 260 matches, the Kth source driver SD _K is triggered, and the K system is a positive integer not greater than N. For example, if each source driver includes 80 shift registers SR ₁ to SR ₈₀ and the specific code of the identification unit 260 of the source drivers SD ₁ , SD ₂ , . . . , SD _N The system is set to 1, 81, ..., (80 * (N-1) + 1), so when the counter 250 counts to 1, the source driver SD ₁ is triggered to shift the register SR ₁ to SR ₈₀ start sampling data; when the counter 250 counts to 81, the source driver SD ₂ will be triggered to shift the register SR ₁ to SR _{80 to} start sampling data; when the counter 250 counts (80 *(N-1)+1), the source driver SD _N is triggered to cause the shift registers SR ₁ to SR _{80 to} start sampling the data sequentially. The frequency divider 246 divides the second clock signal CLK2 generated by the clock signal generator 244 according to the number of pins of the source driver data receiving end to generate the first clock signal CLK1. In the display 200, each of the source drivers includes a plurality of shift registers for sequentially sampling the image data according to the first clock signal after the source driver is triggered.

Please refer to FIG. 4, a schematic view showing a fourth received signal sequentially in the display of the source driver 200 of the present invention, SD ₁ to SD _N. As shown in FIG. 4, the source drivers SD ₁ receives the trigger signal DIO_TRIGGER and the other of the first clock signal CLK1 frequency over to the SD _N lines, when the K-th source driver the SD _K of the counter 250 to the K-th When the specific code of the source driver SD _K matches, the Kth source driver SD _K is triggered to sequentially receive the data from the source drivers SD ₁ to SD _N . Each of the source drivers receives the trigger signal DIO_TRIGGER and the first clock signal CLK1 to determine when to start receiving data from the timing controller 240 according to the trigger signal DIO_TRIGGER and the first clock signal CLK1. In FIG. 4, the source drivers SD ₁ to SD _N receive the data transmitted from the timing controller 240 in a data pair manner. For example, when the timing controller 240 pre-transmits 480 channels of data to the source drivers SD ₁ to SD _N , each channel contains 8 bits of data, and each data pair is set to It can receive data of 3 channels at the same time, so each source driver can receive 6 channels of data at a time, that is, the number of pins of each source driver data receiving end is set to receive 6 channels of data at the same time, so A total of 80 shift registers SR ₁ to SR ₈₀ are required for each source driver to receive data from the timing controller 240 for 480 channels. When a match of the first clock signal source drivers SD ₁ receives the trigger signal DIO_TRIGGER, and the source drivers SD ₁ received by the CLK1 and source drivers SD specific code _1, the source drivers SD shift in _a temporary The SR1 to SR80 will sequentially sample the data. Match the specific code when the source drivers SD shift register SR80 ₁ data sampling is completed, so that the source drivers SD ₂ receives a first clock signal CLK1 will be the source driver SD of _2, the source drivers SD ₂ of the shift register SR1 to SR80 begin sampling data. Therefore case, the source drivers SD ₁ to SD _N received trigger signal DIO_TRIGGER not coupled to an external circuit noise, while avoiding the occurrence of logical false, and thus can be accurately sampled data. For convenience of description in the present embodiment, only the source driver receives the 480 channel data transmitted by the timing controller 240 in a two-data pair manner, but the source driver of the present invention is not limited to the method of only two data pairs. Receiving the data transmitted by the timing controller 240 does not limit the timing controller 240 to transmit only 480 channel data at a time. In addition, the number of pins of each source driver data receiving end can also be set according to actual needs. Any changes and modifications to the manner in which the timing controller 240 transmits data and the source driver receives data in this embodiment are within the scope of the present invention.

Please refer to FIG. 5, which is a structural diagram of the counter 250 of the source driver of the present invention. As shown in FIG. 5, the counter 250 includes eight D-type Flip Flops DFF1 to DFF8, and each D-type flip-flop includes a clock terminal CLK, a control terminal D, an output terminal Q, and a counter. The phase output terminal QB is coupled to the reset signal RST to reset the clock signal on the D-type flip-flops DFF1 to DFF8. The control terminal D is coupled to the inverting output terminal QB. The clock terminal CLK of the D-type flip-flop DFF1 is used to receive the inverted signal of the first clock signal CLK1, and the clock terminal CLK of the D-type flip-flops DFF2 to DFF8 are respectively coupled to the D-type flip-flop DFF1. To the output Q of DFF7. The output Q of the D-type flip-flops DFF1 to DFF8 is used to generate output bits Q ₁ to Q ₈ to provide a count to the source drivers SD ₁ to SD _N , when the counter of the K-th source driver SD _K is 250 when the count matches the specific code and the K-th source driver identification unit 260 of the SD _K generated, triggering the K-th source drivers SD _K. For convenience of description in the present embodiment, only the counter 250 includes eight D-type flip-flops. However, the counter 250 of the present invention may also be configured to include other numbers of D-type flip-flops, and is not limited to only There are 8 D-type flip-flops, and the counter 250 can also be set to include other types of flip-flops.

Through the device and method provided by the present invention, the trigger signal DIO_TRIGGER received by the source driver of the display 200 will not be coupled to the noise of the external circuit, thereby avoiding the occurrence of logical misjudgment, thereby accurately receiving the data. The picture generated by the display panel 220 is not distorted.

The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 20, 30. . . Waveform

40. . . Noise

100. . . LCD Monitor

200. . . monitor

220. . . Display panel

242. . . Trigger signal generator

244. . . Clock signal generator

246. . . Frequency divider

250. . . counter

260. . . Identification unit

140, 240. . . Timing controller

Data. . . data

Clock. . . Clock signal

SD ₁ , SD ₂ , SD ₃ , SD ₄ , SD _N . . . Source driver

DIO. . . Initial pulse signal

DIO_TRIGGER. . . Trigger signal

CLK2. . . Second clock signal

CLK1. . . First clock signal

DFF1 to DFF8. . . D-type flip-flop

Q1 to Q8. . . Output bit

CLK. . . Clock end

D. . . Control terminal

Q. . . Output

QB. . . Inverting output

RST. . . Reset signal

SR ₁ to SR ₈₀ . . . Shift register

Figure 1 is a schematic diagram of signal transmission by a conventional liquid crystal display.

Figure 2 is a schematic diagram of the source driver of Figure 1 erroneously receiving the start pulse signal.

Figure 3 is a schematic diagram of signal transmission for the display of the present invention.

Figure 4 is a schematic diagram of the sequential reception signal of the display source driver of the present invention.

Figure 5 is a block diagram of the source driver counter of the present invention.

200. . . monitor

220. . . Display panel

242. . . Trigger signal generator

244. . . Clock signal generator

246. . . Frequency divider

250. . . counter

260. . . Identification unit

240. . . Timing controller

SD ₁ , SD ₂ , SD ₃ , SD _N . . . Source driver

DIO_TRIGGER. . . Trigger signal

CLK2. . . Second clock signal

CLK1. . . First clock signal

Claims (9)

A method for triggering N source drivers, each source driver comprising a counter and an identification unit, the method comprising: setting the identification unit such that the source driver has a specific set of codes; triggering a trigger according to a trigger signal a source driver and the counter; and when the count of a counter of the Kth source driver matches the set of specific codes of the Kth source driver, triggering the Kth source driver; wherein K≦ N and K and N are positive integers. The method of claim 1, further comprising: after triggering the Kth source driver, sequentially triggering a plurality of shift registers of the Kth source driver according to a first clock signal. The method of claim 2, further comprising dividing a second clock signal to generate the first clock signal. The method of claim 3, wherein the second clock signal is divided to generate the first clock signal, and the second clock signal is divided according to the number of pins of the data receiving end of the source driver. Frequency to generate the first clock signal. A display comprising: a display panel; The N source drivers are coupled to the display panel for providing data signals to the display panel. Each of the source drivers includes: a counter for counting; and an identification unit for setting a specific set of codes; When a first source driver and the counter are triggered by a trigger signal, the counter starts counting, and when the counter of a Kth source driver counts and the group specific of the Kth source driver When the code name matches, the Kth source driver will be triggered; and where K≦N and K and N are positive integers. The display of claim 5, wherein the counter comprises a plurality of serially connected flip-flops. The display of claim 6, wherein the flip-flops are a plurality of D-type flip-flops. The display device of claim 5, wherein the Kth source driver comprises a plurality of shift registers for sequentially, after the Kth source driver is triggered, according to a first clock signal Image data is sampled. The display device of claim 5, further comprising a timing controller coupled to the N source drivers, the timing controller comprising: a trigger signal generator for generating the trigger signal; a clock signal generator for generating a second clock signal; and a frequency divider for dividing the second clock signal to generate the first clock signal.