CN110377549B

CN110377549B - Asynchronous serial data exchange system and method based on FPGA

Info

Publication number: CN110377549B
Application number: CN201910581916.3A
Authority: CN
Inventors: 刘超
Original assignee: 716th Research Institute of CSIC; Jiangsu Jari Technology Group Co Ltd
Current assignee: 716th Research Institute of CSIC; Jiangsu Jari Technology Group Co Ltd
Priority date: 2019-06-30
Filing date: 2019-06-30
Publication date: 2023-04-07
Anticipated expiration: 2039-06-30
Also published as: CN110377549A

Abstract

The invention provides an asynchronous serial data exchange system based on an FPGA (field programmable gate array), which comprises the FPGA, a Schmidt inverter, a differential bus transceiver and a serial peripheral interface; the output end Y1 of the Schmitt phase inverter is connected with the input end Sin of the FPGA, the output end Y0 of the Schmitt phase inverter is connected with the input end A1, the output end En of the FPGA is respectively connected with the input end DE and the input end DE _ N of the differential bus transceiver, the output end Sout of the FPGA is connected with the input end D of the differential bus transceiver, the output end G of the differential bus transceiver is connected with the input end A0 of the Schmitt phase inverter, the VCC end of the differential bus transceiver is connected with a first input pin of the serial peripheral interface through a first fuse, the output end A of the differential bus transceiver is connected with a second input pin of the serial peripheral interface, the input end B of the differential bus retractor is connected with a third output pin of the serial peripheral interface, and the GND end of the differential bus transceiver is connected with a fourth pin of the serial peripheral interface.

Description

Asynchronous serial data exchange system and method based on FPGA

Technical Field

The invention relates to the technical field of electric signal transmission, in particular to an asynchronous serial data exchange system and method based on an FPGA (field programmable gate array).

Background

The asynchronous serial communication requires few transmission lines, has high reliability and long transmission distance, and is widely applied to data exchange between a micro control system and peripheral equipment. With the rapid development of the FPGA, the FPGA plays an increasingly important role in asynchronous serial communication. The asynchronous serial communication system based on the FPGA can effectively simplify circuit design, reduce the volume of a printed board, improve reliability and has higher flexibility in design. Asynchronous serial communication needs to process a data transceiving mechanism, bus direction adjustment, data frame check and the like well and has strict time sequence control requirements, so how to better process the time sequence mechanism is the key for improving the efficiency and reliability of asynchronous serial communication. At present, a plurality of solutions exist for asynchronous serial communication, but the problems of unclear transceiving mechanism flow, high bit error rate, incomplete fault event processing and the like exist more or less.

Disclosure of Invention

The invention aims to provide an asynchronous serial data exchange system and method based on an FPGA.

The first technical scheme for realizing the purpose of the invention is as follows: an asynchronous serial data exchange system based on an FPGA comprises the FPGA, a Schmidt inverter, a differential bus transceiver and a serial peripheral interface; the output end Y1 of the Schmitt phase inverter is connected with the input end Sin of the FPGA, the output end Y0 of the Schmitt phase inverter is connected with the input end A1, the output end En of the FPGA is grounded through a first resistor R1 and is also respectively connected with the input end DE and the input end DE _ N of the differential bus transceiver, the output end Sout of the FPGA is connected with the input end D of the differential bus transceiver, the output end G of the differential bus transceiver is connected with the working voltage 5V through a second resistor R2 and is also connected with the input end A0 of the Schmitt phase inverter, the VCC end of the differential bus transceiver is connected with the first input pin of the serial peripheral interface through a first fuse, the output end A of the differential bus transceiver is connected with the second input pin of the serial peripheral interface, the input end B of the differential bus transceiver is connected with the third output pin of the serial peripheral interface, the GND end of the differential bus transceiver is connected with the fourth pin of the serial peripheral interface, the third resistor R3 is connected in series between the VCC end of the differential bus transceiver and the output end A, the output end A of the differential bus transceiver is connected in series with a fifth resistor R5, and the output end B of the differential bus transceiver are connected in series with the fourth resistor R4.

The second technical scheme for realizing the aim of the invention is as follows: an asynchronous serial data exchange method based on FPGA realizes the sending and receiving of data frames by two finite state machines FSM; wherein

(1) The data transmission process comprises the following steps:

the FPGA writes instruction data into Buffer1, starts a finite state machine FSM, simultaneously adjusts the direction of a half-duplex bus to be sent by the FPGA, the FSM is switched to a Start1 state from an Idle1 state, and sends a data frame Start signal Start on a serial bus through a port Sout;

then switching to a Shift1 state, and sending the data in the Buffer1 to a serial bus through a port Sout;

after data transmission is finished, switching to a Stop1 state, and transmitting a data frame end signal Stop on the serial bus through a port Sout;

switching to an Idle1 state, and simultaneously adjusting the direction of the half-duplex bus to be received by the FPGA;

(2) The data receiving process comprises the following steps:

when the direction of the half-duplex bus is in an FPGA receiving state, after a valid data frame receiving Start signal Start is detected, starting a Finite State Machine (FSM) and switching to a Start2 state;

after the data frame Start signal Start is finished, switching to a Shift2 state, receiving data on a serial bus through a port Sin and writing the data into Buffer2;

after data reception is finished, switching to a Stop2 state, and receiving and checking whether a data frame end signal Stop is on a serial bus or not;

switching to an Idle2 state, and simultaneously adjusting the direction of the half-duplex bus to be transmitted by the FPGA;

in case the Data frame is verified correct and the end signal Stop is correct, buffer2 Data is given to Data.

By adopting the method, the bit data multi-sampling method is adopted, the bit values on the data bus are sampled 7 times and counted respectively in the period of keeping one bit, and a plurality of sampling values are taken as the true value of the bit at the end moment of one bit.

The invention simplifies the sending and receiving process of the data frame by adopting the form of the finite-state machine, and effectively reduces the conditions of high serial communication error rate, low communication efficiency, poor reliability and the like under the external interference by using the bit data multi-sampling method. A plurality of status flags are defined for indicating different communication events.

The invention is further described below with reference to the accompanying drawings.

Drawings

Fig. 1 is an electrical connection schematic.

Fig. 2 is a simplified flow diagram of data transmission.

Fig. 3 is a simplified flow chart of data reception.

Fig. 4 is a diagram illustrating a data frame format.

Fig. 5 is a schematic diagram of a data transmission mechanism based on FSM.

FIG. 6 is a schematic diagram of multiple sampling of bit data.

Fig. 7 is a schematic diagram of a data receiving mechanism based on FSM.

FIG. 8 is a diagram illustrating a received data check and status flag.

FIG. 9 is a timing diagram illustrating bus direction control.

Detailed Description

As shown in figure 1 of the drawings, in which, the circuit system comprises an FPGA (hereinafter referred to as a first unit U1), a Schmidt inverter 74HVC14 (hereinafter referred to as a second unit U2), a differential bus transceiver SN75176B (hereinafter referred to as a third unit U3), a serial Peripheral unit (hereinafter referred to as a fourth unit U4), a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a first fuse Fu1. Wherein, the first and the second end of the pipe are connected with each other,

an output end Y1 of the second unit U2 is connected to an input end Sin of the first unit U1, an output end Y0 of the second unit U2 is connected to an input end A1 of the second unit U2, an output end En of the first unit U1 is connected to GND through a first resistor R1, an output end En is connected to an input end DE of the third unit U3, an input end RE _ N of the third unit U3 is connected to an input end DE of the third unit U3, an output end Sout of the first unit U1 is connected to an input end D of the third unit U3, an output end R of the third unit U3 is connected to a power supply 5V through a second resistor R2, an output end R is connected to an input end A0 of the second unit U2, a power supply VCC of the third unit U3 is connected to a first pin of the fourth unit U4 through a first fuse Fu1, an end A of the third unit U3 is connected to a second pin of the fourth unit U4, an end B of the third unit U3 is connected to a third pin of the fourth unit U4, a third unit U3 is connected to a third pin B3 and a third terminal of the third unit U3, and a fifth unit U3, and a third unit U3 are connected to a third unit U3, and a fifth unit U3.

The invention is suitable for half-duplex communication, the third unit U3 is a differential bus transceiver SN75176B, and the second resistor R2 is a pull-up resistor which is used for pulling up the signal RD _ T to 5V. The second unit U2 is a schmitt inverter 74HVC14, and the schmitt inverter 74HVC14 functions to convert the 5V standard signal RD _ T into 3.3V standard RD and maintain the same phase. The first resistor R1 is a pull-down resistor and is used for pulling the RE _ N end and the DE end of the differential bus transceiver SN75176B down to GND, the third resistor R3 is a pull-up resistor and is used for pulling the A end of the differential bus transceiver SN75176B up to VCC, the fourth resistor R4 is a pull-down resistor and is used for pulling the B end of the differential bus transceiver SN75176B down to GND, and the fifth resistor R5 is used for differential mode signal matching.

As shown in fig. 2, the clock Clk _ FPGA on the FPGA side is 37.5M, and the clock Clk _ Peri on the serial peripheral side is 2.5M. The data sending process comprises the following steps:

the FPGA writes the instruction data into the Buffer1, starts a finite state machine FSM, and simultaneously adjusts the Direction of the half-duplex Bus to be sent by the FPGA, namely the Bus _ Direction =1. The FSM switches from Idle1 state to Start1 state and sends a Start signal Start of a data frame on the serial bus via port Sout. Then, the state is switched to Shift1 again, and the data in Buffer1 is sent to the serial bus through the port Sout. And after the data transmission is finished, switching to a Stop1 state, and transmitting a data frame end signal Stop on the serial bus through the port Sout. And finally, switching to an Idle1 state, and simultaneously adjusting the Direction of the half-duplex Bus to be received by the FPGA, namely Bus _ Direction =0.

As shown in fig. 3, the clock Clk _ FPGA on the FPGA side is 37.5M, and the clock Clk _ Peri on the serial peripheral side is 2.5M. The data receiving process comprises the following steps:

when the Direction of the half-duplex Bus is Bus _ Direction =0, that is, when receiving by the FPGA, the FSM is started and switched to the Start2 state when detecting a valid data frame reception Start signal Start. After the data frame Start signal Start ends, the state is switched to Shift2, and data on the serial bus is received through the port Sin and written into Buffer2. And after the data reception is finished, switching to a Stop2 state, and receiving and checking whether a data frame end signal Stop is on the serial bus or not. And finally, switching to an Idle2 state, adjusting the Direction of the half-duplex Bus to be transmitted by the FPGA, namely the Bus _ Direction =1, and endowing the Buffer2 Data to the Data under the condition that the Data frame is checked to be correct and the end signal Stop is correct.

As shown in fig. 4, for convenience in describing the principles of the present invention, it is assumed that the format of the data frame refers to fig. 3. One complete data is composed of 18 bits, including a Start bit Start code, an end bit Stop code and a 16-bit valid data bit Frame data.

For convenience of describing the principle of the present invention, assuming that the clock frequency Clk _ FPGA on the FPGA side is 37.5M and the clock frequency Clk _ Peri on the serial peripheral side is 2.5M, the number Δ n of FPGA clocks required for transmitting or receiving one bit on the FPGA side is 15 and the duration Δ t according to the baud rate matching method, the calculation is shown in the following formula.

Δt＝Δn*T _{Clk_Fpga} ＝15*T _{Clk_Fpga}

As shown in fig. 5, the FSM-based data transmission mechanism is driven by the rising edge of the clock frequency Clk _ Fpga, and is described in detail as follows:

after the FPGA writes the instruction data Cmd into the Buffer1, the signal Buffer1_ Empty is assigned with 0 at the same time, namely the Buffer1_ Empty < = '0', and after the finite state machine FSM detects that the Buffer1_ Empty is changed from 1 to 0, the finite state machine FSM is started and switched to the Start1 state, and the direction of the half-duplex bus is adjusted to be transmitted by the FPGA.

The data frame Start signal Start is sent in the Start1 state for a duration Δ t, which is the time of 15 Clk _ Fpga cycles, and the FSM switches to the Shift1 state after the counter _ Clk1 variable for counting the number of Clk _ Fpga clocks has been incremented to 15.

And sequentially sending the data in the Buffer1 to the serial bus in a Shift1 state in a cyclic Shift mode. The method specifically comprises the following steps: mapping the LSB bits to port Sout, i.e., sout < = Buffer1 (0), duration Δ t, i.e., the time of 15 Clk _ Fpga cycles; after the variable counter _ Clk1 for counting the number of Clk _ Fpga clocks is increased to 15, buffer1 is shifted to the right by one bit (Buffer 1< = '0' & Buffer1 (15downto 1)), and counter _ Clk1 is cleared (counter _ Clk1: = 0), while the variable counter1 for calculating the number of bits of transmission data is increased by 1 (counter 1: = counter1+ 1). The above process is repeated until counter1 equals 16 (counter 1= 16), i.e. the transmission of the 16-bit data frame has been completed, and the FSM switches to the Stop1 state.

When a data frame end signal Stop is transmitted in the Stop1 state, the duration Δ t, which is the time of 15 Clk _ Fpga cycles, is increased to 15, and then the counter _ Clk1 is cleared (counter _ Clk1: = 0) and the signal Buffer1_ Empty is given 1, i.e., buffer1_ Empty < = '1', after the variable counter _ Clk1 for counting the number of Clk _ Fpga clocks is increased to 15. Meanwhile, the FSM is switched to an Idle1 state, and the direction of the half-duplex bus is adjusted to be received by the FPGA.

In the Idle1 state, the counter _ clk1 is cleared (counter _ clk1: = 0), and the port is assigned a high impedance state (Sout < = z).

As shown in fig. 6, before describing the FSM-based data receiving mechanism in detail, the bit data multi-sampling method used in the present invention will be described. During serial communication, abnormal jump of bus data may be caused by external interference. When receiving data, if bit data at a certain time is sampled once, bit data may be sampled erroneously. The invention uses a bit data multi-sampling method, namely, in the bit receiving period, the bit values of 7 moments, such as the 1 st Clk _ Fpga moment, the 3 rd Clk _ Fpga moment, the 5 th Clk _ Fpga moment, the 7 th Clk _ Fpga moment, the 9 th Clk _ Fpga moment, the 11 th Clk _ Fpga moment and the 13 th Clk _ Fpga moment, are sequentially sampled, and a larger number (0 or 1) of the bit values is taken as the true value of the bit. The different times are counted by the variable count _ clk 2.

As shown in fig. 7, the FSM-based data reception mechanism is driven by the rising edge of the clock frequency Clk _ Fpga, described in detail as:

during the receiving state of the FPGA in the direction of the half-duplex bus, when a valid falling edge on the data bus is detected, falling _ edge (Sin) starts the FSM of the finite state machine and switches to the Start2 state, and simultaneously assigns 1 to the signal Buffer2_ Empty, i.e. Buffer2_ Empty < = '1', and 0 to the signal Rx _ err, i.e. Rx _ err < = '0'.

The data frame Start signal Start is received in the Start2 state, a method of multi-sampling bit data is adopted, specifically, the values of the serial bus are sampled at the arrival time of the 1 st Clk _ Fpga rising edge, the arrival time of the 3 rd Clk _ Fpga rising edge, the arrival time of the 5 th Clk _ Fpga rising edge, the arrival time of the 7 th Clk _ Fpga rising edge, the arrival time of the 9 th Clk _ Fpga rising edge, the arrival time of the 11 th Clk _ Fpga rising edge and the arrival time of the 13 th Clk _ Fpga rising edge, and the sampled 0 or 1 is respectively counted cumulatively by the variable cnt _ rxd0 and the variable cnt _ rxd 1. When the 15 th rising edge of Clk _ Fpga arrives, i.e. counter _ Clk2=15, if the number of sample values 0 is greater than the number of sample values 1, i.e. cnt _ rxd0> cnt _ rxd1, the FSM switches to the Shift2 state; conversely, if the number of sample values 0 is less than the number of sample values 1, i.e., cnt _ rxd0< cnt _ rxd1, indicating that a valid data frame Start signal Start has not been detected, the FSM transitions back to the Idle2 state. Meanwhile, a variable cnt _ rxd0 for counting the number of sampling values 0, a variable cnt _ rxd1 for counting the number of sampling values 1, and a variable counter _ Clk2 for counting the number of clocks of the Clk _ Fpga are respectively cleared, that is, cnt _ rxd0: =0, cnt_rxd 1= 0, counter _ _clk2= 0.

In the Shift2 state, 16-bit valid data on the serial bus are sequentially received into Buffer2 in a cyclic Shift mode. Judging and receiving each bit data of the data frame by adopting a bit data multi-sampling method, which specifically comprises the following steps: when the 1 st bit data of the data frame is received, the values of the serial bus are sampled at the 1 st Clk _ Fpga rising edge arrival time, the 3 rd Clk _ Fpga rising edge arrival time, the 5 th Clk _ Fpga rising edge arrival time, the 7 th Clk _ Fpga rising edge arrival time, the 9 th Clk _ Fpga rising edge arrival time, the 11 th Clk _ Fpga rising edge arrival time and the 13 th Clk _ Fpga rising edge arrival time, and the sampled 0 or 1 is accumulated and counted through a variable cnt _ rxd0 and a variable cnt _ rxd1 respectively. When the rising edge of the 15 th Clk _ Fpga arrives, i.e. counter _ Clk2=15, if the number of sample values 0 is greater than the number of sample values 1, i.e. cnt _ rxd0> cnt _ rxd1, the Buffer2 is cycled to the right by 1 bit, and the highest bit is complemented by 0, i.e. Buffer2< = '0' & Buffer2 (15downto 1); conversely, if the number of sample values 0 is less than the number of sample values 1, i.e., cnt _ rxd0< cnt _ rxd1, buffer2 is cycled to the right by 1 bit, and the highest bit is complemented by 1, i.e., buffer2< = '1' & Buffer2 (15downlnto 1). Meanwhile, the variables cnt _ rxd0, cnt _ rxd1 and counter _ clk2 are respectively cleared, that is, cnt _ rxd0: =0, cnt _rxd1: =0, counter _clk2: =0, and 1 is added to the variable counter2 for calculating the number of bits of received data (counter 2: = counter2+ 1). The above process is repeated until counter2 equals 16 (counter 2= 16), i.e. the reception process of the data frame 16 bits bit is completed, and the FSM switches to the Stop2 state.

The data frame end signal Stop is received in the Stop2 state, and the values of the serial bus are sampled at the 1 st Clk _ Fpga rising edge arrival time, the 3 rd Clk _ Fpga rising edge arrival time, the 5 th Clk _ Fpga rising edge arrival time, the 7 th Clk _ Fpga rising edge arrival time, the 9 th Clk _ Fpga rising edge arrival time, the 11 th Clk _ Fpga rising edge arrival time, and the 13 th Clk _ Fpga rising edge arrival time, respectively. When the rising edge of the 15 th Clk _ Fpga arrives, i.e. counter _ Clk2=15, if cnt _ rxd0> cnt _ rxd1, i.e. the number of sample values 0 is greater than the number of sample values 1, which indicates that the received data frame end signal Stop is erroneous, the signal Rx _ err is given as 1, i.e. Rx _ err < = '1', and the signal Buffer2_ Empty is given as 0, i.e. Buffer2_ Empty < = '0', FSM switches to the Idle2 state.

In the Idle2 state, the variables counter _ clk2, counter2, cnt _ rxd0 and cnt _ rxd1 are cleared respectively, i.e., counter _ clk2: =0, counter2: =0, cnt_rxd 0: =0, cnt _rxd1: =0.

As shown in fig. 8, at the time of the falling edge of Buffer2_ Empty, that is, falling _ edge (Buffer 2_ Empty), if the signal Rx _ err for indicating the data Frame reception status is equal to 0, that is, rx _ err = '0', which indicates that no data Frame reception error has occurred, the data in Buffer2 is moved into the Frame array. Assuming that 4 Frame Data (Frame 1, frame2, frame3 and Frame 4) exist in a complete Data receiving process, CRC check is started after 4 Frame Data are received, if a check result is equal to a corresponding value in a Data Frame, namely CRC _ value = Frame _ value, the received Data is restored and stored in a Data array in a specific manner, and meanwhile, a Data receiving completion flag Rx _ finish is set to 1, namely Rx _ finish =1.

As shown in fig. 9, the present invention relates to the direction of the serial bus, since it is applicable to half-duplex communication. Defining a signal Bus _ Direction to indicate the Direction of the serial Bus, and when the signal Bus _ Direction is set to be 1, indicating that the Direction of the serial Bus is transmitted by the FPGA; conversely, when the Bus _ Direction signal is set to 0, the Direction of the serial Bus is received by the FPGA. The signal Bus _ Direction is mapped to the En port of the FPGA in fig. 1.

When the rising edge of the Buffer1_ Empty comes, namely falling _ edge (Buffer 1_ Empty), indicates that the sending process of the data frame starts to be started, at this time, the signal Bus _ Direction is set to 1, namely the Bus _ Direction < = '1', and the Direction of the serial Bus is adjusted to be FPGA sending.

A variable count _ Clk is defined to count the number of Clk _ Fpga clocks, and 1 count is synchronously started when the rising edge of Buffer1_ Empty arrives, that is, count _ Clk = count _ Clk +1.

When the rising edge of the Buffer1_ Empty comes, namely rising _ edge (Buffer 1_ Empty), the transmission flow of the data frame is finished, at this time, the signal Bus _ Direction is set to 0, namely the Bus _ Direction < = '0', and the Direction of the serial Bus is adjusted to be received by the FPGA.

If Rx _ finish =1 is detected, namely the reception of all data frames (4 frames) is normally completed and the verification is correct, the signal Bus _ Direction is set to 1, namely the Bus _ Direction < = '1', and the Direction of the serial Bus is adjusted to be transmitted by the FPGA.

A variable const _ Clk, constant type, is defined, set to a value of m, which represents the number of Clk _ Fpga clocks. As shown in fig. 9, the m value is greater than the number of Clk _ Fpga clocks counted from the beginning of the rising edge of Buffer1_ Empty to the occurrence of event Rx _ finish =1, and is less than one complete data frame transmission and reception cycle, that is, less than the number of Clk _ Fpga clocks counted when the rising edge of Buffer1_ Empty comes next time.

A signal rx _ timeout is defined for indicating that the received data frame times out.

When the variable count _ clk count reaches const _ clk, i.e. m value, if the status flag rx _ finish is detected to be equal to 0, i.e. rx _ finish =0, indicating that the receiving of all data frames or the checking of errors still fails to be completed at this moment, setting the signal rx _ timeout to 1, i.e. rx _ timeout < = '1', indicating that the received data frame is timed out; conversely, if the status flag rx _ finish is detected to be equal to 1, indicating that the reception of all data frames (4 frames) has been completed normally before and the check is correct, the variable rx _ finish is set to 0, i.e., rx _ finish: =0.

When an rx _ timeout rising edge arrives, namely rising _ edge (rx _ timeout), a Bus _ Direction signal 1, namely Bus _ Direction < = 1', is adjusted to be transmitted by the FPGA in the Direction of the serial Bus.

When the next Clk _ Fpga rising edge arrives, if rx _ timeout equal to 1 is detected, rx _ timeout is set to 0, that is, rx _ timeout = '0'.

When a transition (rising edge or falling edge) of rx _ timeout is detected, which indicates that the receiving of all data frames is not completed or errors are checked according to the previous analysis, a received data frame timeout processing mechanism can be added at this time, and this part of the description and explanation is not repeated here.

The above is the adjustment timing sequence and mechanism of the Bus _ Direction value and the serial Bus Direction in the process of a complete data frame sending and receiving period.

Claims

1. An asynchronous serial data exchange system based on an FPGA is characterized by comprising the FPGA, a Schmidt inverter, a differential bus transceiver and a serial peripheral interface; wherein

The output end Y1 of the Schmidt inverter is connected with the input end Sin of the FPGA,

the output terminal Y0 of the schmitt inverter is connected to the input terminal A1,

the output end En of the FPGA is grounded through a first resistor (R1) and is also respectively connected with the input end DE and the input end DE _ N of the differential bus transceiver,

the output terminal Sout of the FPGA is connected to the input terminal D of the differential bus transceiver,

the output end G of the differential bus transceiver is connected with the working voltage 5V through a second resistor (R2) and is also connected with the input end A0 of the Schmidt inverter,

the VCC end of the differential bus transceiver is connected with the first input pin of the serial peripheral interface through a first fuse,

the output end A of the differential bus transceiver is connected with a second input pin of the serial peripheral interface,

the input end B of the differential bus retractor is connected with a third output pin of the serial peripheral interface,

the GND end of the differential bus transceiver is connected with the fourth pin of the serial peripheral interface,

a third resistor (R3) is connected in series between the VCC end and the output end A of the differential bus transceiver,

a fifth resistor (R5) is connected in series between the output end A and the output end B of the differential bus transceiver,

the output end B and the GND segment of the differential bus transceiver are connected with a fourth resistor (R4) in series;

defining a signal Bus _ Direction to indicate the Direction of the serial Bus, and when the signal Bus _ Direction is set to be 1, indicating that the Direction of the serial Bus is transmitted by the FPGA; on the contrary, when the signal Bus _ Direction is set to 0, the Direction of the serial Bus is received by the FPGA, and the signal Bus _ Direction is mapped to an En port of the FPGA;

the data frame is transmitted and received by two Finite State Machines (FSMs); wherein

(1) The data transmission process comprises the following steps:

after data transmission is finished, switching to a Stop1 state, and transmitting a data frame finishing signal Stop on the serial bus through a port Sout;

switching to an Idle1 state, and simultaneously adjusting the Direction of the half-duplex Bus to be received by the FPGA, namely Bus _ Direction = 0;

(2) The data receiving process comprises the following steps:

switching to an Idle2 state, and simultaneously adjusting the Direction of the half-duplex Bus to be FPGA transmission, namely Bus _ Direction = 1;

under the condition that the Data frame is checked to be correct and the ending signal Stop is correct, giving Buffer2 Data to Data;

and (3) adopting a bit data multi-sampling method, sampling the bit values on the data bus for 7 times during a bit holding period, respectively counting, and taking a larger number of sampling values as the true value of the bit at the end moment of the bit.

2. The asynchronous serial data exchange system based on FPGA of claim 1, wherein said 7 times of sampling the bit values on the data bus and counting respectively, specifically:

that is, in the bit reception period, the bit values at 7 times, such as the 1 st Clk _ Fpga time, the 3 rd Clk _ Fpga time, the 5 th Clk _ Fpga time, the 7 th Clk _ Fpga time, the 9 th Clk _ Fpga time, the 11 th Clk _ Fpga time, and the 13 th Clk _ Fpga time, are sequentially sampled, and the larger number thereof is taken as the true value of the bit.

3. The FPGA-based asynchronous serial data switching system of claim 1, wherein: defining a variable count _ Clk for counting the number of Clk _ Fpga clocks, and synchronously starting to count by 1 when a Buffer1_ Empty rising edge arrives, namely count _ Clk = count _ Clk + 1;

when the rising edge of Buffer1_ Empty comes, namely rising _ edge, the sending flow of the data frame is finished, and at the moment, the Bus _ Direction is set to be 0, namely the Bus _ Direction < = '0', and the Direction of a serial Bus is adjusted to be received by the FPGA;

if Rx _ finish =1 is detected, namely the receiving of all data frames is normally finished and the verification is correct, a signal Bus _ Direction is set to be 1, namely Bus _ Direction < = '1', and the Direction of the serial Bus is adjusted to be transmitted by the FPGA;

defining a constant type variable const _ Clk, setting the number of Clk _ Fpga clocks between a Buffer1_ Empty falling edge event and an Rx _ finish =1 event to be larger than the value m, and simultaneously setting the value m to be smaller than a complete data frame sending and receiving period, namely, the number of Clk _ Fpga clocks between two adjacent Buffer1_ Empty falling edge events is smaller;

defining a signal rx _ timeout for indicating a received data frame is timed out;

when the variable count _ clk count reaches const _ clk, i.e. m value, if the status flag Rx _ finish is detected to be equal to 0, i.e. Rx _ finish =0, indicating that the receiving of all data frames or the checking of errors still fails to be completed at this moment, setting the signal Rx _ timeout to 1, i.e. Rx _ timeout < = '1', indicating that the received data frame is timed out; on the contrary, if the state flag Rx _ finish is detected to be equal to 1, which indicates that the reception of all data frames has been normally completed before and the check is correct, the variable Rx _ finish is set to 0, that is, rx _ finish: = 0;

when the rising edge of rx _ timeout arrives, namely rising _ edge (rx _ timeout), adjusting the Direction of a signal Bus _ Direction to 1, namely Bus _ Direction < = '1', and transmitting the signal by the FPGA;

when the next Clk _ Fpga rising edge comes, if rx _ timeout is detected to be equal to 1, rx _ timeout is set to 0, that is, rx _ timeout < = '0';

when detecting that the rx _ timeout jumps, the rx _ timeout indicates that the rx _ timeout is not complete to receive all data frames or check errors, determines that a data frame reception timeout event occurs, forcibly adjusts the direction of the serial bus to be sent by the FPGA, and triggers a data frame reception timeout processing mechanism.