JPH0660885U - Information display device - Google Patents

Abstract

(57) [Summary] [Purpose] Regarding an information display device using a display unit,
An object of the present invention is to provide an information display device having a simple hardware configuration and capable of individually detecting a defective unit and performing display only by the remaining display units excluding the defective unit. [Composition] A display board having a plurality of display units connected in series, a control circuit, and a monitoring circuit are provided.
A display element array, a shift register for fetching a display signal, a bit counter for counting a clock signal, an address counter for counting a count-up pulse of the bit counter, an address setting switch, an address value and an address of the address setting switch. When the comparator produces a coincidence output, the display signal sent from the control circuit is taken into the shift register, and the taken-in display signal is produced. Is transferred to the monitoring circuit as a monitoring signal at a predetermined timing position.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an information display device using a display unit in which a large number of display elements are arranged in a matrix, and by displaying or extinguishing a display element at a desired position, a desired character or figure is displayed.

[0002]

[Prior art]

 An information display device of this type is known, for example, as shown in FIG. 5 (see Japanese Patent Publication No. 3-219960). This information display device comprises a plurality of display units U1 to Un connected in series, a control circuit 3 for controlling the lighting of these display units, and an error check circuit 2 for monitoring the display state of the display units. In the circuit 2, the first shift registers SA2 to SAn for holding the display signals that have passed through the respective display units and the second shift registers for directly holding the display signals for the respective display units output from the control circuit 3 are provided. By providing the shift registers SB1 to SBn and the comparison circuits C2 to Cn, the display signals held in the first shift registers SA2 to SAn in the comparison circuits C2 to Cn and the second shift registers SB2 to SBn are provided. It is designed to detect the abnormality of the display unit by monitoring the match / mismatch with the held display signals.

[0003]

[Problems to be solved by the device]

 However, in the conventional information display device, in addition to the display units U1 to Un, it is necessary to provide two systems of shift registers SA2 to SAn and SB1 to SBn for error checking, and the hardware configuration is required. Was complicated. Moreover, the error check circuit can identify only the abnormality of one display unit. For the display units after the abnormality occurrence, even if each display unit is normal, the abnormality occurs. There is a problem that normal display cannot be performed due to the influence of the display unit.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to individually detect a display unit in which a failure has occurred, even though the hardware configuration is simple. It is an object of the present invention to provide an information display device capable of displaying only on the remaining display units excluding the defective display unit by making it controllable.

[0005]

[Means for Solving the Problems]

 To achieve the above object, an information display device according to the present invention sends a display signal to a display panel configured by connecting a plurality of display units in series and a plurality of display units connected in series. A control circuit; and a monitor circuit for checking the display unit for each display unit and the monitor signal transferred from each display unit for checking the abnormality of each display unit. The display unit includes a display element array in which a large number of display elements are arranged in a matrix, a display element drive circuit having a shift register for taking in a display signal for controlling lighting of each display element of the display element array, and a clock signal. The bit counter that outputs a count-up pulse each time it counts up a predetermined value, and the count-up output by the bit counter. An address counter that counts pulses, an address setting switch that sets the unit address of the display unit, and a match output is generated when the address value set in the address setting switch and the count value of the address counter match. When the comparator produces a coincidence output, the display signal sent from the control circuit is fetched into the shift register in the display element drive circuit, and the fetched display signal is set to a predetermined value. The monitoring signal is transferred to the monitoring circuit at the timing position.

[0006]

[Action]

 When the comparator in each display unit generates the address coincidence output, the display signal sent from the control circuit is taken into the shift register in the display element drive circuit of the display unit, and the taken display signal is given. Transfer to the monitoring circuit as a monitoring signal at the timing position.

The monitoring circuit compares the display signal sent from the control circuit to each display unit with the above-mentioned monitoring signal transferred from each display unit at a predetermined timing to determine whether each display signal is displayed. Detects unit abnormality.

[0008]

【Example】

 Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram of a display unit used in the information display device of the present invention, and FIG. 2 is a block diagram of one embodiment of the information display device of the present invention constructed using the display unit of FIG.

First, the configuration of the display unit will be described with reference to FIG. In FIG. 1, 1 is a display unit, 2 is a display element array in which display elements such as LEDs are arranged in a matrix of 16 dots × 16 dots (= 256 dots), and 3 is each of the display element array 2. The display element drive circuit 4 for controlling the lighting of the LEDs counts the clock signal C, and outputs one count-up pulse each time counting up 256 clocks equal to the number of display elements of the display element array 2. A bit counter, 5 is an address counter for counting the count-up pulse output from the bit counter 6, 6 is an address setting switch for setting a unit address of the display unit 1 when incorporated in an information display device described later, and 7 is The address value set in the address setting switch 6 and the count value of the address counter 5 A comparator for generating a coincidence output when they match.

The display element drive circuit 3 has a 256-stage (16 × 16) shift register 31 for taking in the display signal D for the display unit sent from the control circuit of the information display device described later. , A latch circuit 32 for latching the display signal D fetched in the shift register 31 for lighting control, and lighting a corresponding display element in the display element array 2 according to the display signal D latched in the latch circuit 32. It is composed of a driver 33 for controlling.

The shift register 31 has a clock input terminal provided with a semiconductor switch 8 such as a tri-state buffer for controlling the opening / closing of the input of the clock signal C, and an output terminal provided with a semiconductor switch 9 for controlling the opening / closing of the output signal. They are connected to each other, and the switches 8 and 9 are made conductive only when the coincidence output is given from the comparator 7.

Reference numeral 10 is a signal line for a display signal D, 11 is a signal line for a monitor signal M, 12 is a signal line for a clock signal C, 13 is a signal line for a latch signal L, and 14 is a reset signal. It is a signal line for R.

The information display device of FIG. 2 is configured by using a plurality of display units having the above configuration. That is, in FIG. 2, 20 is a display panel configured to n display unit 1 ₀ to 1 _n-1 connected in series. A front external view of the display board 20 is shown in FIG. Each display unit 1 ₀ to 1 _n-1 which constitute the display panel 20 are beforehand unit address is assigned, for example, the display unit 1 ₀ address 0, the display unit 1 ₁ is address 1, the display unit 1 ₂ Is address 2, ... Display unit 1 _n-1 is set as address _n-1 . Each unit address is set to the address setting switch 6 in advance the display unit 1 ₀ in to 1 _n-1.

A control circuit 21 sends a display signal D, a clock signal C, a latch signal L, and a reset signal R to each display unit, and gives a display signal sent to each display unit to a monitor circuit 22, Reference numeral 22 is a monitor circuit for collating the display signal D of each display unit provided from the control circuit 21 with the monitor signal M transferred from each display unit through the monitor signal line 11.

Next, the operation of the information display device of the above embodiment will be described. As will be apparent from the following description, the information display apparatus of this embodiment repeats the display signal transfer process twice to write the display signal to each display unit and monitor the abnormality.

[0016] Prior to the start of the processing, the control circuit 21 first sends a reset signal R, resets all count values of the bit counter 4 and the address counter 5 of the display unit 1 ₀ in to 1 _n-1 to 0 To do. In this state, the transfer cycle of the first display signal is started, the display signal D ₀ to D _n-1 for each display unit 1 ₀ to 1 _n-1 from the control circuit 21 is synchronized with the clock signal C However, they are sequentially transmitted as serial signals in the order of addresses. In the case of this embodiment, each of the display signals D _{0 to} D _n-1 is composed of 256 bits, the same number as the number of display elements of the display element array 2.

First, the display signal D ₀ for the display unit at the address 0 position is transferred in synchronization with the clock signal C. Bit counter 4 of each display unit 1 ₀ in to 1 _n-1 starts counting the clock signal C, respectively. At this time, the count value of the address counter 5 in each of the display units 1 ₀ to 1 _n-1 has become 0 due to the reset. On the other hand, address 0 is set in the address setting switch of the display unit 1 _0.

[0018] Thus, simultaneously with the transfer processing of the display signal is started, only the comparator 7 of the display unit 1 ₀ is a first address 0 position generates a coincidence output, the display unit 1 ₀ within the semiconductor switch 8, 9 is set in the conductive state. As a result, the display signal D ₀ sent from the control circuit 21 via the signal line 10 1 is taken into the shift register 31 in the display unit 1 ₀ in synchronization with the clock signal C 1.

[0019] When the display signal D ₀ becomes 256-bit configuration are incorporated all the bits in the shift register 31 of the display unit 1 in the _0, respectively bit counter 4 also 256 clocks of the display unit 1 ₀ in to 1 _n-1 It counts up and outputs a count-up pulse to each address counter 5. As a result, the count value of the address counter 4 in each display unit is incremented by 1 to become the count value 1.

The control circuit 21 controls the display unit 1 at the address 0 position.₀Display signal D for ₀ Of the display unit 1 at the address 1 position following the transmission of₁Display signal D for₁ Is sent. At this time, since the address counter 4 in each display unit has the count value 1 as described above, the display unit 1 corresponding to the address 1 position is₁Only the comparator 7 of the above generates a coincidence output. Therefore, the display signal D₁Is the display unit 1 at address 1₁It is taken into only the shift register 31 of.

[0021] Thus, the display signal D ₀ ~D _n-1 which are sequentially transferred from the control circuit 21 includes a shift register 31 of the display unit _{1 0} ~1 n-1 of the corresponding address location Niso Resolution It is stored in sequence.

When the first display signal transfer cycle ends, the control circuit 21 sends out a reset signal R, and all the display units 1₀~ 1_n-1After resetting the count values of the respective bit counters 4 and address counters 5 to 0 again, the second display signal transfer cycle is started. Also in the second transfer cycle, the display signal D for the display unit at each address position is similarly to the first transfer cycle described above. ₀ ~ D_n-1Are sequentially transmitted in the order of addresses in synchronization with the clock signal C.

[0023] For the second round of transfer cycle, for example, when the display signal D ₀ for the display unit 1 ₀ address 0 position is transferred, the display signal D _0, the transfer of the first time as in the case of the cycle, it will be written while being shifted one bit to the shift register 31 of the display unit 1 ₀ address 0 position. Therefore, by rewriting the display signal D _0, the display signal D ₀ written in the first transfer cycle from the output terminal of the shift register 31 is outputted while being shifted by one bit, the display signal D ₀ It is transferred as a monitoring signal M to the monitoring circuit 22 through the semiconductor switch 9.

The monitor circuit 22 uses the display unit 1 transferred through the signal line 11.₀Display unit 1 provided from the monitor signal M and the control circuit 21₀Display signal D ₀ And are compared, and the match / mismatch is matched. Display unit 1 if the two signals match₀Indicates normal operation, and if they do not match, display unit 1₀Indicates that something is wrong. Therefore, from this collation result, the display unit 1₀It is possible to confirm whether or not there is a failure.

Each time the display signals D _{0 to} D _n−1 are transferred in the second transfer cycle, the transfer of the monitor signal M and the collating operation in the monitor circuit 22 are performed by the display units 1 ₀ to 1 _n−. The status of all display units is inspected by the monitoring circuit 22 by repeating the operation _{one by one} .

[0026] Then, sends the display signal D ₀ ~D _n-1, after confirming that there is no abnormality in all of the display unit _{1 0} ~1 n-1, and sends a latch signal L from the control circuit 21. This ensures that the display unit 1 ₀ to 1 _n-1 of the display signal stored in the second round of transfer cycles that are stored in the shift register 31 D ₀ to D _n-1, respectively of the display unit 1 ₀ It is latched by the latch circuit 32 of 1 _n-1 .

The driver 33 of each display unit turns on the display element at the corresponding position in the display element array 2 based on the latched display signal, and each display unit 1 ₀ to 1 _{n− of the} display plate 21. character or graphics is applied to the ₁ in each of the display signal D ₀ to D _n-1 are respectively displayed.

When an abnormality is found in the display unit in the second transfer cycle, for example, the position of the abnormal unit is displayed on a CRT screen (not shown) for monitoring, It is confirmed whether or not the faulty unit corresponds to the lighting unit position of the character or figure displayed on the display board 20, and if there is a match, a measure such as shifting the display position of the character or figure is taken. After that, the transfer of the display signals D _{0 to} D _n-1 may be restarted. As a result, the target display can be performed using the display unit other than the faulty unit.

It should be noted that the determination as to whether or not the defective unit has a display problem is not limited to visual inspection on the CRT screen, but all 256 bits of the display signal D given from the control circuit 21 to the monitoring circuit 22 are determined. It is also possible to automatically determine in the monitoring circuit 10 by identifying whether the bit of "0" is "0", that is, whether any display element in the display element array 2 of the unit is not turned on. Is.

Further, a parallel input / serial output shift register is added in the display element drive circuit 3 of each display unit, and the display signal D stored in the latch circuit 32 is transferred as the monitor signal M at an arbitrary monitor timing. Therefore, it is possible to monitor at any timing position.

FIG. 4 shows another example of the display unit used in the information display device of the present invention. The display unit shown in FIG. 4 enables the address setting switch 6 to set two addresses k and k + 1, and a coincidence output is generated from the comparator 7 at the address k and the address k + 1 after the address k + 1. In addition to the above, a shift register 31 'having a data storage function is used. With such a configuration, the display signal D 1 is fetched and accumulated in the shift register 31 ′ during the coincidence output period of the first address k, and the 256 bits (1 address) of the display signal D 1 are accumulated during the subsequent output period of the address k + 1. With a phase delay, the display signal D stored in the shift register 31 'is transferred as the monitor signal M.

In the case of the circuit of FIG. 4, the comparator 7 needs to generate the coincidence output not only at the address k position but also at the address k + 1 position delayed by 256 clocks (1 address), and therefore the comparator 7 outputs the coincidence output. The clock signal C to be generated needs to be transmitted by 256 pulses more than the total number of bits of the display signals D _{0 to} D _n-1 . Further, since the shift register 31 'has a data storage function, the display signal D ₀ to D _n-1 of the transfer need only once, that an abnormality after the end transfer of the display signal in the monitoring circuit 22 is not detected After the confirmation, the latch signal L may be transmitted and the display signals D _{0 to} D _n-1 accumulated in the shift registers 31 ′ may be taken into the respective latch circuits 32. The configuration and operation of the other parts are the same as those of the first embodiment described above, and the description thereof is omitted.

[0033]

[Effect of device]

 As described above, according to the information display device of the present invention, since it is not necessary to provide a dedicated shift register for error checking, the hardware configuration of the entire device can be simplified. Further, since the position of the failed display unit can be detected individually and the display units can be individually controlled, desired information display can be performed only by the remaining normal display units excluding the failed display unit. It has an excellent effect of being able to do things.

[Brief description of drawings]

FIG. 1 is a block diagram of a display unit used in an information display device of the present invention.

FIG. 2 is a block diagram of an embodiment of the information display device of the present invention.

FIG. 3 is a front external view of a display plate portion of the information display device.

FIG. 4 is a block diagram showing another example of a display unit used in the information display device of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional information display device.

[Explanation of symbols]

1, 1 ₀ to 1 _n-1 Display unit 2 Display element array 3 Display element drive circuit 4 bit counter 5 Address counter 6 Address setting switch 7 Comparator 8, 9 Semiconductor switch 20 Display board 21 Control circuit 22 Monitoring circuit 31, 31 ′ Shift register D, D _{0 to} D _n-1 display signal M monitoring signal C clock signal L latch signal R reset signal

Claims (1)

[Scope of utility model registration request] 1. A display panel configured by connecting a plurality of display units in series, a control circuit for sending a display signal to the plurality of display units connected in series, and each control circuit provided by the control circuit. The display unit is provided with a monitoring circuit for checking the abnormality of each display unit by collating the display signal of the display unit with the monitoring signal transferred from each display unit, and the display unit is a display in which a large number of display elements are arranged in a matrix. An element array, a display element drive circuit having a built-in shift register for taking in a display signal for controlling the lighting of each display element of the display element array, a clock signal, and counting up each time a predetermined value is counted up. A bit counter for outputting a pulse, an address counter for counting the count-up pulse output by the bit counter, and a table It comprises an address setting switch for setting the unit address of the unit and a comparator for generating a coincidence output when the address value set in the address setting switch and the count value of the address counter coincide with each other. When an output is generated, the display signal sent from the control circuit is captured in the shift register in the display element drive circuit, and the captured display signal is transferred to the monitoring circuit as a monitoring signal at a predetermined timing position. An information display device characterized by the above.