SU1008745A1 - Function unit checking device - Google Patents

Abstract

1. A DEVICE FOR INSPECTION OF FUNCTIONAL BLOCKS, containing an input signal multiplexer, the output of which is connected to the input of the data register, the information input control unit, the clock generator, the service register, and the buffer. a nary register, a counter, a comparator and a test signal driver, IU e, so that, in order to reduce the test time, the address register, the command register, the address decoder, the command decoder, the manual input block, the mode switching unit and the display unit, the first and; the second information inputs of the multi; plexer input signals are connected respectively to the information input; the device input and the output of the manual input block, the output with the register-address and command register inputs, and the address input with the first output of the operating mode switch block: the second output of the generator connected to the input sync pulses, the output of which is connected to the (I / O line bus clock bus of the device and the first input of the test signal generator, which is connected via the command decoder to the output using the second route the register of commands and the control bus of the device I / O bus, and the third input to the address bus of the input / output bus and the address decoder to the output of the address register, the output of the data register is connected to the information bus of the input / output bus and the first inputs of the service and buffer registers, the second inputs of which are connected to the output of the driver of the test- ing signals, to the control bus of the I / O bus, to the first. to the input of the information input control unit and through the counter to the first input of the display unit, the second input of the information input control unit connected with the first output, the second output of which is connected to the device input synchronization output, and the second, third and fourth inputs respectively with the output of the service register The control mine of the I / O bus and the output of the comparator, the first input of which is connected to the output of the buffer re: gist, and the second to the information bus of the I / O bus. 2. The device according to claim 1, about tl and -; likely that the unit up-; The information input contains a comparison node, a switch, a manual start node for an input device and two OR elements, the first and second information inputs of the comparison node being connected respectively to the second and fourth inputs of the block,

Description

control input with first output. the switch and the output with the first input of the first OR element, the second and third inputs of which are connected respectively to the first input of the block and the second output of the switch, the input and third output of which are connected respectively to the third input of the block

and the first input of the second element OR, the second input of the manual start input device connected to the output, the outputs of the first and second elements OR are connected to the second output of the block, and the inputs of the first OR element and the output of the second OR element are connected to the first output of the block.

 one

The invention relates to a computing technique and can be used for test control of software-controlled blocks in a CAMAC system.

Devices for test control of logic blocks are known, comprising an input block, a control block, a switch, a comparator, a block of standards, a parameter control register, a data register, a comparison circuit, a display and output unit, and a time delay generating unit 1.

The disadvantage of these devices is limited scope.

Closest to the proposed technical solution is a device for controlling large integrated circuits containing a group of input drivers, the outputs of which are connected to the input of the tested circuit, and the input is connected to the memory output and one input of the comparator, the second input of which is connected to the output the test circuit, and the output through the error register with the fault indication LED of the digital computer, the comparison circuit, the first input polklyuchnnuyu through the address register to the first information output of the digital computer, the second input to you ode of the counter and the memory input, and the output to one input of the element I, the other input of which is connected to the clock pulse generator, and the output to the input of the counter and the first inputs of the switch and the buffer register, the second input of which is connected to the second information output of the digital computer, and the output to the second input of the switch, the third input connected via the control register to the control output of the digital computer, the fourth input to the first output of the trigger, and the output to the second input of the am, the third input of which is connected to the second output of the trigger This input is connected to the output of the DVR mode setting. t The disadvantage of this device is a large testing time and large hardware costs, which is caused by the impossibility of promptly checking one or a group of blocks without shutting down the object and the need to use a digital computer for monitoring.

The purpose of the invention is to reduce the inspection time and reduce hardware costs.

The goal is achieved in that the device containing the input multiplexer, the output of which is connected to the data register input, information input control unit, clock generator, service register, buffer register, counter, comparator, and test signal generator, has entered the address register, command register, an address decoder, a command decoder, a manual input unit, a mode switching unit and a display unit, the first and second information inputs of the multiplexer of the input signals of the connection here, respectively, with the information input of the device and the output of the manual input block, the output with the inputs of the address register and the command register, and the address input with the first output of the operating mode switching unit, the second output connected to the clock generator input, the output of which is connected to the clock bus of the input highway the output of the device and the first input of the tester shaper, the second input of the command through the decoder to the output of the command register and the control bus of the input-output circuit, and the third input - to the address bus of the I / O trunk and through the address decoder to the output of the address register, the output of the data register is connected to the information bus of the I / O bus and the first inputs of the service and buffer registers, the second inputs of which are connected to the test signal generator, to the input bus command bus - output, to the first input of the input control unit and through a counter to the first input of the display unit, the second input connected to the first output of the information input control unit, the second output cat The first is connected to the device input synchronization output, and the second, third, and fourth inputs, respectively, with the output of the service register, the control bus of the I / O line, and the output of the comparator, the first input of which is connected to the output of the buffer register, and the second to the information bus of the input highway - withdrawal.

The information input control block contains a comparison node, a switch, a manual start node of the input device and two OR elements, with the first and second information inputs of the comparison node being connected respectively to the second and fourth inputs of the block, the control input to the first output of the switch, and the output from the first input of the first element OR, the second and third inputs of which are connected respectively to the first input of the unit and the second output of the switch, the input and the third output of which are connected respectively to the third input of the unit and ervomu input of the second OR gate, a second input connected to the output node manual actuation of the input device, outputs the first and second OR elements are connected to the second output unit and the inputs of the first element and the output of the second-or-OR gate connected to the first output unit.

FIG. 1 is a block diagram of the device; in fig. 2 and 3 is a functional diagram of an information input control unit and an operation mode switching unit.

The device (fig. O contains a manual input block 1, input signal multiplexer 2, operating mode switching unit 3, data register k, address 5 register, decoder 6; addresses, command register 7, decoder 8 commands, driver 9 test signals , generator 10 clock pulses, service register 11, buffer register 12, comparator 13 information input control block T, counter 15. indication block 16, device input-output bus 17, device information input 18, information input synchronization output 19.

Information input control unit 1 (Fig. 2 contains elements

OR 20 and 21, switch 22, manual input device start node 23, and comparison node 2k. The operation mode switching unit 3 (FIG. 3) consists of a mode switch 25,

multiplexer 2b, node 27 of manual input of control pulses and node 28 of input of control pulses from an information input device.

The device works as follows.

The device implements the verification of computer system units (organized according to CAMAC standards. All units of this system (including

and the proposed device is connected to the input-output bus 17, over which information is exchanged.

The device can operate in manual and automated control modes.

13 of the first mode (manual control), the necessary information is generated using a keypad (for example, a toggle switch) of block 1. In the second mode (automated control), information is received at input 18 from an external source (for example, a computer, a punched tape reader or any device capable of store the verification program, test and reference test kits, etc.), and the output from such an external source is synchronized according to the signals from output 19 and

assistance of node 28 (external links of node 28 are not shown). The choice of the first or second mode is carried out by a switch 25 setting to the corresponding position multiplexers 2 and 26.

When addressing information into one of the functional blocks, which is connected to the device (crate controller) via trunk 17, information from the output of the H register goes to trunk 17, where the address and subaddress defined by the decoder 6 and register 7, respectively, are executed This function is a register 7.

So, for example, when forming the input action on the checked block, the data coming from the punched tape is recorded in the checked block on the corresponding subaddress; To synchronize all operations in the ACK, a generator of 10 sync pulses is provided, having an output to the bus 17. When addressing data to the device, the driver 9 generates the appropriate control signals for writing data to the buffer register 12 or to the service register 11.

The buffer register 12 is designed to store reference values.

The information entered into the buffer register 12 from the register is stored and transmitted to Comparator 13, S of which performs the function of comparing reference data and data arriving on the corresponding data reading buses from highway 17 and from the defect being checked. At the output of the comparator 13, signals of the result of comparing two numbers appear - from buffer register 12 and highway 17. Mode selection is performed programmatically and information about it is stored in service register 11, for example, when polling the output states of the tested block when exactly what should be the value of the parameter being tested, selects the equality mode; if the parameter to be checked; has a tolerance field, the mode is set to be larger or smaller, depending on what limit (lower or upper) it will be spent with comparing it with.

Thus, after the data sent to the tested block are formed, information defining the mode of operation of the comparator 13 is entered into the service register 11, and the reference value of the checked parameter is entered into the buffer register 12, the device sends a command to the trunk 17, which appears on the reading buses

state of outputs of the tested block Next, the comparator 13 compares two numbers and the result of the comparison is analyzed for compliance with the selected mode in the I block. When the comparison result matches the selected mode, the It block generates a signal allowing the external source of information to issue the next piece of information. Otherwise, the block And informs the operator about the failure, issuing appropriate signals in block 16, and. Stops the external source of information.

The It block can also ignore signals from the digital comparator, issuing signals to stop or start an external source of information on the signals of the imaging unit 9 or on the corresponding signals arriving on the busbars 17 from the functional blocks.

To locate the fault location in the device, a command counter 15 is used, which changes its state by 1 according to a signal from the driver 9. The sequence number of each executed command is indicated and when the program is stopped, it helps the operator to find the cause of the failure.

In block 16 of the display, signals such as Work, Stop on X, Stop on Q are provided (stop of program execution on signals received from line 17, Stop on a comparison scheme, (if the result of comparing two numbers in the comparator matches the selected mode) End of program and Transfer of control to operator. There is a program stop, if necessary, transfer control to the operator. If such a need arises, driver 9 sends a signal to the AND block, which causes the entire system to stop with the corresponding indication in block 16.

Thus, the device allows you to check the functioning of the system blocks without removing the boards from their workstations, which reduces the time of the test, the ability to check the blocks without using a digital computer, and reduces hardware costs.

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Claims (2)

1. DEVICE FOR CHECKING FUNCTIONAL BLOCKS, containing an input signal multiplexer, the output of which is connected to the data register input, an information input control unit, a clock generator, a service register, a buffer register, a counter, a comparator and a shaper of test signals, of which In addition, in order to reduce the verification time, an address register, an instruction register, an address decoder, an instruction decoder, a manual input unit, an operation mode switching unit and an indication unit are introduced into it, the first and * w The information inputs of the input signal multiplexer are connected respectively to the information input of the device and the output of the manual input unit, the output is with the inputs of the address register and the command register, and the address input is connected with the first output of the operation mode switching unit,: the second output of the clock generator connected to the input, the output which is connected to the clock bus of the device I / O line and the first input of the test signal shaper, the second input connected through the command decoder to the register output commands and the control bus of the device I / O line, and the third input to the address bus of the I / O line and through the address decoder to the output of the address register, the output of the data register is connected to the information * bus of the I / O line and the first inputs of the service and buffer registers, the second whose inputs are POD; are connected to the output of the test signal generator, to the command bus of the I / O line, to the first, the input of the information input control unit and through the counter to the first input of the display unit, the second input connected to the first output of the information input control unit, the second output of which is connected to the synchronization output input information of the device, and the second, third and fourth inputs, respectively, with the output of the service register, the control bus of the I / O line and the output of the comparator, the first input of which is connected: to the output of the buffer retister, and the second to the information bus of the I / O line. 2. The device according to π. 1, about t l and - _; reigning in that the unit is up-; equalization by input of information contains a comparison node, a “switch, · a node for manually starting an input device and; two OR elements, the first and second information inputs of the comparison node being connected respectively to the second and fourth” inputs of the block. a control input with the first output , the second input of the manual start device of the input device connected to the output, the outputs of the first and second OR elements are connected to the second output of the block, and the inputs of the first OR element and the output of the second OR element are connected to the first output block. ' 1