CN101419580B - Multi-load topological structure - Google Patents
Multi-load topological structure Download PDFInfo
- Publication number
- CN101419580B CN101419580B CN2007102022804A CN200710202280A CN101419580B CN 101419580 B CN101419580 B CN 101419580B CN 2007102022804 A CN2007102022804 A CN 2007102022804A CN 200710202280 A CN200710202280 A CN 200710202280A CN 101419580 B CN101419580 B CN 101419580B
- Authority
- CN
- China
- Prior art keywords
- receiving end
- tie point
- signal
- transmission line
- receiving terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4086—Bus impedance matching, e.g. termination
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The invention relates to a multi-load topological architecture which comprises a signal control terminal for sending drive signals. The signal control terminal is connected to a first connection point by a transmission line, the first connection point is connected to a first receiving terminal and a second connection point by two transmission lines, and the second connection point is connected to a second receiving terminal by a transmission line and connected to a third receiving terminal by a transmission line and a resistor, the difference values between the length of the transmission lines connecting the first receiving terminal and the second receiving terminal and the first connection point and the length of the transmission lines connecting the second receiving terminal and the third receiving terminal and the second connection point are greater than the product of the signal transmission speed of the drive signals and signal rise time, and the first receiving terminal does not have a data transmission function. The multi-load topological architecture can attenuate intensity of the signals entering the second receiving terminal by the resistor, and reduces the intensity of the signals reflected and returned by the resistor; meanwhile, the multi-load topological hardware architecture can enhance the intensity of the signals entering the third receiving terminal, avoid a non-monotonic phenomenon of the signals, and ensure the operating stability of a system.
Description
Technical field
The present invention relates to a kind of multi-load topological hardware structure.
Background technology
Development of electronic technology makes that the operating rate of IC (integrated circuit) is more and more faster; Frequency of operation is increasingly high; Load of design is that chip-count is also more and more on it; So the deviser time often need be connected to two even a plurality of chip with a signal controlling end in design, be used to said two even a plurality of chip signal is provided.
With reference to Fig. 1; It is multi-load topological structure figure in the prior art; Wherein include a signal controlling end 10 and four receiving ends 20,30,40,50; Adopt the daisy topology framework to be connected between wherein said signal controlling end 10 and four receiving ends 20,30,40 and 50, it includes three tie point A, B and C.
In this framework; Drive signal is to arrive each receiving end from signal controlling end 10s along transmission line; Because each receiving end skewness; Promptly from the signal of said signal controlling end 10s arrive each receiving end the length of transmission line of process can be different; Will have the delay of certain hour and said drive signal is every through the transmission line of a segment distance, if the difference in length of two transmission lines greater than the signaling rate of said drive signal and the product of signal elevating time, the received signal of the receiving end that then said two transmission lines are connected will be obviously asynchronous; Simultaneously; Because the distance between each receiving end differs bigger; Cause the reflected signal of receiving end far away can reflex to other nearer receiving end places, thereby make the signal that receiving end received of close together produce stack, can make its waveform between the rising stage, produce non-dullness (non-monotonic) phenomenon this moment; Influence the integrality and the function thereof of signal, caused sequential and digital operation mistake.
Please continue with reference to Fig. 2; It is for carrying out the oscillogram of simulating, verifying to the signal that multi-load among Fig. 1 received; Wherein signal curve 22,33,44 and 55 corresponds to the signal simulation curve of receiving end 20,30,40 and 50 respectively, and we can find out from figure, and said receiving end 20,40,50 corresponding signal simulation curves 22,44 and 55 produce serious non-dull phenomenon between the rising stage; It might influence the integrality of signal, more likely causes sequential and digital operation mistake.
Summary of the invention
In view of above content, be necessary to provide a kind of multi-load topological hardware structure, be used to weaken the nonmonotonicity of the signal that receiving end receives, with the stability of elevator system work.
A kind of multi-load topological hardware structure; Comprise that one is used to send the signal controlling end of drive signal; Said signal controlling end is connected to one first tie point through a transmission line; Said first tie point is connected to one first receiving end and one second tie point respectively via two transmission lines; Said second tie point is connected to one second receiving end and one the 3rd receiving end respectively via two transmission lines; Length of transmission line between said second receiving end and said first tie point greater than the difference in length value of length of transmission line between said first receiving end and first tie point and two transmission lines greater than the signaling rate of said drive signal and the product of signal elevating time; Length of transmission line between said the 3rd receiving end and said second tie point greater than the difference in length value of length of transmission line between said the 3rd receiving end and second tie point and two transmission lines greater than the signaling rate of said drive signal and the product of signal elevating time; Said first receiving end is one not have the receiving end of data-transformation facility, also is serially connected with a resistance between said second tie point and second receiving end.
Above-mentioned multi-load is opened up hardware and is pounced in the frame; Between second tie point and second receiving end, be connected in series a resistance, said resistance can be decayed and got into the signal intensity of said second receiving end, and reduces the signal intensity of its reflection passback; It can also promote the signal intensity that gets into said the 3rd receiving end simultaneously; Avoid it that non-dull phenomenon takes place, simultaneously, reduce its non-dull phenomenon so resistance need not be set because said first receiving end is one not have the receiving end of data-transformation facility; Can reduce the use amount of resistance in the whole framework, guarantee the stability of system works.
Description of drawings
Below in conjunction with accompanying drawing and preferred embodiments the present invention is described in further detail.
Fig. 1 is a multi-load topological hardware structure synoptic diagram in the prior art.
Fig. 2 is for carrying out the oscillogram of simulating, verifying to the signal that multi-load among Fig. 1 received.
Fig. 3 is the configuration diagram of multi-load topological hardware structure preferred embodiments of the present invention.
Fig. 4 is for carrying out the oscillogram of simulating, verifying to the signal that multi-load among Fig. 3 received.
Embodiment
With reference to Fig. 3; Multi-load topological hardware structure preferred embodiments of the present invention comprises a signal controlling end 100, four receiving ends 200,300,400,500, a resistance R S1 and some transmission lines; Wherein adopt the daisy topology mode to be connected between signal controlling end 100 and four receiving ends 200,300,400 and 500; Said signal controlling end 100 is connected to one first tie point A through a transmission line; The said first tie point A is connected to receiving end 200 and one second tie point B via two transmission lines respectively; The said second tie point B is connected to receiving end 300 and one the 3rd tie point C through two transmission lines respectively, and said the 3rd tie point C is connected to receiving end 400 and 500 through two transmission lines respectively.Said resistance R S1 is series between said second tie point B and the receiving end 300.
In the above-mentioned daisy topology framework; The length of the transmission line between said receiving end 300 and the said second tie point B greater than said receiving end 400 and 500 and the said second tie point B between the length of transmission line, and its difference value is greater than the signaling rate of the drive signal of being sent by said signal controlling end 100 and the product of signal elevating time.Said receiving end 400 and 500 and said the 3rd tie point C between the length of transmission line differ less, its difference value is less than or equal to the signaling rate of the drive signal of being sent by said signal controlling end 100 and the product of signal elevating time.Said receiving end 200 is debugging (Debug) device, and it only is used to assist to detect the content of host-host protocol, does not have data-transformation facility, and said receiving end 300,400 and 500 is the receiving end with data-transformation facility.
In the above-mentioned multi-load topological hardware structure; Drive signal arrives each receiving end 200,300,400 and 500 from said signal controlling end 100s along transmission line, said resistance R S1 can decay and got into the signal intensity of receiving end 300 this moment, thereby had reduced the signal intensity of said receiving end 300 reflection passbacks; It can also promote the signal intensity that gets into said the 3rd tie point C simultaneously; The signal quality that makes said receiving end 400 and 500 received is able to promote, and avoids it that non-dull phenomenon takes place, and guarantees the stability of system works; The characteristic impedance of the connected transmission line of resistance of wherein said resistance R S1 is complementary, and is used to reduce the generation of reflected signal.
Please continue with reference to Fig. 4; It is for carrying out the oscillogram of simulating, verifying to the signal that multi-load received in the multi-load topological hardware structure of the present invention; Wherein signal curve 222,333,444 and 555 corresponds to the signal simulation curve of receiving end 200,300,400 and 500 respectively; As can be seen from the figure, the signal that receives except said receiving end 200 has produced the tangible non-dull phenomenon, and the signal that other receiving ends received does not all have tangible non-dull phenomenon and produces.Because said receiving end 200 is a debugging apparatus; It only is used to assist to detect the content of transfer protocol; So can ignore the non-dull phenomenon of its signal that receives, promptly not be used in and another resistance is set between the said first tie point A and the second tie point B strengthens its signal intensity of entering, thereby can reduce the use amount of resistance in the whole daisy topology framework; Both save cost, can also reduce the delay of signals time that arrives each receiving end.If said receiving end 200 is one to have the receiving end of data-transformation facility; Then need between the said first tie point A and the second tie point B, another resistance be set; Be used to avoid its signal that receives that non-dull phenomenon takes place, its principle is identical with said resistance R S1.
Above-mentioned embodiment is that example describes with three branch circuits, three tie points; It also can be suitable for the framework that other chrysanthemum topology modes connect; At the tie point place, if the difference in length value of the length of a transmission line and another transmission line then is provided with a resistance greater than the signaling rate and the signal elevating time of the drive signal of being sent by said signal controlling end 100 on than long transmission line; If what link to each other with one of two transmission lines is a debugging apparatus; Then resistance need be set, to reduce the use amount of resistance, the stability of enhanced system work.
Claims (4)
1. multi-load topological hardware structure; Comprise that one is used to send the signal controlling end of drive signal; Said signal controlling end is connected to one first tie point through a transmission line; Said first tie point is connected to one first receiving end and one second tie point respectively via two transmission lines; Said second tie point is connected to one second receiving end and one the 3rd receiving end respectively via two transmission lines; Length of transmission line between said second receiving end and said first tie point greater than the difference in length value of length of transmission line between said first receiving end and first tie point and two transmission lines greater than the signaling rate of said drive signal and the product of signal elevating time; Length of transmission line between said second receiving end and said second tie point greater than the difference in length value of length of transmission line between said the 3rd receiving end and second tie point and two transmission lines greater than the signaling rate of said drive signal and the product of signal elevating time; It is characterized in that: said first receiving end is one not have the receiving end of data-transformation facility, is serially connected with a resistance between said second tie point and second receiving end.
2. multi-load topological hardware structure as claimed in claim 1; It is characterized in that: be provided with one the 3rd tie point between said second tie point and the 3rd receiving end; Said the 3rd tie point links to each other with one the 4th receiving end through another transmission line, and the length of transmission line difference value between said the 3rd receiving end and the 4th receiving end and said the 3rd tie point is less than or equal to the signaling rate of said drive signal and the product of signal elevating time.
3. multi-load topological hardware structure as claimed in claim 1 is characterized in that: the characteristic impedance of the connected transmission line of resistance of said resistance is complementary.
4. multi-load topological hardware structure as claimed in claim 1 is characterized in that: said first receiving end is a debugging apparatus.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2007102022804A CN101419580B (en) | 2007-10-26 | 2007-10-26 | Multi-load topological structure |
US11/955,409 US7746195B2 (en) | 2007-10-26 | 2007-12-13 | Circuit topology for multiple loads |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2007102022804A CN101419580B (en) | 2007-10-26 | 2007-10-26 | Multi-load topological structure |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101419580A CN101419580A (en) | 2009-04-29 |
CN101419580B true CN101419580B (en) | 2012-03-28 |
Family
ID=40582093
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007102022804A Expired - Fee Related CN101419580B (en) | 2007-10-26 | 2007-10-26 | Multi-load topological structure |
Country Status (2)
Country | Link |
---|---|
US (1) | US7746195B2 (en) |
CN (1) | CN101419580B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101887712B (en) * | 2009-05-15 | 2014-12-17 | 深圳市齐创美科技有限公司 | RGB (Red, Green and Blue) signal overdrive topological structure |
CN102957411A (en) * | 2011-08-25 | 2013-03-06 | 鸿富锦精密工业(深圳)有限公司 | Multi-load topological hardware framework |
CN102958268A (en) * | 2011-08-30 | 2013-03-06 | 鸿富锦精密工业(深圳)有限公司 | Printed circuit board |
CN103870431A (en) * | 2012-12-17 | 2014-06-18 | 鸿富锦精密工业(武汉)有限公司 | Multi-load topology wiring framework |
CN105871353B (en) * | 2016-06-22 | 2019-03-15 | 迈普通信技术股份有限公司 | A kind of multi-load circuit and device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1663119A (en) * | 2002-04-19 | 2005-08-31 | 英特尔公司 | Interconnecting of digital devices |
CN1829414A (en) * | 2005-03-03 | 2006-09-06 | 日本电气株式会社 | Transmission line and wiring forming method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4356462A (en) * | 1980-11-19 | 1982-10-26 | Rca Corporation | Circuit for frequency scan antenna element |
US5126704A (en) * | 1991-04-11 | 1992-06-30 | Harris Corporation | Polyphase divider/combiner |
-
2007
- 2007-10-26 CN CN2007102022804A patent/CN101419580B/en not_active Expired - Fee Related
- 2007-12-13 US US11/955,409 patent/US7746195B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1663119A (en) * | 2002-04-19 | 2005-08-31 | 英特尔公司 | Interconnecting of digital devices |
CN1829414A (en) * | 2005-03-03 | 2006-09-06 | 日本电气株式会社 | Transmission line and wiring forming method |
Also Published As
Publication number | Publication date |
---|---|
US7746195B2 (en) | 2010-06-29 |
US20090108956A1 (en) | 2009-04-30 |
CN101419580A (en) | 2009-04-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101419580B (en) | Multi-load topological structure | |
JP4712006B2 (en) | Equipment and systems | |
CN101452434A (en) | Multi-load topological structure | |
CN100447771C (en) | Universal serial bus transmitter | |
US20130166954A1 (en) | Test apparatus for testing signal transmission of motherboard | |
US11343065B2 (en) | Serial bidirectional communication circuit and method thereof | |
KR100959846B1 (en) | Differential signal transmitting apparatus and differential signal receiving apparatus | |
US8510485B2 (en) | Low power digital interface | |
CN102111142A (en) | Interface apparatus for semiconductor integrated circuit and interfacing method thereof | |
CN102958268A (en) | Printed circuit board | |
US6708238B1 (en) | Input/output cell with a programmable delay element | |
CN102957411A (en) | Multi-load topological hardware framework | |
CN104597822A (en) | Digital input line break detection method and circuit | |
CN101187950A (en) | Multi-load topology cabling architecture | |
US20080309354A1 (en) | Method and apparatus for testing characteristic impedance of transmission lines | |
US5388225A (en) | Time-domain boundary bridge method and apparatus for asynchronous sequential machines | |
CN110823281B (en) | Circuit arrangement | |
CN101420250B (en) | Switching device | |
CN101452050B (en) | IOB test method | |
CN101853825B (en) | Multi-load topology framework | |
TWI442700B (en) | Topology structure of multiple loads | |
CN107741919B (en) | Data communication device applied to control system | |
US20140239971A1 (en) | Debugging circuit and circuit board using same | |
US6430198B1 (en) | Apparatus and method of reducing packet length count processing | |
CN100405336C (en) | Wiring architecture for transmission wires in high speed printed circuit board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120328 Termination date: 20141026 |
|
EXPY | Termination of patent right or utility model |