JP3589752B2 - Frame synchronization circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frame synchronization circuit.
When generating a frame signal, the frame synchronization circuit generates a frame timing pulse for determining a frame signal interval by synchronizing two types of frame timing pulses having different frequencies.
[0002]
For example, in digital mobile communication, the present invention is applied to a circuit that synchronizes two frame timing pulses generated using output clocks having different frequencies of two PLL circuits.
[0003]
[Prior art]
FIG. 8 shows a block diagram of a conventional frame synchronization circuit, and its description will be given. The frame synchronization circuit shown in FIG. 8 generates one frame timing pulse FP synchronized with the two systems of the first and second frame timing pulses FP1 and FP2. It includes units 3, 4, a retiming circuit 5, a selector unit 6, a frame counter unit 7, a synchronization monitoring circuit 8, and a synchronization protection circuit 9.
[0004]
The PLL circuits 1 and 2 generate different clock signals CK2 and CK3 having different frequencies from the same phase synchronization clock signal CK1. The frame timing generators 3 and 4 generate first and second frame timing pulses FP1 and FP2 having different periods from the clock signals CK2 and CK3.
[0005]
The retiming circuit 5 synchronizes by adjusting the pulse widths and periods of the two frame timing pulses FP1 and FP2, and generates a third frame timing pulse FP3 synchronized with the two frame timing pulses FP1 and FP2. .
[0006]
This third frame timing pulse FP3 is supplied to the selector section 6 and the synchronization monitoring circuit 8 shown in FIG.
At the initial stage, the third frame timing pulse FP3 is input to the frame counter unit 7 via the selector unit 6. The frame counter 7 generates a frame timing pulse FP at a cycle of one frame of the frame timing pulse FP3.
[0007]
The generated frame timing pulse FP is output as a desired frame timing pulse FP and is supplied to the synchronization monitoring circuit 8. The synchronization monitoring circuit 8 monitors the pulse positions of the frame timing pulses FP3 and FP, and outputs a “H” pulse to the synchronization protection circuit 9 if they match, and outputs an “L” pulse if they do not match.
[0008]
When "H" is input N times in a row, the synchronization protection circuit 9 determines that the signal is in a synchronized state (backward protection), outputs a "H" synchronization state signal H1 to the selector unit 6, and outputs the "H" state in a continuous manner M times. When “L” is input, it is determined that an out-of-synchronization state has occurred (forward protection), and an “L” synchronization state signal H 1 is output to the selector unit 6.
[0009]
When the synchronization state signal H1 is "H" indicating the synchronization state, the selector section 6 selects the third frame timing pulse FP3 and outputs it to the frame counter section 7, and when the synchronization state signal H1 is "L" indicating the out-of-synchronization state. The frame timing pulse FP is selected and output to the frame counter 7.
[0010]
That is, the frame counter unit 7 outputs a pulse synchronized with the third frame timing pulse FP3 as the frame timing pulse FP in the synchronous state, and outputs the frame timing synchronized with the previously output frame timing pulse FP in the unsynchronized state. The pulse FP is output.
[0011]
[Problems to be solved by the invention]
By the way, in the above-mentioned conventional frame synchronization circuit using the front protection and the rear protection, two frame timing pulses FP1 and FP2 are generated by different PLL circuits 1 and 2, respectively. The phase fluctuations of the two systems of frame timing pulses FP1 and FP2 due to the frequency fluctuations of 1 and 2 may cause an out-of-synchronization state even once synchronization is established, and it takes a long time until complete synchronization is established. In addition, there is a problem that the circuit size of the synchronization protection circuit 9 increases because the number of rear protection stages must be increased.
[0012]
Further, the output frequency of the PLL circuits 1 and 2 fluctuates due to the temperature change during operation, and the pulse positions of the two frame timing pulses FP1 and FP2 generated from the output frequencies of the PLL circuits 1 and 2 also fluctuate. The output position of the third frame timing pulse FP3 after retiming by the retiming circuit 5 also fluctuates, resulting in a problem of an out-of-synchronization state.
[0013]
Furthermore, in the case of frequency fluctuations occurring under such a temperature condition or the like, there is a problem that the synchronized state and the out-of-synchronization state are repeated even though it is originally preferable to maintain the synchronized state.
[0014]
The present invention has been made in view of such a point, it is possible to eliminate out-of-synchronization due to frequency fluctuations caused by temperature changes and the like, and it is possible to make synchronization at power-on as fast as possible. An object of the present invention is to provide a frame synchronization circuit capable of reducing the size of a synchronization protection circuit.
[0015]
[Means for Solving the Problems]
FIG. 1 shows a principle diagram of a frame synchronization circuit of the present invention. This frame synchronization circuit synchronizes with the first and second frame pulses after generating first and second frame pulses for synchronizing frames from clock signals having different frequencies generated by two systems of PLL processing. Retiming means 100 for generating one third frame pulse FP3; selector means 6 for selecting one of the third frame pulse FP3 and the frame timing pulse FP obtained in the final stage according to a synchronization state signal; A frame counter means 7 for generating a frame timing pulse FP at one cycle interval of the pulse selected by the means 6, a synchronization monitoring means 8 for determining whether or not the third frame pulse FP3 and the frame timing pulse FP match, When a predetermined number of coincidences of the determination results of the synchronization monitoring means 8 are consecutive, the synchronization status is indicated. A first synchronization protection means for outputting a state signal and outputting a synchronization state signal indicating an out-of-synchronization state when a predetermined number of mismatches have occurred consecutively. The third frame pulse FP3 is selected to indicate the state, and the frame timing pulse FP is selected to indicate the out-of-synchronization state. A feature of the present invention is that the third frame pulse FP3 has a predetermined pulse width synchronized with the frame timing pulse FP. An aperture generating means 11 for generating an aperture signal, a synchronous state is determined if the third frame pulse FP3 is included in the aperture signal, and an out-of-synchronous state is determined if the third frame pulse FP3 is not included in the aperture signal, and this determination result is output to the first synchronous protection means 9. The first processing is started when the synchronization state signal indicates the synchronization state, and the previous processing is stopped when the synchronization state signal indicates the out-of-synchronization state. ; And a synchronization protection unit 10 lies in the configuration.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of a frame synchronization circuit according to an embodiment of the present invention. In this figure, parts corresponding to the respective parts of the conventional example shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted.
[0017]
In FIG. 2, reference numeral 10 denotes a synchronization protection circuit, and 11 denotes an aperture generation unit. In this embodiment, the retiming circuit 5 includes flip-flops (FF) 31, 32, 33, 34 and AND circuits 35, 36 as shown in FIG.
[0018]
The operation of the retiming circuit 5 shown in FIG. 3 will be described with reference to FIG.
The first frame timing pulse FP1 is supplied as data to the FF 31, and the supplied data is triggered by a clock signal CK3 synchronized with the second frame timing pulse FP2.
[0019]
The data held in the FF 31 by this trigger is output from the inverted output terminal XQ and supplied to the FF 32, and the supplied data is triggered and held by the clock signal CK3. The AND circuit 35 performs an AND operation on the data from the XQ of the FF 32 and the data from the XQ of the FF 31 to output data D1 shown in FIG.
[0020]
The "H" level portion of the data D1 has the same cycle as the first frame timing pulse FP1 and has the same pulse width as the second frame timing pulse FP2.
[0021]
When the data D1 is input to the clock terminal CLK of the FF 33, the FF 33 holds and outputs “H” data at the rising edge of the data D1. This output data D2 is supplied to the AND circuit 36.
[0022]
On the other hand, the second frame timing pulse FP2 is supplied to the AND circuit 36, and the logical product of the second frame timing pulse FP2 and the "H" portion of the data D2 is obtained, so that the second frame timing pulse FP1 has the same period as the first frame timing pulse FP1. A third frame timing pulse FP3 having the same phase as the pulse FP2 is generated.
[0023]
The aperture generation unit 11 shown in FIG. 2 detects a pulse portion of the frame timing pulse FP output from the frame counter unit 7, and takes a predetermined time width before and after the detected pulse portion to generate an “H” level portion. Is generated.
[0024]
The synchronization protection circuit 10 determines that the synchronous state is established when the second frame timing pulse FP3 is included in the "H" portion of the aperture signal A1, and operates when the synchronous state signal H1 is "L" indicating loss of synchronization. Instead, it operates at the time of "H".
[0025]
Further, the result of the logical sum of the output signal indicating the synchronization state of the synchronization protection circuit 10 and the output signal of the synchronization monitoring circuit 8 is input to the synchronization protection circuit 9 via the OR circuit 13.
[0026]
In such a configuration, for example, when the frame synchronization circuit is in a state immediately after the power is turned on and is out of synchronization, the synchronization protection circuit 10 does not operate because the synchronization state signal H1 becomes "L", and the frame synchronization protection is not performed. Is performed by the synchronization protection circuit 9.
[0027]
Here, when the synchronization state N times is detected by the synchronization protection circuit 9, the synchronization state signal H1 becomes "H" and the synchronization protection circuit 10 operates.
On the other hand, when the frame timing pulse FP supplied from the frame counter unit 7 is input to the aperture generation unit 11, an aperture having a specific width is opened by the aperture signal A1 and is input to the synchronization protection circuit 10.
[0028]
The synchronization protection circuit 10 monitors whether or not the frame timing pulse FP3 is detected in the aperture, and outputs an “H” pulse to the synchronization protection circuit 9 via the OR circuit 13 when detected.
[0029]
In this case, the output signal of the synchronization monitoring circuit 8 is ignored, and the synchronization protection circuit 9 outputs the synchronization state signal H1 of “H” as long as the input signal is “H”. The forward protection is switched to the synchronization protection circuit 10, and the synchronization protection circuit 10 performs aperture type forward protection.
[0030]
Here, when the frame timing pulse FP3 is not detected in the aperture, the synchronization protection circuit 10 outputs an “L” pulse. In this case, the pulse output from the synchronization monitoring circuit 8 becomes valid, and the protection of synchronization is switched to the synchronization protection circuit 9 again.
[0031]
Therefore, if the phase of the frame timing pulse FP3 after retiming also fluctuates due to the phase fluctuation of the two frame timing pulses FP1 and FP2 due to the output frequency fluctuation of the PLL circuits 1 and 2 when the power is turned on, there is a conventional case. The synchronization protection circuit 9 alone repeats the synchronization / out-of-synchronization state until the PLL circuits 1 and 2 are stabilized. However, the synchronization protection circuit 10 added in the present embodiment once establishes synchronization in the synchronization protection circuit 9. And the fluctuation of the frame timing pulse FP3 within the aperture can be regarded as synchronized, and as a result, the time for establishing synchronization from the time of turning on the power can be shortened.
[0032]
Further, even when a frame timing phase change due to a temperature change during operation occurs, it can be regarded as synchronized as long as the frame timing pulse FP3 is detected in the aperture, so that unnecessary loss of synchronization can be avoided. .
[0033]
The aperture generation unit 11 shown in FIG. 2 can be configured using a ROM, for example, as indicated by reference numeral 40 in FIG. The synchronization monitoring circuit 8 and the synchronization protection circuits 9 and 10 can have, for example, the circuit configuration shown in FIG. That is, as shown in FIG. 6, the synchronization monitoring circuit 8 uses the AND circuit 43, the synchronization protection circuit 10 uses the FF 45, and the synchronization protection circuit 9 includes the n-stage shift register FFs 47, 48, and 49. It is configured using NAND circuits 50, 51, 52 and 53.
[0034]
This operation will be described with reference to the timing chart of FIG. The third frame timing pulse FP3 shown in FIG. 2 is input to the frame counter unit 7, and the frame counter unit 7 generates a frame timing pulse FP having the same cycle as the frame timing pulse FP3.
[0035]
The AND circuit 43, which is the synchronization monitoring circuit 8, takes the logical product of the pulses FP3 and FP, outputs this as data D3, and inputs it to the OR circuit 13. The other input of the OR circuit 13 receives a signal from the FF 45, which is the synchronization protection circuit 10, but the synchronization is not established at this time, that is, the synchronization state signal H1 output from the NAND circuit 52 is "L". Since the signal of “L” is output from the FF 45, the data D 3 is directly input to the FF 47 of the synchronization protection circuit 9.
[0036]
Here, the N-stage rear protection and the M-stage front protection are performed by the FFs 47 to 49 and the NAND circuits 50 and 51, and the results are input to the NAND circuits 52 and 53. Here, the operation of the NAND circuits 52 and 53 outputs an "H" level when the N-stage backward protection condition is satisfied, and outputs an "L" -level synchronization state signal H1 when the M-stage forward protection condition is satisfied.
[0037]
When the synchronization state signal H1 becomes “H”, the reset (RESET) of the FF 45 is released. On the other hand, the aperture signal A1 is input to the ROM 40 shown in FIG. 5 using the output data of the frame counter unit 7 as an address, and a specific “H” level signal is provided at a position where the frame timing pulse FP3 shown in FIG. Expand the width aperture.
[0038]
The aperture is triggered by the frame timing pulse FP3 in the FF 45, and the output data is input to the OR circuit 13. That is, "H" is output while the frame timing pulse FP3 is within the aperture, and "L" is output when the frame timing pulse FP3 is out of the aperture.
[0039]
When the output of the FF 45 is always "H", the output of the OR circuit 13 is "H". Therefore, even if the output of the AND circuit 43, that is, the position of the frame pulse FP3 does not coincide with the position of the FP, the fluctuation of the FP3 does not change. Is within the range of the aperture, it can be determined that the camera is in a synchronized state.
[0040]
By setting the width of the aperture to a width that can withstand the frequency fluctuation during the operation of the PLL, it is possible to avoid the loss of synchronization due to the frequency fluctuation of the PLL.
[0041]
【The invention's effect】
As described above, according to the frame synchronization circuit of the present invention, it is possible to eliminate out-of-synchronization due to frequency fluctuations caused by temperature changes and the like, and to make synchronization establishment at power-on as fast as possible. There is an effect that the synchronization protection circuit can be downsized.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is a block diagram of a frame synchronization circuit according to an embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of a retiming circuit.
FIG. 4 is a timing chart for explaining the operation of the retiming circuit shown in FIG. 3;
FIG. 5 is a configuration diagram when a ROM is used for the aperture generation unit shown in FIG. 2;
FIG. 6 is a specific circuit diagram of a main part shown in FIG. 2;
FIG. 7 is a timing chart for explaining the operation of FIGS. 5 and 6;
FIG. 8 is a block diagram of a conventional frame synchronization circuit.
[Explanation of symbols]
6 selector means 7 frame counter means 8 synchronization monitoring means 9 first synchronization protection means 10 second synchronization protection means 11 aperture generation means 100 retiming means FP3 third frame pulse FP frame timing pulse

Claims (5)

After generating first and second frame pulses for synchronizing frames from clock signals having different frequencies generated by the two systems of PLL processing, one third frame synchronized with the first and second frame pulses is generated. Retiming means for generating a pulse; selector means for selecting one of the third frame pulse and the frame timing pulse obtained in the final stage according to a synchronization state signal; Frame counter means for generating the frame timing pulse at one cycle interval, synchronization monitoring means for determining whether the third frame pulse matches the frame timing pulse, and coincidence which is a result of the synchronization monitoring means The synchronization status signal indicating the synchronization status is output when a predetermined number of consecutive errors occur. First synchronization protection means for performing synchronization protection for outputting the synchronization state signal indicating an out-of-sync state, wherein the selector means selects the third frame pulse when the synchronization state signal indicates a synchronization state; In a frame synchronization circuit that selects the frame timing pulse when indicating an out-of-sync state,
Aperture generating means for generating an aperture signal having a predetermined pulse width synchronized with the frame timing pulse,
If the third frame pulse is included in the aperture signal, the synchronization state is determined. If the third frame pulse is not included, an out-of-synchronization state is determined. A process of outputting the determination result to the first synchronization protection unit is performed. A frame synchronization circuit comprising: a second synchronization protection unit that starts the processing when the synchronization state is indicated, and stops the processing when the synchronization state is lost. The first synchronization protection unit performs the synchronization protection using the determination result of the second synchronization protection unit when the second synchronization protection unit is performing the processing, and performs the synchronization protection when the processing is not performed. 2. The frame synchronization circuit according to claim 1, wherein said synchronization protection is performed using a result of determination by said synchronization monitoring means. When the first synchronization protection means detects a synchronization state from the determination result of the synchronization monitoring means at an initial stage, the first synchronization protection means performs the synchronization protection using the determination result of the second synchronization protection means. 3. The frame synchronization circuit according to claim 1, wherein: 4. The frame synchronization circuit according to claim 1, wherein a pulse width of the aperture signal is larger than a frequency variation width of a clock signal generated by the PLL processing. The retiming means generates data by triggering the first frame pulse with a clock signal that has generated the second frame pulse, and generates the third frame pulse by triggering the generated data with a second frame pulse. 5. The frame synchronization circuit according to claim 1, wherein retiming is performed.

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