JPH0983504A - Frame synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frame synchronizing circuit where out of synchronization due to frequency fluctuation caused by a temperature change and the like is eliminated, synchronism establishment at the time of power supply can considerably be speeded up and a synchronism protection circuit can be miniaturized. SOLUTION: A means 100 for generating one pulse FP 3 synchronized with the frame timing of two systems, a means 6 for selecting either a frame timing pulse FP or FP 3, a means 7 for generating FP at the one period internal of the selected pulse, a coincidence/non-coincidence judgment means 8 of FP 3 or FP and a means 9 for outputting a synchronous state signal at the continuity of coincidence and a step-out state signal at the continuity of non-coincidence are provided. A means 1 for generating the aperture signal synchronized with FP and a second synchronism protection means 10 outputting a synchronous result to the means 9 when FP 3 is not stored in the aperture signal and a step-out result when it is not stored are provided in constitution for selecting FP 3 in the synchronous state and FP in the step-out state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit. When generating a frame signal, this frame synchronization circuit generates a frame timing pulse for determining the frame signal interval by synchronizing frame timing pulses of two systems having different frequencies.

For example, in digital mobile communication, the present invention is applied to a circuit for synchronizing two systems of frame timing pulses generated by using output clocks having different frequencies of two systems of PLL circuits.

[0003]

2. Description of the Related Art FIG. 8 shows a block diagram of a conventional frame synchronization circuit, which will be described. The frame synchronization circuit shown in FIG. 8 generates one frame timing pulse FP synchronized with the two systems of the first and second frame timing pulses FP1 and FP2. It is configured to include units 3 and 4, a retiming circuit 5, a selector unit 6, a frame counter unit 7, a synchronization monitoring circuit 8, and a synchronization protection circuit 9.

The PLL circuits 1 and 2 generate different clock signals CK2 and CK3 having different frequencies from the same phase synchronization clock signal CK1. The frame timing generators 3 and 4 use the clock signals CK2 and CK3 to generate first and second frame timing pulses F having different periods.
P1 and FP2 are generated.

The retiming circuit 5 establishes synchronization by adjusting the pulse widths and periods of the frame timing pulses FP1 and FP2 of the two systems, and the third frame timing pulse FP3 synchronized with the frame timing pulses FP1 and FP2 of the two systems. To generate.

This third frame timing pulse FP3
Are supplied to the selector unit 6 and the synchronization monitoring circuit 8 shown in FIG. Initially, the third frame timing pulse F
P3 is connected to the frame counter unit 7 via the selector unit 6.
Is input to The frame counter section 7 generates the frame timing pulse FP at a cycle of one frame of the frame timing pulse FP3.

The generated frame timing pulse FP is output as the desired frame timing pulse FP and is also supplied to the synchronization monitoring circuit 8. The synchronization monitoring circuit 8 monitors the pulse positions of the frame timing pulses FP3 and FP, and outputs “H” pulse to the synchronization protection circuit 9 when they match and “L” pulse when they do not match.

The synchronization protection circuit 9 judges that the state is the synchronization state (backward protection) when "H" is input N times consecutively, and "H"
Of the sync state signal H1 of "L" is output to the selector section 6, and when "L" is continuously input M times, it is judged to be out of sync (forward protection), and the sync state signal H1 of "L" is selected. Output to.

When the synchronization state signal H1 is "H" indicating the synchronization state, the selector section 6 selects the third frame timing pulse FP3 and outputs it to the frame counter section 7 to indicate the out-of-synchronization state "L". In this case, the frame timing pulse FP is selected and output to the frame counter section 7.

That is, the frame counter section 7 outputs a pulse synchronized with the third frame timing pulse FP3 as the frame timing pulse FP in the synchronous state, and synchronizes with the previously output frame timing pulse FP in the out of synchronization state. Frame timing pulse F
Outputs P.

[0011]

By the way, in the above-mentioned conventional frame synchronization circuit with forward protection and backward protection, there are two systems of frame timing pulses FP1,
Since the FP2 is generated by the different PLL circuits 1 and 2, the frame timing pulses FP1 and F of two systems are generated due to the frequency fluctuations of the PLL circuits 1 and 2 when the power is turned on.
The phase of P2 may vary, and even if synchronization is once established, the state may become out of synchronization again, and it takes a long time to completely establish synchronization, and a large number of backward protection stages must be taken. Therefore, the synchronization protection circuit 9 There was a problem that the circuit scale of became large.

Further, the output frequencies of the PLL circuits 1 and 2 are changed due to the temperature change during operation, and the PLL circuits 1 and 2 are changed.
The pulse positions of the two systems of frame timing pulses FP1 and FP2 generated from the output frequency of the above also fluctuate, and the output position of the third frame timing pulse FP3 after retiming by the retiming circuit 5 also fluctuates, resulting in synchronization. There was a problem of getting out.

Further, in the case of frequency fluctuations that occur under such temperature conditions, although it is originally preferable to maintain the synchronization state as it is, there is a problem that the synchronization state and the out-of-synchronization state are repeated. .

The present invention has been made in view of the above points, and it is possible to eliminate loss of synchronism due to frequency fluctuations caused by temperature changes, etc., and to speed up the establishment of synchronization when the power is turned on. It is an object of the present invention to provide a frame synchronization circuit which can be made compact and can further reduce the size of the synchronization protection circuit.

[0015]

FIG. 1 shows a principle diagram of a frame synchronization circuit according to the present invention. This frame synchronization circuit has 2
After generating first and second frame pulses for frame synchronization from clock signals having different frequencies generated by the PLL processing of the system, one third frame pulse FP3 synchronized with the first and second frame pulses , A selector means 6 for selecting any one of the third frame pulse FP3 and the frame timing pulse FP obtained at the final stage according to the synchronization state signal, and the pulse selected by the selector means 6. Frame counter means 7 for generating the frame timing pulse FP at intervals of 1 cycle, the synchronization monitoring means 8 for determining whether the third frame pulse FP3 matches the frame timing pulse FP, and the determination result of the synchronization monitoring means 8. If a predetermined number of consecutive matches occur, a sync status signal indicating the sync status is output and A first synchronization protection means 9 for performing synchronization protection for outputting the synchronization status signal indicating an out-of-synchronization status when a predetermined number of consecutive times have occurred, and the third frame when the selector means 6 indicates the synchronization status. The pulse FP3 is selected, and the frame timing pulse FP is selected when the out-of-synchronization state is indicated. The feature of the present invention is that the aperture generation means generates an aperture signal having a predetermined pulse width synchronized with the frame timing pulse FP. 11 and
If the third frame pulse FP3 is included in the aperture signal, it is determined to be in the synchronization state, and if it is not included, it is determined to be out of synchronization, and the determination result is output to the first synchronization protection means 9, and the synchronization state signal is in the synchronization state. The second synchronization protection means 10 starts the previous processing when the above-mentioned is indicated, and stops the above-mentioned processing when the out-of-synchronization state is indicated.

[0016]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a frame synchronization circuit according to an exemplary embodiment of the present invention. In this figure, parts corresponding to those of the conventional example shown in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 2, 10 is a synchronization protection circuit, and 11
Is an aperture generation unit. Further, in this embodiment, the retiming circuit 5 is configured to include flip-flops (FF) 31, 32, 33, 34 and AND circuits 35, 36 as shown in FIG.

The operation of the retiming circuit 5 shown in FIG.
This will be described with reference to FIG. The first frame timing pulse FP1 is supplied to the FF 31 as data, and this supplied data is triggered by the clock signal CK3 synchronized with the second frame timing pulse FP2.

The data held in the FF 31 by this trigger is output from the inverting output terminal XQ and supplied to the FF 32, and the supplied data is held by being triggered by the clock signal CK3. The AND circuit 35 ANDs the data from XQ of the FF 32 and the data from XQ of the FF 31 to output the data D1 shown in FIG.

The "H" level portion of this data D1 has the same period as the first frame timing pulse FP1 and the same pulse width as the second frame timing pulse FP2.

The data D1 is the clock terminal CLK of the FF33.
FF33, the FF 33 holds and outputs "H" data at the rising edge of the data D1. The output data D2 is supplied to the AND circuit 36.

On the other hand, the second frame timing pulse FP
2 is supplied to the AND circuit 36, and the AND of the data D2 and the "H" portion is taken, so that the pulse has the same period as the first frame timing pulse FP1 and the same phase as the second frame timing pulse FP2. Is the third
The frame timing pulse FP3 is generated.

The aperture generation section 11 shown in FIG. 2 detects the pulse portion of the frame timing pulse FP output from the frame counter section 7, and takes a width of a predetermined time before and after this detected pulse portion to obtain "H". The aperture signal A1 forming the level portion is generated.

The sync protection circuit 10 has an aperture signal A1.
If the second frame timing pulse FP3 is included in the "H" part of the above, it is determined that the synchronization state is reached. When the synchronization state signal H1 is "L" indicating out of synchronization, it does not operate,
It operates when "H".

Further, the result of the logical sum of the output signal indicating the synchronization state of the synchronization protection circuit 10 and the output signal of the synchronization monitoring circuit 8 is input to the synchronization protection circuit 9 via the OR circuit 13. .

In such a configuration, for example, when the frame synchronization circuit is in a state immediately after power-on and is out of synchronization, the synchronization state signal H1 becomes "L" so that the synchronization protection circuit 10 does not operate and the frame is not activated. The synchronization protection is performed by the synchronization protection circuit 9.

Here, the synchronization state of N times is the synchronization protection circuit 9.
When detected by, the synchronization status signal H1 becomes "H" and the synchronization protection circuit 10 operates. On the other hand, when the frame timing pulse FP supplied from the frame counter unit 7 is input to the aperture generation unit 11, the aperture of the specific width is opened by the aperture signal A1 and it is input to the synchronization protection circuit 10.

The sync protection circuit 10 monitors whether or not the frame timing pulse FP3 is detected within the aperture, and when detected, outputs a "H" pulse to the sync protection circuit 9 via the OR circuit 13.

In this case, the output signal of the synchronization monitoring circuit 8 is ignored, and the synchronization protection circuit 9 outputs the synchronization state signal H1 of "H" as long as the input signal is "H". Then, the forward synchronization protection is switched to the synchronization protection circuit 10, and the aperture protection front protection is performed in the synchronization protection circuit 10.

Here, the frame timing pulse FP3
Is not detected in the aperture, the sync protection circuit 10 outputs an "L" pulse. In this case, the pulse output from the synchronization monitoring circuit 8 becomes valid, and the synchronization protection is switched to the synchronization protection circuit 9 again.

Therefore, when the phase of the frame timing pulses FP1 and FP2 of the two systems changes due to the output frequency fluctuations of the PLL circuits 1 and 2 when the power is turned on, the phase of the frame timing pulse FP3 after retiming also changes.
The synchronization protection circuit 9 existing from the conventional example repeats the sync / out-of-sync state until the PLL circuits 1 and 2 become stable, but the synchronization protection circuit 10 added in the present embodiment allows
Once the synchronization is established by the synchronization protection circuit 9, it can be considered that the variation of the frame timing pulse FP3 within the aperture is synchronized, and as a result, the synchronization establishment time from the power-on can be shortened.

Even if the frame timing phase changes due to the temperature change during operation, it can be considered that the frame timing pulse FP3 is in synchronization as long as it is detected in the aperture, so unnecessary synchronization loss can be avoided. I can do things.

The aperture generator 11 shown in FIG. 2 can be constructed by using a ROM as shown by reference numeral 40 in FIG. 5, for example. Further, the synchronization monitoring circuit 8 and the synchronization protection circuit 9
And 10 can have the circuit configuration shown in FIG. 6, for example. That is, as shown in FIG. 6, the synchronization monitoring circuit 8 uses the AND circuit 43, the synchronization protection circuit 10 uses the FF 45, and the synchronization protection circuit 9 uses the F-type shift register configuration of n stages.
F47, 48, 49 and NAND circuits 50, 51, 52,
And 53.

This operation will be described with reference to the timing chart of FIG. The third frame timing pulse FP3 shown in FIG. 2 is input to the frame counter unit 7, and the frame counter unit 7 generates a frame timing pulse FP having the same period as the frame timing pulse FP3.

The AND circuit 4 which is the synchronization monitoring circuit 8
3 takes the logical product of the pulses FP3 and FP, outputs this as data D3, and inputs it to the OR circuit 13. The other input of the OR circuit 13 is an FF which is the synchronization protection circuit 10.
Although the signal from the signal 45 is input, it is a case where the synchronization is not established now, that is, the synchronization state signal H1 output from the NAND circuit 52 is "L", and the signal from the FF 45 is "L".
Since the signal of (3) is output, the data D3 is directly input to the FF 47 of the synchronization protection circuit 9.

Here, each FF 47-49 and NAND circuit 5
0 and 51 provide N-stage rear protection and M-stage front protection, and the results are input to NAND circuits 52 and 53.
Here, the operation of the NAND circuits 52 and 53 outputs the synchronization state signal H1 of "H" level when the backward protection conditions of the N stages are satisfied and "L" level when the forward protection conditions of the M stages are satisfied.

When the synchronization status signal H1 becomes "H", FF
The reset (RESET) of 45 is released. On the other hand, the aperture signal A1 is input to the ROM 40 shown in FIG. 5 by using the output data of the frame counter section 7 as an address, and a specific "H" level is specified at a position where the frame timing pulse FP3 as shown in FIG. Increase the width of the aperture.

Then, in the FF 45, this aperture is triggered by the frame timing pulse FP3, and this output data is input to the OR circuit 13. That is, "H" is output while the frame timing pulse FP3 is within the aperture, and "L" is output when the frame timing pulse FP3 is out of the aperture.

When the output of the FF 45 is always "H", the output of the OR circuit 13 is "H". Therefore, even if the output of the AND circuit 43, that is, the positions of the frame pulses FP3 and FP do not match, If the variation of FP3 is within the aperture, it can be determined that the FP3 is in the synchronization state.

By setting the width of this aperture to a width that can withstand the frequency fluctuations during the operation of the PLL, it is possible to avoid the loss of synchronization due to the frequency fluctuations of the PLL.

[0041]

As described above, according to the frame synchronization circuit of the present invention, loss of synchronization due to frequency fluctuations caused by temperature changes and the like can be eliminated, and synchronization establishment at power-on can be made as fast as possible. It is also possible to reduce the size of the synchronization protection circuit.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a frame synchronization circuit according to an exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a retiming circuit.

FIG. 4 is a timing chart for explaining the operation of the retiming circuit shown in FIG.

5 is a configuration diagram when a ROM is used in the aperture generation unit shown in FIG.

FIG. 6 is a specific circuit diagram of the main part shown in FIG.

FIG. 7 is a timing chart for explaining the operation of FIGS. 5 and 6;

FIG. 8 is a block diagram of a conventional frame synchronization circuit.

[Explanation of symbols]

 6 selector means 7 frame counter means 8 synchronization monitoring means 9 first synchronization protection means 10 second synchronization protection means 11 aperture generation means 100 retiming means FP3 third frame pulse FP frame timing pulse

Claims (5)

[Claims] 1. A first and a second frame pulse for frame synchronization are generated from clock signals having different frequencies generated by two-system PLL processing, and then synchronized with the first and second frame pulses. The retiming means for generating one third frame pulse, the selector means for selecting any one of the third frame pulse and the frame timing pulse obtained at the final stage according to the synchronization state signal, and the selector means. The frame counter means for generating the frame timing pulse at one cycle interval of the selected pulse, the synchronization monitoring means for determining the match / mismatch between the third frame pulse and the frame timing pulse, and the synchronization monitoring means When the number of coincidences, which is the determination result, continues for a predetermined number of times, the synchronization state signal indicating the synchronization state is output,
A first synchronization protection means for performing synchronization protection for outputting the synchronization status signal indicating an out-of-sync state when a predetermined number of disagreements occur, and the selector means operates when the synchronization status signal indicates a synchronization status. In a frame synchronization circuit that selects the third frame pulse and selects the frame timing pulse when an out-of-synchronization state is indicated, an aperture generation unit that generates an aperture signal having a predetermined pulse width synchronized with the frame timing pulse; If the third frame pulse is included in the aperture signal, it is determined to be in the synchronization state, and if it is not included, it is determined to be the out-of-synchronization state, and the determination result is output to the first synchronization protection means. Second synchronization protection means for starting the processing when the synchronization state is shown and stopping the processing when the synchronization state is shown. Frame synchronization circuit characterized in that the. 2. The first synchronization protection means, when the second synchronization protection means is performing the processing, performs the synchronization protection using the determination result of the second synchronization protection means, and executes the processing. 2. The frame synchronization circuit according to claim 1, wherein the synchronization protection is performed by using the determination result of the synchronization monitoring means when not performing. 3. The first synchronization protection means, when initially detecting the synchronization state from the determination result of the synchronization monitoring means, uses the determination result of the second synchronization protection means to perform the synchronization protection. The method according to claim 1 or 2, wherein
The frame synchronization circuit described. 4. The pulse width of the aperture signal is set to the P
4. The frame synchronization circuit according to claim 1, wherein the width is larger than the frequency fluctuation width of the clock signal generated by the LL process. 5. The retiming means triggers the first frame pulse with a clock signal that has generated the second frame pulse to generate data, and triggers the generated data with a second frame pulse to generate the data. The frame synchronization circuit according to claim 1, wherein retiming for generating three frame pulses is performed.