JPH02190944A - Reset system for processor - Google Patents

Abstract

PURPOSE:To collectly reset a processor by allowing a processor to generate a frame pattern with the same period as that of a program or a longer period and comparing the frame pattern with a reference frame pattern in each bit to decide coincidence/discrepancy. CONSTITUTION:The reset system is provided with the processor 1 for outputting a prescribed frame pattern with the same period as that of the program or a longer period, a frame synchronizing circuit 2 for comparing a reference frame pattern included in itself with the frame pattern outputted from the processor in each bit and each period and outputting the compared result and a reset signal generating part 3 for applying a reset signal to the processor 1 when the compared result indicates discrepancy. Thereby, all pulse patterns have meaning and only one pattern out of various pulses is decided as a normal one. Consequently, the processor 1 can be correctly reset independently of the state of a runaway pulse pattern and the runaway can be evaded.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for resetting a processor to prevent a program from running out of control, the processor is reset to avoid runaway regardless of the runaway pulse pattern generated by the processor. The purpose is to realize a system in which the processor generates a predetermined frame pattern at a cycle equal to or longer than the program cycle, and a reference frame pattern, and the reference frame pattern is converted into a frame pattern from the processor. - a frame synchronization circuit that compares bits with each cycle and outputs the comparison result, and a reset signal generator that provides a reset signal to the processor when the comparison result indicates a mismatch.

[Industrial application field]

The present invention relates to a method for resetting a processor, and more particularly to a method for resetting a processor to prevent a program from running out of control.

In recent years, line termination equipment installed in homes has come to be equipped with microprocessors, and processors are extremely useful. ), but the firmware may run out of control when turning on the power or inserting a board when adding a boat, and in such cases, the processor
Must be automatically detected and reset by hardware or manually reset.

In particular, since the in-home line termination device is installed in a general building and maintenance and monitoring personnel are not available, measures must be taken to prevent program runaway during operation.

[Conventional technology]

As a conventional processor reset method, the one shown in FIG. 6 is used. In this method, the processor 1 is reset by a timer circuit 50 and a reset path generation section 60, as shown in FIG. During normal operation, a watchdog timer (WDT) pulse shorter than the timer period of the timer circuit 50 is always generated by the processor 1 and given to the timer circuit 50, and when this WDT pulse is received, the timer circuit 50 is reset. Counting is started again, and when the processor 1 goes out of control and the WDT pulse is no longer generated, the timer circuit 50 counts up, so it is determined that there is a runaway, and the reset pulse generator 60 sends a reset pulse to the processor 1.

An example of such a conventional example is the one disclosed in Japanese Patent Laid-Open No. 62-31452.

[Problem to be solved by the invention]

In the processor reset method described above,
There are several patterns for the WDT pulse when it goes out of control, as shown in Figure 7. There is no particular problem in the case of pattern ■, but when patterns ■ to ■ occur, the timer circuit 50 is reset. There was a problem in that it was impossible to stop the processor 1 from running out of control.

Therefore, it is an object of the present invention to realize a system that resets the processor and avoids runaway, regardless of the runaway pulse pattern generated by the processor.

[Means to solve the problem]

FIG. 1 shows the principle of a processor reset method according to the present invention to achieve the above object. a frame synchronization circuit 2 which has a reference frame pattern and compares bits of the reference frame pattern with the frame pattern from the processor I at each cycle and outputs the comparison result; A reset signal generating section 3 is provided which provides a reset signal to the processor 1 when a mismatch is indicated.

Further, in the present invention, a synchronization protection circuit 4 is provided between the frame synchronization circuit 2 and the reset signal generation section 3, which generates a runaway detection signal when the number of discrepancies resulting from the comparison exceeds a predetermined number of protection stages. Can be done.

Furthermore, in the present invention, the frame synchronization circuit 2 can be configured to input the runaway detection signal and synchronize the reference frame pattern with the frame pattern from the reset processor 1.

[For production]

In the present invention, the processor 1 uses software to generate a frame pattern with a cycle equal to or longer than the program cycle (this is because runaway cannot be detected if it is shorter than the program cycle), and this frame pattern is The frame synchronization circuit 2 generates a reference frame pattern and compares the two frame patterns for each bit for coincidence/mismatch. Then, this comparison result is outputted at each of the above-mentioned cycles. In the reset signal generator 3, the comparison result is 1.
If even the bits do not match, a reset signal is generated to reset the processor 1.

Therefore, as shown briefly in FIG. 2, in the conventional example, it was meaningful that a predetermined pulse existed during the program cycle (see FIG. 2(a)), but in the present invention, all of the pulse patterns becomes meaningful (see Figure 2),
Since only one pattern is determined to be normal for a variety of pulses, runaway conditions can be detected accurately.

Further, in the present invention, by providing a synchronization protection circuit 4 having a predetermined number of protection stages between the frame synchronization circuit 2 and the reset signal generation section 3, the number of discrepancies in the comparison results in the frame synchronization circuit 2 can be reduced. A runaway detection signal can be generated when the number of protection stages is exceeded, and it is possible to prevent the processor 1 from being erroneously reset due to noise.

Furthermore, in the present invention, the frame synchronization circuit 2 can synchronize the reference frame pattern with the frame pattern from the reset processor 1 by the runaway detection signal, so that the processor 1 that has been reset and becomes normal can also synchronize the reference frame pattern with the frame pattern from the reset processor 1. The frame pattern of processor 1 and the reference frame pattern can be synchronized, and then the frame pattern of processor 1 can be synchronized with the reference frame pattern.
It becomes possible to accurately reset when a runaway occurs.

〔Example〕

FIG. 3 shows an embodiment of the frame synchronization circuit 2 and the synchronization protection circuit 4 used in the processor reset method according to the present invention.
2 is a ripple carry (hereinafter referred to as RC) of the reference frame pulse pattern (hereinafter referred to as frame pattern).
A heptadary counter 21 that outputs in the form of a signal, an EOR gate 22 that detects a mismatch between this RC signal and the frame pulse from the processor 1; Flip-flop (hereinafter referred to as FF) 23, FFs 25 and 26 for shifting the RC signal of the counter 21 by half the focus by a clock input CK obtained by inverting the clock CLK by the inverter 24, and inverting and clearing the output of the FF 23. Input to terminal CLR, 0 human power is fixed to +5v H'',
FF27 with the clock input CK as the ζ output of FF25, and A with the ζ output of FF26 and the ζ output of FF27 as inputs.
ND gate 2, a NAND gate 29 which inputs the output of this AND gate 28 and the judgment signal from the synchronization protection circuit 4, and the output of this NAND gate 29 and the clock CL.
It is composed of an AND gate 30 that manually operates K and K.

The synchronization protection circuit 4 also includes a shift register 31 with three forward protection stages and three rear protection stages, which receives the ζ output of the FF 27 and uses the ζ output of the FF 25 as a clock CK, and stores the comparison results of the frame synchronization circuit 2. Q of shift register 31
The NAND gate 32 which receives the outputs from Q1 to Q3 as input, and the shift register 31? :NA with L1 to σ3 output manually
ND gate 33 and these NAND gates 32 and 3
3) and a launch circuit 34 which holds the output state of 7) and outputs the runaway detection signal to the signal generator 3.

Next, the operation of the above embodiment will be explained with reference to the time charts of FIGS. 4 and 5.

FIG. 4 shows a time chart when the frame pattern from processor I is normal, that is, when this frame pattern is synchronized with the reference frame pattern generated as an RC signal from counter 21 of frame synchronization circuit 2. In this case, the output of the EOR 22 is always at the "L" level, so the ζ output of the FF 23 is at the "H" level, and the ζ output of the FF 27 is at the "L" level.

In addition, an FF that shifts the RC signal of the counter 21 by half a bit
In the shift register 31 in which the ζ output of FF 25 is used as the clock CK and the output of the FF 27 is 0 manual output, the Q1 to Q3 outputs are at the 'L' level and the 'C11 to ζ3 outputs are at the 'H' level, so the AND gate 32. The outputs of 33 are at H" and "L" levels, respectively. Therefore, the latch circuit 34
The output of the reset signal generating section 3 also becomes "L" level, and runaway detection is not performed, so that the reset signal generating section 3 does not generate a reset signal.

When the output of the latch circuit 34 is at "L" level, AND
No matter what the output of gate 28 is, the output of NAND gate 29 will be at the 1H'' level, passing clock CLK from AND gate 30 to counter 21, which causes counter 21 to operate as a heptad counter, and clock CLK
When seven K's are input, an "H" level pulse, ie, an RC signal, is output as shown in the figure.

Therefore, under normal conditions, this RC signal matches the frame pattern from processor 1, and the same operation as described above is repeated.

FIG. 5 shows a synchronization pull-in (hunting) time chart when the frame patterns are not synchronized (when the RC signal of the counter 21 is shifted by 1 bit in front of the frame pattern). is counted up by the clock CLK and generates an RC signal, the EOR gate 22 generates a mismatch output, and when this is input to the FF 23 by the clock CLK, the ζ output of the FF 23 becomes a 1L'' level signal only during the mismatch period, and this The output of the FF27 received at the clear terminal CLR rises and remains at the "H" level until the Q output of the FF25 rises.In other words, if even one bit of mismatch is detected during one cycle of the reference frame pattern, this Like-
It is at "H" level during the cycle.

Therefore, the ζ output of the second FF27 is set to the reset signal generator 3.
If the reset signal is sent to the processor 1, the runaway of the processor 1 can be reset.

However, even when a mismatch between both frame patterns is detected due to noise in the EOR gate 22 or the like, there is a risk that the processor 1 will be reset.In order to eliminate this, the present invention provides a synchronization protection circuit having a predetermined number of protection stages. There are 3.

That is, the shift register 31 is at "H" level 0FF2
After receiving the output, it is shifted every round according to the rising edge of the Q output of the FF 25.

In this case, the shift register 31 has forward and forward protection stages.
Since both the rear and rear stages have three stages, only when a pattern mismatch is detected by the EOR gate 22 for three consecutive periods,
Outputs Ql-Q3 are both at 'H' level ('C11 to 'c1
The outputs of the NAND gate 32 both become "L" level), and the output of the NAND gate 32 becomes the "L" level (the output of the NAND gate 33 becomes the "H" level), thereby inverting the output of the latch circuit 34.

Furthermore, when the output of the latch circuit 34 is inverted, the output of the NAND gate 32 remains at "H" level until a pattern match (complete failure) is detected by the EOR gate 23 for three consecutive cycles. This state is maintained until the output of the gate 33 becomes "L" level.

That is, the output of the latch 34 is connected to the NAND gate 32 or 3.
It changes only when the output of No. 3 becomes "L" level.

Now, if pattern mismatch is detected for three consecutive cycles, the output of the latch circuit 34 is "H" as shown in FIG.
level and generates a runaway detection signal, which is sent to the reset signal generator 4. This causes processor 1 to be reset.

If this continues, even if the processor 1 is reset, the normal frame pattern and the reference frame pattern of the frame synchronization circuit 2 will remain out of synchronization.

In order to prevent this, the present invention further uses the runaway detection signal to synchronize the phase of the RC signal (reference frame pattern) of the counter 21 with the frame pattern from the processor l.

That is, due to the runaway detection signal being generated, the NAND
One input of the gate 29 is at the #H'' level, but the other input is at the 1Hm level due to the bit shift of the RC signal of the counter 21, so the other input is NAND.
The output of the gate 29 becomes L” level only during that period, and the AN
The D gate 30 masks and removes one clock CLK.

As a result, the counting operation of the counter 21 is performed using the clock CL.
K1 will not be performed, and the count will increase to 7.
The 8th count bit is originally the 8th count focus, and the RC signal is delayed by this 1 bit so that it matches the I) level of the frame pattern as shown in the figure. Become.

In this way, when a pattern mismatch is detected for three consecutive cycles, a runaway detection signal is generated and the counter 2
1 is stopped by one step, and the synchronization pull-in is performed by chasing the frame pattern so that it matches the pattern of the RC signal as the reference frame pattern.

This masking operation of the clock CK of the counter 21 is performed until both frame patterns match for three consecutive cycles, so that synchronization can be carried out without fail.

As a result, both frame patterns become synchronized as shown in FIG. 4, and if a runaway occurs in the processor 1 thereafter, the runaway can be accurately detected including the number of protection stages described above.

〔Effect of the invention〕

As described above, according to the processor reset method of the present invention, the frame pattern generated by the processor is compared with the reference frame pattern of the frame synchronization circuit for bit-by-bit coincidence/inconsistency at each program cycle. Since the configuration is configured so that if even one bit does not match, a reset signal is generated to reset the processor l, all pulse patterns are meaningful, and only one pattern is determined to be normal even for a variety of pulses. , programs can be accurately monitored, and the processor can be safely installed even in data transmission equipment in the subscriber's premises, especially when there are no maintenance personnel.

Furthermore, in the present invention, by providing a synchronization protection circuit having a predetermined number of protection stages, it is possible to generate a runaway detection signal when the number of discrepancies resulting from the comparison results in the frame synchronization circuit exceeds the number of protection stages, thereby generating noise. This prevents the processor from being reset accidentally.

Furthermore, in the present invention, when a runaway is detected, the reference frame pattern can be synchronized with the frame pattern from the reset processor, so the frame pattern of the processor that has been reset and becomes normal can be synchronized with the reference frame pattern. This makes it possible to accurately reset the processor the next time it goes out of control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the processor reset method according to the present invention, FIG. 2 is a time chart diagram conceptually explaining the processor reset method according to the present invention, and FIG. A circuit diagram showing an embodiment of a frame synchronization circuit and a synchronization protection circuit used in the processor reset method according to the invention; FIGS. 4 and 5 are operation time charts when the embodiment of FIG. 3 is used; FIG. 6 is a block diagram showing a conventional processor reset method, and FIG. 7 is a pulse waveform diagram showing a runaway pattern. In FIG. 1, ■...Processor 2...Frame synchronization circuit, 3...Synchronization protection circuit, 4...Reset signal generation section. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A processor (1) that generates a predetermined frame pattern at a cycle equal to or longer than the cycle of the program, and a reference frame pattern, and the processor (1) has a reference frame pattern that is matched with the frame pattern from the processor (1). a frame synchronization circuit (2) that compares bits every cycle and outputs the comparison results; and when the comparison results indicate a mismatch, the processor (2);
Reset signal generator (3) that provides a reset signal to 1)
A processor reset method characterized by comprising: and. (2) A synchronization protection circuit (4) that generates a runaway detection signal when the number of discrepancies resulting from the comparison exceeds a predetermined number of protection stages.
The frame synchronization circuit (2) and the reset signal generator (
3) The processor reset method according to claim 1, wherein the processor reset method is provided between 3) and 3). (3) The frame synchronization circuit (2) receives the runaway detection signal and synchronizes the reference frame pattern with the reset frame pattern from the processor (1). Processor reset method.