JPH07250054A - Bit synchronizing circuit/method for serial communication - Google Patents

Abstract

PURPOSE:To provide a bit synchronizing circuit which can surely settle the synchronization without being affected by noises by detecting whether the width of the bit pulse of preamble of the reception data is kept within the allowable pulse width set by adding a prescribed allowable error to the pulse width that is prescribed by the transfer speed of the reception data. CONSTITUTION:The settlement of synchronization is decided and a synchronization settlement signal is outputted to a clock pulse generating part CPG when the coincidence pulses sent from the pulse width detecting parts 1 and 2 are continuously counted in the prescribed frequency by a synchronization settling part SYN while the preamble of the reception data is received. The part CPG generates a reception clock pulse in the center timing of the bit pulse of a data frame of the reception data. Therefore the coincidence pulses are not continuously outputted from the parts 1 and 2 in the prescribed frequency if the reception data include the noises. Then a non-coincidence pulse signal is outputted halfway so that the influence of noises can be evaded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit and a bit synchronization method for serial communication for detecting a synchronization timing with reception data by serial communication and generating a reception synchronization signal.

[0002]

2. Description of the Related Art Conventionally, in a serial communication system for extracting a synchronization signal from a transmission data signal waveform without using a special synchronization clock line, the transmission lines are connected in a bus type, and a node on the transmission side is replaced when necessary. However, when performing burst transmission (CSMA / CD, token bus, etc.) in which transmission data is transmitted in chunks, each node operates with its own clock, so the clock accuracy is a fixed cycle of burst transmission data length. Even if the sampling is performed at a high level so that there is no problem, each node on the receiving side needs to re-acquire bit synchronization, especially bit phase synchronization, every time the transmitting side node changes.

In order to perform bit synchronization in this way,
As described in JP-A-4-259137, PWM
And the edge of the transmission data by the encoding method that superimposes the synchronous clock signal component such as Manchester method,
A bit synchronization method for generating a reception clock signal based on an edge detection signal has been proposed, but in this case, there is a problem that it is easily affected by noise.

Further, as described in JP-A-4-264837, the phase difference between the input signal and the reproduction clock is obtained by the phase difference detecting means, and the phase shift amount corresponding to the obtained phase difference is set in the setting means. It is considered that bit synchronization that is strong against noise is performed by changing the phase of the reproduction clock by the synchronizing means by the set phase shift amount or by using a PLL. A microcomputer equipped with a CPU, a timer, a counter, etc. is required as a means for changing the phase of the reproduced clock, and these microcomputers and PLL circuits complicate the overall structure of the device, increase the size, and increase the cost. Therefore, it is not suitable for integration into logic circuits.

In the field of optical communication, for example, an AC coupling circuit is provided at the input stage of the receiving section in order to realize high-speed transmission, long-distance transmission, and high-sensitivity transmission.
This AC coupling circuit is generally characterized in that the output is delayed at the beginning of signal input and that it takes a long time for the output to stabilize. When burst transmission is executed in such a system, burst reception data The first waveform is not received correctly and cannot be reproduced exactly.

Therefore, as previously proposed by the applicant of the present application, for example, "01" is added to the beginning of the burst data packet.
It is conceivable that a preamble of a bit pattern that does not include transmission information such as "01 ..." Is added and the AC coupling circuit is stabilized during the transmission of this preamble to enable reliable data transmission (Japanese Patent Laid-Open No. Hei. Such a preamble can also be used for establishing the bit synchronization described above.

For example, as described in JP-A-4-40126, a synchronization establishment clock is generated by detecting a synchronization flag in data to be transmitted, and a check bit added to the data to be transmitted is used as a basis. According to the result of data error detection performed in the above, it is considered to select the clock of the phase that can capture the data without error from the multiple clocks with the phase relationship shifted in multiple stages to establish the synchronization. There is a width in the clock phase that can take in the clock pulse, and the clock pulse is not always located at the center of the received waveform, and there is a problem in terms of reliability.

On the other hand, Japanese Patent Publication No. 56-1825 discloses that
Counts the number of bits with a polarity of "1" or "0" in the preamble provided prior to the information data for transmission, and synchronizes when the count value reaches a predetermined value within a predetermined time by the timer. Although it is considered to judge that it has been established, it still lacks certainty.

In addition, as described in Japanese Patent Laid-Open No. 1-265740, a bit synchronization signal added before transmission data is sampled at a rate several times as high as the bit rate to change the sign of the bit synchronization signal. Is detected, the average value of jitter, which is the difference between the number of sampling times included between the code change points and a predetermined number representing the bit rate of the bit synchronization signal, is detected, and the sample start point is set using this average value. It is also considered that the sampling period of the sampling timer is set to be equal to or almost equal to the bit rate of transmission data and sampling is performed at the center of the data signal, but the selection criterion is the pulse waveform to be averaged for jitter. Since there is no waveform, even if the waveform is greatly distorted, it may be averaged, and the sampling cycle may shift from the center of the data signal. .

[0010]

As described above, the conventional bit period establishing means cannot accurately synchronize due to noise and requires a microcomputer, a PLL circuit, etc., which complicates and enlarges the structure. Causes an increase in cost, and the synchronization clock is not always located at the center of the bit of the data waveform, and there is a problem that reliability is low.

Therefore, the present invention has been made in order to solve the above-mentioned problems, and makes it possible to provide a bit synchronizing circuit which is not easily affected by noise, has a simple structure, and can reliably establish synchronization. The purpose is to

[0012]

The invention according to claim 1 is
In a bit synchronization circuit of serial communication, which detects a synchronization timing with reception data by serial communication in which a predetermined preamble is provided at the beginning of a data packet and generates a reception clock pulse, a pulse of the preamble bit pulse of the reception data Detects whether or not the width is within the allowable pulse width obtained by adding a predetermined allowable error to the pulse width specified by the transmission rate of the received data. Matches when the pulse signal is input, and disagrees when it is not. A pulse width detection unit that outputs a pulse signal and a synchronization establishment that outputs the synchronization establishment signal when the coincidence pulse signal is reset by the input of the non-coincidence pulse signal and the coincidence pulse signal is continuously counted a predetermined number of times And a bit pulse of the data frame of the received data by the synchronization establishment signal. It is characterized in at the center of the timing that a clock pulse generator for generating a receive clock pulse.

As a synchronizing method, as described in claim 2, whether or not the pulse width of the bit pulse of the preamble of the received data is within an allowable pulse width defined by the transmission rate of the received data. Of the data frame of the received data by the clock pulse generator after the synchronization is established, when the pulse width of the bit pulse of the preamble is continuously detected within a predetermined number of times within the allowable pulse width. It is effective to output the reception clock pulse at the central timing of the bit pulse.

[0014]

According to the present invention, when the coincidence pulse signal from the pulse width detecting section is continuously counted a predetermined number of times by the synchronization establishing section, it is judged that the synchronization is established and the synchronization establishing signal is output to the clock pulse generating section. Then, the clock pulse generation unit generates the reception clock pulse at the center timing of the bit pulse of the data frame of the reception data.

At this time, if the received data contains noise, the pulse width detection section does not continuously output the coincidence pulse signal a predetermined number of times, but the non-coincidence pulse signal is output in the middle of the coincidence pulse signal. It will not be affected.

Further, since the conventional microcomputer and PLL circuit are not required, the configuration can be simplified and downsized, the cost is reduced, and the synchronization is directly established by the preamble waveform after the stabilization of the received data. The certainty of establishment is high.

[0017]

1 is a block diagram of the present invention, FIG. 2 is an operation explanatory diagram of FIG. 1, FIG. 3 is a partial block diagram of FIG. 1, FIG. 4 is an operational explanatory diagram of FIG. 3, and FIG. Some other block diagrams of
6 is an operation explanatory view of FIG. 5, and FIG. 7 is an operation explanatory view of still another part of FIG.

As shown in FIG. 1, received data by serial communication in which a predetermined preamble is provided at the beginning of a data packet is input to the positive and negative pulse width detection units 1 and 2 via a data input terminal D. , It is detected whether or not the pulse width of the preamble bit pulse of the received data is within the allowable pulse width that is the pulse width specified by the transmission rate of the received data plus a predetermined allowable error. When no coincidence pulse signal is input, the non-coincidence pulse signal is output.

Both of the pulse width detection units 1 and 2 operate by the clock pulse from the clock input terminal C having a cycle sufficiently smaller than the allowable pulse width, and the pulse width detection units 1 and 2 respectively input the OR gate OR1. The coincidence pulse signal is output to the end, and the non-coincidence pulse signal is input to the input end of the OR gate OR2 from both the pulse width detection units 1 and 2.

The output of the OR gate OR1 is input to the clock terminal CK of the first counter 3, and the output of the OR gate OR2 is the reset terminal RST of the first counter 3.
, The first counter 3 is reset by the input to the reset terminal RST, counts the input pulses to the clock terminal CK, and when the count value reaches a predetermined number (for example, “5”), A counter pulse is output from the first counter 3 to the latch 4, and a synchronization establishment signal is output from the latch 4 to the enable terminal EN of the second counter 5 and at the same time to the disenable terminal DEN of the first counter 3. It

At this time, the first counter 3 and the latch 4
The synchronization establishing unit SYN is constituted by.

The first counter 3 stops its operation while a signal is input to the disenable terminal DEN,
The second counter 5 operates during the signal input to the enable terminal EN and repeats counting up the clock pulse to the clock terminal CK, and the output pattern of the second counter 5 is the bit pulse of the data frame of the received data. The collating unit 6 collates whether or not a predetermined pattern indicating the central timing is reached, and when the predetermined pattern is reached, the collating unit 6 outputs the reception clock pulse to the waveform synchronization circuit 7. The counter 5 and the collation unit 6 constitute a clock pulse generation unit CPG, and the waveform synchronization circuit 7 samples the data frame of the reception data based on the reception clock pulse.

When reception completion or an error in the middle of reception is detected by a reset circuit (not shown), the reset circuit outputs a reset signal to the latch 4 to reset the latch 4, and the latch 4 resets the first counter. Input of a signal to the disable terminal DEN to the 3 and the enable terminal EN to the second counter 5 is stopped.

Next, a detailed configuration of both pulse width detection units 1 and 2 will be described with reference to FIG.

As shown in FIG. 3, the received data via the data input terminal D is input to one input terminal of the AND gate 1a and inverted and input to one input terminal of the AND gate 2a. , A falling / rising edge detection unit 1 for detecting rising and falling of the received data waveform
b and 2b are input to one of the input terminals of the AND gates 1a and 2
At the same time as being input to the other input terminal of a, it is input to the other input terminals of both edge detection units 1b and 2b.

Then, the outputs of the both edge detection sections 1b and 2b are input to the reset terminals of the binary counters 1c and 2c, respectively, and the binary counters 1c and 2c are reset, so that the input pulses from both AND gates 1a and 2a are input. Both counters 1 are counted by binary counters 1c and 2c.
It is determined whether each of the output patterns of c and 2c has become a predetermined pattern corresponding to the allowable pulse width.
If a predetermined pattern is obtained by the collation, the collating units 1d and 2d perform flip-flop (hereinafter referred to as FF) 1
The verification signal is input to one of the input terminals of e and 2e, and the inverted signals of the verification signal are FF1f and FF1f, respectively.
It is input to one input terminal of 2f, and each FF 1e, 1f,
From the outputs of 2e and 2f, a signal corresponding to one input state is output at the input timing of the clock pulse to the other input terminal of each.

Further, the output signals of the FFs 1e and 1f are input to one input terminals of the AND gates 1g and 1h, respectively, and the output signal of the falling edge detection section 1b is input to the other input terminal, and the AND gates are similarly provided. The output signals of the FFs 2e and 2f are input to one of the input terminals of 2g and 2h, the output signal of the rising edge detection unit 2b is input to the other input terminal, and a match pulse signal is output from the AND gates 1g and 2g. And AND gate 1
The non-matching pulse signals are output from h and 2h, and the AND gate 1a, the falling edge detection unit 1b,
The positive pulse width detection unit 1 is configured by the binary counter 1c, the collation units 1d, FFs 1e, 1f, and AND gates 1g, 1h, and the AND gate 2a, the rising edge detection unit 2b, the binary counter 2c, the collation unit 2d, FF2e, The negative pulse width detection unit 2 is composed of 2f, AND gates 2g, 2h.

By the way, the received data S0 having the waveform as shown in FIG. 4A is stored in both the pulse width detection units 1 and 2 shown in FIG.
And a clock pulse S1 as shown in FIG. 4B is input, output waveforms S2, S of the AND gates 1a, 2a.
3 is as shown in FIGS. 4 (c) and 4 (d), respectively, and the output waveforms S4 and S5 of the both edge detectors 1b and 2b are shown in FIG.
As shown in (e) and (f), respectively.

The output patterns S6 and S7 of the binary counters 1c and 2c are as shown in FIGS. 4 (g) and 4 (h), respectively, and the count values of the counters 1c and 2c are "6". If the allowable pulse width is within the range of “10”, the output waveforms S8 and S9 of the collating units 1d and 2d are as shown in FIGS. 4 (i) and 4 (j), respectively. Matching units 1d and 2d that are respectively inverted
The other output waveforms S10 and S11 of FIG.
Since the negative pulse width exceeds the count value “6” to “10” corresponding to the allowable pulse width at this time, the AND gates 1g and 2h to FIGS.
Coincidence pulse signal S12 and non-coincidence signal S1 as shown in FIG.
3 is output.

Further, the clock pulse generator CPG has a second counter 5 which is a binary counter composed of a plurality of flip-flops and collating circuits 6a and F as shown in FIG.
It is configured by the collation unit 6 including F6b.
The received data S0 having the waveform as shown in FIG.
When the clock pulse S1 as shown in (b) is input to the clock terminal CK, counting is started by the synchronization establishment signal S20 to the enable terminal EN as shown in FIG. 6 (c).

At this time, the frequency of the clock pulse S1
In order to output the reception clock pulse at the central timing of the bit pulse of the reception data S0 based on the known information such as the transmission rate of the reception data S0 and the coding method, which pattern is the output pattern based on the count value of the second counter 5 When it becomes, the pattern is checked by the matching circuit 6
It is preset to a.

Then, for example, with respect to the count value of the second counter 5 as shown in FIG. 6D, an output pattern based on the count value of "2" as shown in FIG. By detecting the
As shown in (g), the reception clock pulse S21 is output from the FF 6b at the center timing of the bit pulse of the reception data S0 shown in FIG. 6 (a).

On the other hand, when the second counter 5 counts up to a predetermined value, the output pulse S22 of the second counter 5 itself at that time as shown in FIG. 6 (f) is input to the reset terminal RST, and the second The counter 5 is reset and repeats counting again, and as long as the signal S20 to the enable terminal EN is active, the second counter 5 keeps counting repeatedly in a free running state.

Therefore, with respect to the received data S0 having the waveform shown in FIG. 2A, since the waveform is unstable at the beginning of reception, both pulse width detections are performed as shown in FIGS. 2C and 2E, respectively. As the mismatched pulse signals S25 and S13 are output from the units 1 and 2, and the waveform of the reception data S0 stabilizes, as shown in FIG.
As shown in (b) and (d) respectively, the coincidence pulse signals S12 and S26 are output from both the pulse width detection units 1 and 2,
The logical sum of the coincidence pulse signals S12 and S26 shown in FIGS. 2B and 2D is input to the clock terminal CK of the first counter 3 through the OR gate OR1, and the OR gate OR2
Through the mismatch pulse signal S shown in FIGS. 2 (c) and 2 (e).
The logical sum of 25 and S13 is input to the reset terminal RST of the first counter 3.

After the first counter 3 is reset, for example, five coincidence pulse signals are continuously input to the clock terminal CK, so that the first counter 3 latches as shown in FIG. 2 (f). 4 outputs the counter pulse S27, and the latch 4 outputs the synchronization establishment signal S20 as shown in FIG. 2 (g) to the enable terminal EN of the second counter 5.
And the disabling terminal DEN of the first counter 3 to stop the operation of the first counter 3, while the second counter 5 is in the active state, and the reception clock pulse S21 as shown in FIG. Is output to the waveform synchronization circuit 7.

By the way, when reception completion or an error in the middle of reception is detected by the reset circuit (not shown),
The reset signal S29 as shown in FIG.
Is input to the reset terminal of and the latch 4 is reset,
The input of the synchronization establishment signal from the latch 4 to the enable terminal EN of the second counter 5 and the disenable terminal DEN of the first counter 3 is stopped, and the synchronization establishment operation is repeated from the beginning.

In this way, at the central timing of the data bits of the reception data S0 having the waveform shown in FIG.
As shown in FIG. 7B, when the reception clock pulse S21 is output from the FF 6b of the matching unit 6 to the waveform synchronization circuit 7, the reception clock pulse S21 is generated by the waveform synchronization circuit 7.
The data frame of the received data S0 is sampled by 21, and the signal whose waveform has been shaped as shown in FIG. 7C is output from the waveform synchronization circuit 7 to the subsequent circuit.

Therefore, according to the above embodiment, when the coincidence pulse signals from the pulse width detection units 1 and 2 are continuously counted by the synchronization establishment unit SYN during the reception of the preamble of the reception data, the synchronization is established. Is determined to have been established, the synchronization establishment signal is output to the clock pulse generator CPG, and the clock pulse generator CPG generates the reception clock pulse at the center timing of the bit pulse of the data frame of the reception data. Even if noise is included, the coincidence pulse signals from both the pulse width detection units 1 and 2 do not continue a predetermined number of times and a non-coincidence pulse signal is output in the middle, so that it is possible to prevent the influence of noise as in the conventional case.

Further, since both the pulse width detecting units 1 and 2, the synchronization establishing unit SYN, and the clock pulse generating unit CPG can be easily constructed by a counter or a logic gate, the P
The analog circuit such as the LL circuit and the complicated digital circuit such as the microcomputer are not required, the configuration can be simplified and downsized, and the cost is reduced. Further, the received data is not an indirect method such as an error check. Since synchronization is directly established with the preamble waveform after the stabilization of, reliable synchronization can be established, and reliability and stability are excellent.

In the above embodiment, the case where it is determined that the synchronization has been established when the coincidence pulse signal is continuously counted five times by the first counter 3 has been described.
The value is not limited to “5” in particular, and may be appropriately determined based on the frequency of the clock pulse, the transmission rate of the received data, the coding method, and the like.

Regarding the set value of the allowable pulse width,
The setting value "2" of the matching circuit 6a is not limited to these values, and the detailed circuit configuration is not limited to the above embodiment.

[0042]

According to the first and second aspects of the present invention, during the reception of the preamble of the received data, when the synchronization establishing section continuously counts the coincidence pulse signals from the pulse width detecting section a predetermined number of times, When the synchronization is established, the clock pulse generator generates the reception clock pulse at the center timing of the bit pulse of the data frame of the reception data, so if the reception data contains noise, the pulse width detector From this, the coincidence pulse signal is not determined to be erroneously established as synchronization without continuing a predetermined number of times, it is possible to prevent the influence of noise, and moreover, by directly establishing synchronization with the preamble waveform after stabilization of the received data,
It is possible to reliably establish synchronization and improve reliability and stability.

According to the third and fourth aspects of the invention, since the synchronization establishing section and the clock pulse generating section can be configured by simple counters and logic gates, the conventional microcomputer and PLL circuit etc. are unnecessary. In addition, the structure can be simplified and downsized, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of FIG.

3 is a block diagram of a part of FIG. 1. FIG.

FIG. 4 is an operation explanatory diagram of FIG. 3;

5 is a block diagram of another part of FIG. 1. FIG.

FIG. 6 is an operation explanatory diagram of FIG. 5;

FIG. 7 is an explanatory diagram of still another part of the operation shown in FIG. 1;

[Explanation of symbols]

 1, 2 Positive and negative pulse width detection unit 3 First counter 4 Latch S Synchronization establishment unit 5 Second counter 6 Collation unit CPG Clock pulse generation unit

Claims (4)

[Claims] 1. A bit synchronization circuit for serial communication, wherein a predetermined preamble is provided at the beginning of a data packet to detect a synchronization timing with received data by serial communication and generate a reception clock pulse. It is detected whether or not the pulse width of the bit pulse is within the allowable pulse width obtained by adding a predetermined allowable error to the pulse width specified by the transmission rate of the received data. And a pulse width detection unit that outputs a mismatch pulse signal respectively, and when the mismatch pulse signal is reset, the match pulse signal is counted, and when the match pulse signal is continuously counted a predetermined number of times, a synchronization establishment signal is generated. And a data frame of the received data by the synchronization establishment signal. Bit synchronization circuit of the serial communication, characterized in at the center timing of the bit pulse that includes a clock pulse generator for generating a receive clock pulse. 2. A bit synchronization method of serial communication in which a reception clock pulse is generated by detecting a synchronization timing with reception data by serial communication in which a predetermined preamble is provided at the head of a data packet, the preamble of the reception data It is detected whether the pulse width of the bit pulse of is within the allowable pulse width obtained by adding a predetermined allowable error to the pulse width specified by the transmission rate of the received data, and the pulse width of the bit pulse of the preamble is It is determined that the synchronization has been established when a predetermined number of times continuously within the allowable pulse width, and after the synchronization is established, the clock pulse generator outputs the reception clock pulse at the central timing of the bit pulse of the data frame of the reception data. A bit synchronization method for serial communication characterized by the above. 3. The serial communication bit synchronization circuit according to claim 1, wherein the synchronization establishing unit includes a counter and a latch that receives an output pulse of the counter as an input. Synchronous circuit. 4. The bit synchronization circuit for serial communication according to claim 1, wherein the clock pulse generation unit includes a counter and a collation unit that detects that the output pattern of the counter has become a predetermined pattern. A bit synchronization circuit for serial communication characterized in that