JPH0759031A - Sound mute control circuit - Google Patents

Abstract

PURPOSE:To prevent production of noise and to attain smooth sound demodulation by applying muting to a sound output for a period when sound frame synchronization is implemented and a sound control code to control sound data is established. CONSTITUTION:When frame synchronization is unlocked in a trigger circuit 8, a pulse input signal to a timing generating circuit B6 stops. When the pulse input signal to the circuit B6 is interrupted, an output signal of the circuit B6 is interrupted. Since an output signal from the circuit B6 is used for an input signal to a clock input of an FF 9 provided to an output section of a control code detection circuit 4, the control code is used to hold data just before frame synchronization is unlocked due to interruption of the clock signal to the FF 9 till frame synchronization is applied again. Furthermore, a comparator circuit 10 compares output data of the circuit 4 with output data of the FF 9 to control a mute signal based on the result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mute control technique for an audio signal processing circuit of a PCM broadcast receiver.

[0002]

2. Description of the Related Art An example of a mute control circuit of this type is MU.
The case of the SE method will be described. The MUSE system is one of the transmission systems for high-definition signals. The audio data multiplexed in the vertical blanking period in this MUSE system is a 1.35 Mbps serial audio data bit stream that is subjected to frequency conversion, time axis conversion, and audio frame deinterleave processing in the audio signal processing unit in the MUSE decoder. Becomes Further, frame synchronization detection, voice control code detection, bit deinterleave, BCH error correction, word deinterleave, DPCM decoding processing, D / A
A conversion process is performed to form an audio signal.

FIG. 6 shows a conventional frame synchronization detection circuit section and control code detection circuit section. Reference numeral 1 denotes a frame sync detection circuit which outputs an address clear signal 2 and a frame sync signal 3 (hereinafter referred to as FDET). Reference numeral 4 is a control code detection circuit, 5 is a timing generation circuit A for generating the timing required for the control code detection circuit, 6 is an output signal of the timing generation circuit A, and is required for the control code detection circuit. Timing generation circuit B for generating timing
Is. The timing of the timing generation circuit A5 is compensated by the address clear signal 2 output from the frame synchronization detection circuit 1. After that, it operates by a clock of 1.35 MHz and outputs a necessary timing signal to the control code detection circuit 4. Further, FDET3 is a signal that changes in the state of frame synchronization detection, and the FDET3 is a mute signal. In the case where the frame synchronization is lost after the frame synchronization is applied in Fig. 7 and the frame synchronization is applied again, and the 1.35 MHz clock is normally input even if the frame synchronization is lost (for example, the special playback mode of the MUSE laser disk). Shows the timing relationship of time). In the conventional circuit, the mute is released at the same time as the frame synchronization is applied.

[0004]

However, in the circuit configuration described in the prior art, once the frame synchronization is applied, it is determined that the clock of 1.35 MHz is normally input even if the frame synchronization is lost. Is operating, the control code detection circuit 4 operates. For example, in the MUSE laser disk special playback mode (fast forward and rewind), the video signal is sent as usual (1.35MHz clock is input normally) but the audio data disappears, or It's disordered. In such a case, of course, the voice control code is not the original state and is erroneous data. Therefore, when the erroneous voice control code data is detected and the voice data is input again and the frame synchronization is detected, the mute is released. The disturbed voice data caused by controlling the voice data with an incorrect voice control code is output as noise (see FIG. 7). It is an object of the present invention to prevent the generation of noise due to this erroneous voice control code and shorten the mute time when normal voice data is input again, thereby performing voice control more faithful to the original voice data.

[0005]

A frame synchronization detection circuit for detecting a frame synchronization pattern from a digital data signal transmitted while having a frame structure including a frame synchronization pattern composed of a plurality of bits and a control code, and the frame synchronization detection circuit. And a mute delay circuit capable of freely setting a time from immediately after the frame sync signal is input from the circuit to the frame sync state until the mute is released by a control signal.

A frame sync detection circuit for detecting a frame sync pattern from the digital data signal, a control code detection circuit for inputting the digital data signal and detecting a voice control code, an operating frequency clock for the digital data signal, and A first timing generation circuit for inputting a timing signal from the frame synchronization detection circuit to generate timing necessary for the control code detection circuit, a signal indicating a frame synchronization state from the frame synchronization detection circuit, and the first timing generation circuit. When the output signal of the timing generation circuit is input and the frame is asynchronous, a trigger circuit that outputs a signal in which the output signal of the first timing generation circuit is stopped, and the control code detection by inputting the output signal of the trigger circuit A second timing generation circuit that generates the timing required for the circuit, and A flip-flop for inputting the output data of the control code detection circuit and the output signal of the second timing generation circuit and latching the data, a frame synchronization signal, the digital data signal, and the output data of the flip-flop and inputting the frame synchronization again. It is characterized by comprising a comparison circuit capable of comparing the voice control code data newly output from the control code detection circuit with the output data of the flip-flop when the delay occurs and adjusting the mute release time based on the result.

[0007]

With this configuration, it is possible to prevent noise from occurring by muting the audio output until the audio frame is synchronized and the audio control code for controlling the audio data is established.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An audio mute control in the MUSE system will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals. The frame synchronization detection circuit 1 is the same as the conventional circuit of FIG. In one embodiment of the present invention, the FDET signal 3 which is the output signal of the frame sync detection circuit 1 used for the mute signal of the frame sync detection circuit 1 and the conventional circuit of FIG. 6 is input to the mute delay circuit 7 and its output is output. It is configured to be used as a mute signal. The basic structure of the mute delay circuit 7 is composed of a counter and a selector, and delays the FDET3 signal until the counter value set by the selector is reached. The role of the mute delay circuit 7 is to prevent the generation of noise due to the disturbance of the audio output that is likely to occur immediately after the frame synchronization, and the mute delay circuit 7 determines how long the mute is performed after the frame synchronization.
It is controlled by inputting a control signal, which is an input signal of the above, to the selector. As a result, it is possible to prevent the occurrence of noise in the audio output immediately after frame synchronization.

(Embodiment 2) FIG. 2 shows another embodiment of the present invention. 2, the same parts as those in FIG. 6 are designated by the same reference numerals. In another embodiment of the present invention, in addition to the conventional circuit of FIG. 6, a trigger circuit 8 is provided between the timing generation circuit A5 and the timing generation circuit B6 to detect the control code when the frame asynchronous state changes to the frame synchronous state. The voice control code data newly output from the circuit 4 and the flip-flop 9
Of the output data of (1) and the mute release time can be adjusted according to the result.

FIG. 3 is a diagram showing the output timing of the timing generating circuit A5. The pulse is output at every frame (every 1 ms) at the timing when the control code can be detected. FIG. 4 shows the output timing of the timing generation circuit B6. The pulse is output for every 18 frames from the rising timing of the pulse of the timing generation circuit A5.

The role of the trigger circuit 8 is to stop the pulse of the input signal to the timing generation circuit B6 when the frame synchronization is lost. The trigger circuit is AND
Consists of a gate, etc. When the pulse of the input signal to the timing generating circuit B6 is interrupted, the timing generating circuit B is
The pulse of the output signal of 6 is also cut off. Since the output signal of the timing generation circuit B6 is used as the input signal to the clock of the flip-flop 9 provided in the output section of the control code detection circuit 4, the control code is framed by the interruption of the clock signal to the flip-flop 9. The data immediately before synchronization is held until the frame is synchronized again.
This is shown in FIG.

Further, the comparator circuit 10 detects that when the frame synchronization is lost and the frame is synchronized again as shown in FIG.
The output data of the control code detecting circuit 4 and the output data of the flip-flop 9 are compared, and the mute signal is controlled according to the result. By adding the trigger circuit 8 and the comparison circuit 10 in this way, it is possible to perform sound control more faithful to the original sound data rather than muting for a certain period.

[0014]

As described above, according to the present invention, the disturbance controlled by an erroneous voice control code during the period until the voice control code for controlling the voice data is established after the voice frame synchronization is applied. It is possible to prevent the generation of noise caused by the audio data. Further, by controlling the mute release time, it is possible to perform voice control more faithful to the original voice data.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an audio mute control circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an audio mute control circuit according to another embodiment of the present invention.

FIG. 3 is an output timing chart of the timing generation circuit A of the audio mute control circuit.

FIG. 4 is an output timing diagram of the timing generation circuit B of the audio mute control circuit.

FIG. 5 is a diagram showing an output timing of a comparison circuit of the audio mute control circuit.

FIG. 6 is a conventional audio mute control circuit diagram.

FIG. 7 is a timing diagram of a conventional audio mute control circuit.

[Explanation of symbols]

 1 frame synchronization detection circuit 2 address clear signal 3 frame synchronization signal 4 control code detection circuit 5 timing generation circuit A 6 timing generation circuit B 7 mute delay circuit 8 trigger circuit 9 flip-flop 10 comparison circuit

Claims (2)

[Claims] 1. A frame synchronization detection circuit for detecting a frame synchronization pattern from a digital data signal transmitted while having a frame structure including a frame synchronization pattern of a plurality of bits and a control code, and a frame synchronization detection circuit for frame synchronization. An audio mute control circuit comprising: a mute delay circuit that can freely set a time from immediately after a signal is input to change from frame asynchronous state to frame synchronous to mute release by a control signal. 2. A frame synchronization detection circuit for detecting a frame synchronization pattern from a digital data signal transmitted while having a frame structure including a frame synchronization pattern consisting of a plurality of bits and a control code, and a voice which inputs the digital data signal. A control code detection circuit for detecting a control code, a first timing generation for inputting an operating frequency clock of the digital data signal and a timing signal from the frame synchronization detection circuit, and generating a timing necessary for the control code detection circuit. Circuit, a signal indicating the frame synchronization state from the frame synchronization detection circuit and the output signal of the first timing generation circuit are input, and in the case of frame asynchronization, a signal that stops the output signal of the first timing generation circuit And the output signal of the trigger circuit A second timing generation circuit for generating a timing necessary for the control code detection circuit; a flip-flop for inputting the output data of the control code detection circuit and the output signal of the second timing generation circuit and latching the data; When the frame synchronization signal, the digital data signal, and the output data of the flip-flop are input and the frame synchronization is applied again, the voice control code data newly output from the control code detection circuit is compared with the output data of the flip-flop. An audio mute control circuit comprising: a comparison circuit capable of adjusting the mute release time based on the result.