JP3018848B2 - Audio mute control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mute control technique for an audio signal processing circuit of a PCM broadcast receiver.

[0002]

2. Description of the Related Art An example of this type of mute control circuit is an MU.
The case of the SE method will be described. The MUSE method is one of the transmission methods of a Hi-Vision signal. In the MUSE system, audio data multiplexed during the vertical blanking period is converted into a 1.35 Mbps serial audio data bit stream by frequency conversion, time axis conversion, and audio inter-frame deinterleaving in an audio signal processing unit in the MUSE decoder. Becomes Furthermore, frame synchronization detection, voice control code detection, bit deinterleaving, BCH error correction, word deinterleaving, DPCM decoding processing, D / A
A conversion process is performed to obtain an audio signal.

FIG. 6 shows a conventional frame synchronization detecting circuit and a control code detecting circuit. 1 is the frame synchronization pattern
Frame synchronization from digital data signal including control code
A frame synchronization detection circuit for detecting a pattern.
Ri, address clear signal 2 and the frame synchronizing signal 3 (hereinafter, F
DET). The FDET signal is used for frame synchronization detection.
This signal changes with the output status and is used as a mute signal.
Used. 4 is a control code from the digital data signal.
This is a control code detection circuit for detecting. 5 is the digital
Operating frequency clock (1.35 MHz clock )
Address clear signal 2 from the frame synchronization detection circuit
Is a timing generation circuit A to which
The timing is compensated by the rear signal 2. 1.35 afterwards
It operates with a clock of MHz and
Timing at which control code can be detected from digital data signal
To output a pulse and detect the control code.
An imming pulse is supplied to the control code detection circuit. 6
Inputs the output signal of the timing generating circuit A, 18
The timing generation circuit B that outputs a pulse for each frame
The timing pulse from the timing generation circuit A
Pulse for one frame from the rising edge of the
And the control code detection circuit generates one frame of data.
Required to detect control codes from digital data
Supplied to the control code detection circuit as a
You. Reference numeral 9 denotes a flip-flop for detecting the control code.
Latch the control code detected on the
Each time a timing pulse is input from the raw circuit B,
The latched control code is output. In FIG.
The FDET signal used as the
The output from the detection circuit is directly supplied to the mute circuit.
It has become. Therefore, in the conventional circuit, the frame
The mute circuit is immediately controlled by the presence or absence of the
Mute is released at the same time as frame synchronization. Or
In such a conventional circuit configuration, for example, a MUSE laser
-As in the special playback mode of the disc,
1.35MHz clock is input normally even if the period is out of date
FIG. 7 shows the timing relationship in the case of the above. Figure 7
Frame synchronization is lost after frame synchronization
If frame synchronization is restored, correct voice control code
Mute is released when there is no
Speech data is controlled by incorrect control code output
It has been shown.

[0004]

However, in the circuit configuration described in the prior art, once the frame synchronization is performed, the timing generation circuit A5 determines that the 1.35 MHz clock is normally input even if the frame synchronization is lost. Operates, the control code detection circuit 4 operates. For example, in the special playback mode of the MUSE laser disk (fast forward, rewind), the video signal is sent as usual (the 1.35 MHz clock is normally input), but the audio data disappears, or It is disordered. In such a case, naturally, the voice control code is not in the original state, but is incorrect data. Therefore, when the data of the incorrect voice control code is detected and the voice data is input again and the frame synchronization is detected, the mute is released. In addition, disturbed voice data caused by controlling voice data with an incorrect voice control code is output as noise (see FIG. 7). It is an object of the present invention to prevent the occurrence of noise due to the incorrect voice control code and to reduce the mute time when normal voice data is input again, thereby performing voice control more faithful to the original voice data.

[0005]

A frame synchronization detecting circuit for detecting a frame synchronization pattern from a digital data signal transmitted while having a frame structure including a frame synchronization pattern composed of a plurality of bits and a control code, and the frame synchronization detection. A mute delay circuit that can freely set a time from a time immediately after a frame synchronization signal is input from the circuit and the state changes from the frame asynchronous state to the frame synchronization until the mute is released by a control signal.

A frame synchronization detection circuit for detecting a frame synchronization pattern from the digital data signal, a control code detection circuit for receiving the digital data signal and detecting a voice control code, an operating frequency clock for the digital data signal, A first timing generation circuit that receives a timing signal from the frame synchronization detection circuit and generates a necessary timing for the control code detection circuit; a signal indicating a frame synchronization state from the frame synchronization detection circuit; In the case of inputting the output signal of the timing generation circuit of the first embodiment, and outputting a signal in which the output signal of the first timing generation circuit is stopped when the frame is asynchronous, a control circuit detecting the control signal by inputting the output signal of the trigger circuit A second timing generator for generating the necessary timing for the circuit, and A flip-flop for inputting the output data of the control code detection circuit and the output signal of the second timing generation circuit and latching the data; and inputting a frame synchronization signal, the digital data signal, and the output data of the flip-flop, and re-frame synchronization. And a comparator circuit that compares the voice control code data newly output from the control code detection circuit with the output data of the flip-flop and adjusts the mute release time based on the result.

[0007]

With this configuration, it is possible to prevent the occurrence of noise by muting the audio output until the audio frame synchronization is established and the audio control code for controlling the audio data is established.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings, with regard to audio mute control in the MUSE system.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 6 are denoted by the same reference numerals. The frame synchronization detection circuit 1 is the same as the conventional circuit of FIG. In one embodiment of the present invention, the FDET signal 3 of the output signal of the frame synchronization detection circuit 1 used for the mute signal of the frame synchronization detection circuit 1 and the conventional circuit of FIG. It is configured to be used as a mute signal. The basic configuration of the mute delay circuit 7 includes a counter and a selector, and delays the FDET3 signal until the counter value set by the selector is reached. The role of the mute delay circuit 7 is to prevent the occurrence of noise due to disturbance of the audio output, which tends to occur immediately after the frame synchronization, and how long the mute should be applied after the frame synchronization is determined by the mute delay circuit 7.
The control is performed by inputting a control signal, which is an input signal, to the selector. As a result, it is possible to prevent noise in the audio output immediately after the frame synchronization.

(Embodiment 2) FIG. 2 shows another embodiment of the present invention. 2, the same parts as those in FIG. 6 are denoted by the same reference numerals. In another embodiment of the present invention, a trigger circuit 8 is provided between the timing generation circuit A5 and the timing generation circuit B6 in addition to the conventional circuit of FIG. The voice control code data newly output from the circuit 4 and the flip-flop 9
And a comparison circuit 10 which can adjust the mute release time based on the result.

FIG. 3 is a diagram showing the output timing of the timing generation circuit A5. The pulse is output at a timing at which a control code can be detected every frame (every 1 ms). FIG. 4 shows the output timing of the timing generation circuit B6. The pulse is output for one frame every 18 frames from the rising edge of the pulse of the timing generation circuit A5.

The role of the trigger circuit 8 is to stop the pulse of the input signal to the timing generation circuit B6 when the frame synchronization is lost. The trigger circuit is AND
It is composed of a gate and the like. When the pulse of the input signal to the timing generation circuit B6 stops, the timing generation circuit B
The pulse of the output signal of No. 6 also stops. Since the output signal of the timing generation circuit B6 is used as an input signal to the clock of the flip-flop 9 provided at the output part of the control code detection circuit 4, when the clock signal to the flip-flop 9 is interrupted, the control code becomes the frame. The data immediately before the synchronization is lost is held until the frame is synchronized again.
FIG. 5 shows this state.

When the frame synchronization is lost and the frame is synchronized again, as shown in FIG.
The output data of the control code detection circuit 4 is compared with the output data of the flip-flop 9, and the result is used to control the mute signal. By adding the trigger circuit 8 and the comparison circuit 10 in this manner, a mute is not applied for a certain period, but audio control more faithful to original audio data can be performed.

[0014]

As described above, according to the present invention, during the period from when the voice frame synchronization is applied to when the voice control code for controlling the voice data is established, the disturbance controlled by the wrong voice control code is performed. It is possible to prevent the generation of noise due to the voice data. Further, by controlling the mute release time, it is possible to perform sound control more faithful to the original sound data.

[Brief description of the drawings]

FIG. 1 is an audio mute control circuit diagram according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an audio mute control circuit according to another embodiment of the present invention.

FIG. 3 is an output timing chart of a timing generation circuit A of the audio mute control circuit.

FIG. 4 is an output timing chart of a timing generation circuit B of the audio mute control circuit.

FIG. 5 is a diagram showing an output timing of a comparison circuit of the audio mute control circuit.

FIG. 6 is a conventional audio mute control circuit diagram.

FIG. 7 is a timing chart of a conventional audio mute control circuit.

[Explanation of symbols]

 Reference Signs List 1 frame synchronization detection circuit 2 address clear signal 3 frame synchronization signal 4 control code detection circuit 5 timing generation circuit A 6 timing generation circuit B 7 mute delay circuit 8 trigger circuit 9 flip-flop 10 comparison circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/50-5/63

Claims (2)

(57) [Claims] [Claim 1, further comprising a frame structure including a frame synchronization pattern and the control code consisting of plural bits, the frame
Data is composed for each frame based on the system synchronization pattern
A frame synchronization detection circuit for detecting a frame synchronization pattern from the digital data signals being, the frame same
Hand controlled by the detection signal from the phase detection circuit
Stage and time for supplying the detection signal to the mute means
A mute delay circuit for delaying
Mute the control signal for controlling the delay time of the delay circuit
Control means for supplying a signal to the delay circuit.
When the frame synchronization signal is not detected by the
Supplying a mute signal to the mute means,
The frame synchronization signal is detected by the frame synchronization detection circuit.
When issued, a mute release signal is sent to the mute means.
Supply through the mute delay circuit,
The frame synchronization signal is detected by the frame synchronization detection circuit
Frame synchronization detection
The delay time from when the frame synchronization signal is detected by the output circuit and the mute release signal is supplied to the mute means and the mute is released immediately after the change to the frame synchronization is set by a control signal for controlling the mute delay circuit.
Audio mute control circuit, characterized in that the the like. 2. A frame structure comprising a frame synchronization pattern comprising a plurality of bits and a control code , wherein the frame
Data is composed for each frame based on the system synchronization pattern
A frame synchronization detection circuit for detecting a frame synchronization pattern from a digital data signal being processed, and a plurality of bits of the control code from the digital data signal.
Assigned to control audio data in
And control code detecting circuit for detecting the number bits of the audio control code, the timing signal from the operating frequency clock and the frame synchronization detecting circuit of the digital data signal is input
Timing that can detect the control code for each frame
A first timing signal generating circuit for generating a pulse by a signal, and a timing signal from the first timing signal generating circuit.
And the timing required for the control code detection circuit
As a signal, a pulse with a pulse width of 1 frame is used for 18 frames.
A second timing signal generation circuit for generating each time, the first timing signal generation circuit, and the second timing signal.
The frame is inserted and disposed between the
A signal indicating a frame synchronization state from a synchronization detection circuit;
The output signal of the first timing signal generation circuit is
Is a trigger circuit composed of AND gates, and a flip-flop for latching the input data of the output signal of the output data and the second timing signal generating circuit of the control code detecting circuit, the frame synchronization signal and the control Output from code detection circuit
When the voice control code data to be output and the output data of the flip-flop are input and the frame is again synchronized from the frame asynchronous state , the frame synchronization is deviated from the voice control code data newly output from the control code detection circuit.
A comparison circuit for comparing the output data of the flip-flop with the immediately preceding data held therein, and when the frame synchronization has been resumed from the frame asynchronous state.
Receiving the first timing signal via the trigger circuit.
Signal is the control code detection circuit and the second timing generation circuit.
Is supplied from the control code detection circuit to the
Is latched by the flip-flop,
Output from the flip-flop at the second timing.
And the control code inputted to the flip-flop
Speech control code data newly output from the detection circuit
The output data of the flip-flop is compared by the comparison circuit.
Comparison, the comparison confirms the identity of the two signals
The generation of the mute release signal is delayed until the comparison circuit
Mute release time can be adjusted based on the comparison result in
Audio mute control circuit, characterized in that the the like.