JP3263567B2 - Error correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an RDS broadcast signal and FM
The present invention relates to an error correction device that receives a signal to which an error correction code is added in advance, such as a multiplex broadcast signal, and executes an error correction process.

[0002]

2. Description of the Related Art When receiving a broadcast signal or the like, a received signal generally contains a large amount of noise due to interference generated on a transmission path such as fading. In a demodulation circuit for demodulating a received signal into digital data, It may not be possible to determine exactly 0 or 1. Therefore, in the conventional RDS broadcast receiver and FM multiplex broadcast receiver, the data demodulated by the demodulation circuit is subjected to an error correction process to improve the accuracy of the data.

[0003]

In the conventional demodulation circuit,
If the original data is 1 but the level becomes 0 close to 1 due to noise, the demodulation circuit determines that the data is 0 instead of 1. If the number and position of such erroneous determination bits are within the range of the correction capability of the error correction circuit,
There is no problem because the error is corrected by the error correction processing. However, if the correction capability is exceeded, the correction becomes impossible.

For example, an error correction circuit of an RDS broadcast receiver can correct up to 5 bits when the error bit interval is 5 bits or less, but can correct even a 2-bit error when the interval exceeds 5 bits. Can not.

[0005]

According to the present invention, an input signal is demodulated to output a demodulated data pattern, and a reliability information bit indicating the reliability of each demodulated data of the demodulated data pattern is corresponded to the demodulated data. A demodulation circuit that performs error correction on the demodulated data pattern, an error correction circuit that performs error correction on the demodulated data pattern, and a control circuit that controls error correction on the demodulated data pattern in accordance with the reliability information bits. .

Further, in the present invention, the control circuit operates demodulated data in which the reliability information bits are at a predetermined level to generate demodulated data patterns of all possible combinations of the demodulated data patterns. A generation circuit, wherein the error correction circuit performs error correction on the demodulated data patterns of all the generated combinations.

Further, in the present invention, the generation circuit inputs the reliability information bits of the predetermined level, and generates all possible combinations of demodulated data corresponding to the reliability information bits of the predetermined level. An error correction control circuit for sequentially outputting bit data, and sequentially changing demodulated data corresponding to a reliability information bit of a predetermined level in the demodulated data pattern to bit data of all of the combinations to demodulate all of the combinations. It has a logic circuit for sequentially outputting data patterns.

In the present invention, the generation circuit includes a first shift register and a second shift register which respectively take in the demodulated data pattern and the reliability information bit and perform a shift operation in synchronization with each other, and a second shift register. A number-of-bits determination circuit for determining the number n of reliability information bits of a predetermined level among the fetched reliability information bits, wherein the error correction control circuit is performed by the first and second shift registers. A first counter that counts the shift operation of the 2nd nth cycle shift operation, and counts the number of occurrences of the predetermined level reliability information bits appearing during the 1st cycle shift operation. A second counter for receiving the predetermined level of reliability information bits and receiving the predetermined level according to the contents of the first and second counters. The bit data of all possible combinations of demodulated data corresponding to the reliability information bits are sequentially output in each cycle, and the logic circuit corresponds to the reliability information bits of a predetermined level in each cycle. The demodulated data to be output is changed to the sequentially output bit data, and the demodulated data patterns of all the combinations are sequentially output to the error correction circuit.

Further, according to the present invention, a signal distance measuring circuit for measuring an inter-signal distance between an error correction result and the demodulated data for at least a demodulated data pattern which has been successfully corrected as a result of the correction processing in the error correction circuit; A minimum value judging circuit for judging the minimum value of the inter-signal distance from the measurement result of the demodulated data pattern that has been corrected successfully in the distance measurement circuit, wherein the demodulated data pattern having the inter-signal distance judged to be the minimum value Is output as the final error correction result.

Further, in the present invention, the minimum value determination circuit has a determination circuit for determining whether or not the minimum value is larger than a predetermined value. When the minimum value is larger than a predetermined value, the control signal is output. It is characterized by outputting. Also,
In the present invention, the signal distance measuring circuit measures a distance between signals based on the error correction result, demodulated data from the demodulation circuit, and reliability information bits.

In the present invention, the input signal is RD
It is an S broadcast signal or an FM multiplex broadcast signal.

[0012]

According to the present invention, all the demodulated data patterns that can be taken by the demodulated data are generated based on the reliability information bits indicating the reliability of the demodulated data. Since the correction circuit is executed, even if the error correction circuit exceeds the correction capability range, the error correction can be reliably realized.

When there are a plurality of data patterns for which error correction has succeeded, the distance between signals between the error correction result and the demodulated data is measured, and the minimum value of the measured distance between signals is determined. Since the data pattern with the minimum distance is adopted as the final error correction result, a more accurate correction result can be obtained.

[0014]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention. An example will be described in which one block of data corrects an RDS signal composed of a total of 26 bits including error correction bits. . In FIG. 1, 1 is the received R
A demodulation circuit that demodulates the DS broadcast signal and outputs a demodulated data pattern in units of one block, and outputs a reliability information bit T indicating the likelihood of each bit data of the demodulated data pattern in one block. The 26-bit first shift register, in which the demodulated data pattern of the block is fetched via the switch 2 and the shift operation of the fetched demodulated data pattern is repeated a plurality of cycles, is 1
A 26-bit second shift register 6 having a 26-bit reliability information bit corresponding to the demodulated data pattern of the block via the switch 3 and repeating a shift operation of the captured 26-bit reliability information bit for a plurality of cycles, 6 A synchronous reproduction circuit for generating a synchronous timing signal based on the demodulated data; 7, an error correction control circuit for controlling error correction; and 8, a bit of the one-level reliability information bit taken into the second shift register 5. A bit number determination circuit 9 for determining the number controls the passing of the reliability information bits output from the second shift register 5 by an enable signal EN output from the error correction control circuit 7.
The ND gate 10 and the output of the first shift register 4
EXOR gate which takes exclusive OR with the output of D gate 9; 11 is an error correction circuit which inputs data from EXOR gate 10 to execute error correction; 12 is error correction result and demodulation from first shift register A signal distance measuring circuit for measuring a distance between signals with data based on the reliability information bits from the second shift register; This is a minimum value determination circuit that determines the minimum value.

The switches 2 and 3 are switched by switch switching signals SW1 and SW2 from the error correction control circuit 7, and the shift registers 4 and 5 are synchronized according to the same clock signal CL from the error control circuit 7. To perform a shift operation. Further, the error correction control circuit 7 includes a shift register 2,
3, a loop counter 21 for counting the number of cycles of the shift operation performed by the third shift register 5 during one cycle.
1. An order counter 20 for counting the number of one-level reliability information bits output from the CPU, and an identification circuit 22 for identifying whether or not the bit number n determined by the bit determination circuit 8 is larger than a reference value N. Control signal A from outside
Thus, the reference value N is set to either 2 bits or 4 bits.

The minimum value judging circuit compares the inter-signal distance m input through the AND gate 13 with a reference value M, and determines whether the distance m is smaller than the already stored minimum value only when the signal distance is smaller than the reference value M. Then, the minimum value is updated only when the value is small. In FIG. 1,
Correction OK indicating that the correction was successful in the error correction circuit 11
The / NG signal is input to the AND gate 13 inserted on the input side of the minimum value determination circuit 14, and only the distance between signals of the data pattern that has been successfully corrected is input to the minimum value determination circuit 14. The signal distance measurement circuit 12 may measure the inter-signal distance only for a data pattern in which an error has succeeded.

Hereinafter, the operation of the present embodiment will be described with reference to FIGS. First, as shown in FIG. 2, the demodulation circuit 1 compares the input analog received signal with a first threshold level V0, and when the received signal level is higher than V0, the level is 1 level, and when it is lower, the level is 0 level. Output demodulated data. Further, the demodulation circuit 1 compares the received signal level with the second and third threshold levels VH and VL in order to detect the certainty of the demodulated data, and the received signal level is higher than VH or lower than VL. At this time, a 0-level reliability information bit is output, and when the received signal level is between VH and VL, a 1-level reliability information bit is output. That is, when the degree of certainty of the demodulated data is high, a 0-level reliability information bit is output, and when the degree is low, a 1-level reliability information bit is output.

Therefore, the received true data pattern is data such as DD shown in FIG.
The demodulated data pattern D0 shown in FIG. 3A and the reliability information bit string T shown in FIG.
Assume that 0 is output. When the demodulation data and the reliability information bit are output from the demodulation circuit 1, the error correction control circuit 7 sets the switch switching signals SW1 and SW2 to one level, so that the switches 2 and 3 are switched upward in the figure. The first shift register 4 captures a demodulated data pattern of 26 bits per block, and the second shift register 5 similarly captures a 26-bit reliability information bit string of one block. When each data is taken in, the error correction control circuit 7 sets the switch switching signals SW1 and SW2 to the 0 level, so that the switches 2 and 3 are switched to the lower side in FIG.
The outputs of the shift registers 4 and 5 are fed back to the shift registers 4 and 5, respectively.
It becomes possible to shift the taken data cyclically.

Here, the bit number determination circuit 8 determines the number n of one-level reliability information bits among all the reliability information bits taken into the second shift register 5. This bit number n is taken in by the error correction control circuit 7 and an internal identification circuit 22 identifies whether or not it is larger than a reference value N. When the value is larger than the reference value, a normal error correction operation using no reliability information bit (hereinafter, referred to as hard decision error correction operation) is performed. When the value is smaller than or equal to the reference value, the reliability information bit is used. Perform a soft decision error correction operation. Further, in order to inform the next stage whether the error correction has been performed by the hard decision or the soft decision, the error correction control circuit 7 generates a control signal hard / soft indicating whether the hard decision or the soft decision is made.

When the reliability information bit is at level 1, there is a possibility that the corresponding demodulated data is both 1 and 0. Therefore, at the time of soft decision, all the sets that can be taken as demodulated data are set. A combined demodulated data pattern is generated internally, and an error correction process is performed on all of these combined demodulated data patterns.
In the example shown in FIGS. 3A and 3C, of the 26-bit data,
Demodulated data 0 whose reliability information bit is 1 level exists at the 12th and 20th bits. Therefore, a possible bit pattern for these two bits is "0
0 ”,“ 10 ”,“ 01 ”, and“ 11 ”.
Accordingly, the demodulation data patterns of all combinations that are possible as demodulation data patterns are four patterns D1 to D4 shown in FIGS. Therefore, at the time of soft decision error correction, error correction is sequentially performed on these four patterns.

If the number of bits determined by the bit number determination circuit 8 is n, the number of all possible combinations is 2
, So that the number of times of processing in the error correction circuit 11 is also 2
N times. For this reason, the shift operations of the first and second shift registers 4 and 5 need to be repeated 2 n cycles, and the number of times is counted by the loop counter 21 in the error correction control circuit 7. The order counter 20 in the error correction control circuit 7 is a counter that counts the number of one-level reliability information bits appearing in one cycle, and the error correction control circuit 7 operates according to the contents of these two counters. To control the enable signal EN to the AND gate 9.

That is, the first time when the loop counter 21 becomes 0
In the cycle, when the twelfth bit of the reliability information bit 1 is output from the second shift register 5 by the shift operation of the shift registers 4 and 5, the content of the order counter 20 becomes 1, and the error correction control circuit 7 turns off the enable signal. The bull signal EN is set to the 0 level. Therefore, the passing of the reliability information bit 1 is blocked by the AND gate 9, and the output of the AND gate 9 is maintained at 0. The EXOR gate 10 outputs the demodulated data 0 from the first shift register 4 as it is. You. When the shift operation further proceeds and the 20th bit of the reliability information bit 1 is output from the second shift register 5, the order counter 20 counts up to 2, and at this time, the error correction control circuit 7 enables the error correction control circuit 7. The signal EN is set to the 0 level.
Therefore, as described above, the outputs of the AND gate 9 and the EXOR gate 10 become 0, and the demodulated data 0 from the first shift register 4 is output as it is. When the 0 level is output from the second shift register 5, the output of the AND gate 9 is always 0, so that the demodulated data output from the first shift register 4 is output from the EXOR gate 10 as it is. .

Therefore, in the first cycle of the shift operation, the data pattern D1 shown in FIG. 3D, which is exactly the same as the demodulated data, is input to the error correction circuit 11, and error correction processing is performed on this pattern. Next, in the second cycle of the shift operation, the content of the loop counter 21 is counted up to 1, and the 1st of the twelfth bit is output from the second shift register 5 and the order counter 20 becomes 1, and this time, The error correction control circuit 7 sets the enable signal EN to one level. Therefore, the output of the AND gate 9 becomes 1, and the demodulated data 0 output from the first shift register 4 is inverted by the EXOR gate 10 to become 1.
When the 1 of the 20th bit is output and the order counter 20 becomes 2, the error correction control circuit 7 sets the enable signal EN to 0.
The level, and thereby, the demodulated data 0 is output from the EXOR gate 10 as it is. Therefore, in the second cycle, the data pattern D2 shown in FIG.

In the third cycle, when the loop counter 21 becomes 2 and the sequence counter 20 becomes 1, the enable signal EN is set to the 0 level, and when the sequence counter 20 becomes 2, the enable signal EN becomes 2. -Set the bull signal EN to one level. Therefore, in this case, the EXOR gate 10 outputs the data pattern D3 shown in FIG. And
In the last fourth cycle, when the loop counter 21 becomes 3 and the order counter 20 becomes 1 and 2, the enable signal EN is set to 1 level at the same time.
The EXOR gate 10 outputs the data pattern D4 shown in FIG.

As described above, the four data patterns D1 to D4 are sequentially input to the error correction circuit 11, where the error correction processing is sequentially performed. When the error correction processing is successful, the correction OK / NG signal becomes 1, and when the error correction processing fails, the signal becomes 0. If only one of the plurality of data patterns is successfully corrected, the error correction result may be used as the final correction result. However, the correction may be successfully performed on the plurality of data patterns. Therefore, the following processing is further performed.

First, an error correction result, demodulated data from the first and second shift registers 4 and 5, and reliability information bits are input to the signal distance measurement circuit 12, and each bit is determined based on the rule shown in FIG. Then, the inter-signal distance between the error correction result and the demodulated data is calculated, and they are integrated for one block to measure the inter-signal distance for each data pattern. And AND
Only the inter-signal distance of the data pattern that has been successfully corrected is sent to the minimum value determination circuit 14 via the gate 13, where
The minimum value is determined by the method described above. The error correction control circuit 7 stores the value of the loop counter 21 corresponding to the data pattern in which the inter-signal distance has become the minimum, sets this value in the loop counter 21 again, and the inter-signal distance has become the minimum. The data pattern is generated again, and the error correction circuit 1
Output to 1. Then, the error correction result at this time is transmitted to the next stage as a final correction result.

In the example of FIG. 3, suppose that three data patterns D2 to D4 have been corrected successfully, and the error results are DC1, DC2, and DC3 shown in FIGS. The distance between the signals is measured based on FIG.
It becomes 0. Therefore, in this case, the minimum value is determined to be 9 by the minimum value determination circuit 14, and the error correction result DC2 of the corresponding data pattern D3 is adopted as the final correction result.

In the above embodiment, the error correction is performed twice for the data pattern with the minimum distance between signals. However, the error correction result for each data pattern is stored in a buffer memory or the like at the time of the correction processing. In advance, the error correction result of the data pattern with the minimum inter-signal distance may be read from this buffer memory.
Alternatively, in the determination of the minimum value, the error correction result of the buffer memory is rewritten only when it is determined that the correction value is smaller than the distance between the signals already stored, and the correction result remaining in the buffer memory is finally determined. It may be adopted as a final result.

When the minimum value determination circuit 14 determines that the inter-signal distances of all data patterns are greater than the reference value M, the initial value remains as the minimum value. In such a case, the error correction control circuit 7 outputs an error correction NG signal indicating that the error correction processing has not succeeded to the next stage, whereby the output error correction result is output to the next stage circuit. Avoid using.

Next, the hard decision error correction executed when the bit number n determined by the bit number determination circuit 8 exceeds the reference value N will be described below. The fact that the number of bits n exceeds the reference value indicates that the demodulated data is in an extremely uncertain state. In such a situation, if soft-decision error correction using the reliability information bit is executed, the possibility of erroneous correction being successful increases, and the number of erroneous corrections increases. Therefore, in this embodiment,
In such a case, the following hard decision error correction is performed.

That is, in this hard decision, since the error correction control circuit 7 always outputs the enable signal EN of 0 level, the output of the AND gate 9 is always 0, and the EXO
In the R gate 10, the output of the first shift register 4 passes as it is. Therefore, at the time of this determination, only the demodulated data output from the demodulation circuit 1
1 and no other demodulated data pattern is generated. Then, the error correction result is sent to the next stage as a final result.

[0032]

According to the present invention, error correction can be performed even on data that exceeds the correction capability of the error correction circuit, and occurrence of erroneous correction can be suppressed as much as possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining an operation of a demodulation circuit in the embodiment.

FIG. 3 is an explanatory diagram showing various data patterns in the embodiment.

FIG. 4 is a diagram showing a rule for measuring a distance between signals in the embodiment.

[Explanation of symbols]

 Reference Signs List 1 demodulation circuit 2, 3 switch 4 first shift register 5 second shift register 7 error correction control circuit 8 bit number determination circuit 9, 13 AND gate 10 EXOR gate 11 error correction circuit 12 signal distance measurement circuit 14 minimum value determination circuit 20 Order counter 21 Loop counter 22 Identification circuit

──────────────────────────────────────────────────続 き Continued on the front page (72) Hiroshi Kaneko 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-63-13444 (JP, A) Hei 8-330980 (JP, A) JP-A-62-277824 (JP, A) JP-A-62-146033 (JP, A) JP-A-62-136939 (JP, A) US Patent 4,763,331 (US, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 13/00 H04L 27/00

Claims (5)

(57) [Claims] A demodulation circuit for demodulating an input signal and outputting a demodulated data pattern, and outputting a reliability information bit indicating the reliability of each demodulated data of the demodulated data pattern in correspondence with the demodulated data; A generation circuit for generating demodulation data patterns of all possible combinations of demodulation data patterns by manipulating demodulation data whose reliability information bits are at a predetermined level; and a demodulation data pattern of all the generated combinations. And an error correction circuit for performing error correction on the reliability information bits of the predetermined level.
And corresponding to the predetermined level of reliability information bits
Of all possible combinations of demodulated data
An error correction control circuit for sequentially outputting bit data,
A predetermined level of reliability information bit in the demodulated data pattern
The demodulated data corresponding to the bit
Demodulation of all the above combinations
A logic circuit for sequentially outputting a data pattern;
Data pattern and reliability information bits
And second shift registers for performing a shift operation in synchronization with
And the reliability information captured in the second shift register.
Bits of the reliability information bits of a predetermined level among the report bits
A bit number determination circuit for determining the number n,
The positive control circuit is configured so that the first and second shift registers are in a row.
Of the 2nd nth cycle shift operation
A first counter for counting whether the operation is a shift operation,
The signal of the predetermined level appearing during the shift operation of one cycle.
Second count for counting the number of appearances of the reliability information bit
And inputs the predetermined level of reliability information bits.
Then, according to the contents of the first and second counters,
Demodulated data corresponding to a predetermined level of reliability information bits
Bit data of all possible combinations
The logic circuit sequentially outputs the data every cycle.
Each cycle corresponds to a predetermined level of reliability information bits.
Demodulated data to the sequentially output bit data
The demodulated data patterns of all the combinations in order.
Next, an error correction is output to the error correction circuit.
Positive device. 2. An error correction circuit according to claim 1, wherein
As a result, at least the demodulated data pattern
To measure the distance between the signal between the error correction result and the demodulated data.
Signal distance measuring circuit, and the signal distance measuring circuit
Is the measurement result for a demodulated data pattern that has been corrected successfully?
The minimum value determination circuit that determines the minimum value of the distance between signals
Having the signal-to-signal distance determined to be the minimum value
Final error correction of error correction result of demodulated data pattern
2. The error according to claim 1, wherein the error is output as a result.
Correction device. 3. The minimum value judging circuit according to claim 1 , wherein
A judgment circuit for judging whether the minimum value is larger than a predetermined value is provided.
Having a control signal when the minimum value is greater than a predetermined value.
3. The error correcting device according to claim 2, wherein the error is output.
Place. 4. The signal distance measurement circuit according to claim 1 , wherein
Result and demodulated data from demodulation circuit and reliability information bit
Measuring the distance between signals based on
Item 3. The error correction device according to Item 3. 5. The input signal may be an RDS broadcast signal or
Is an FM multiplex broadcast signal.
Error correction device according to the fourth to fourth aspects.