JPH0537515A - Synchronous circuit - Google Patents

Synchronous circuit

Info

Publication number
JPH0537515A
JPH0537515A JP3190475A JP19047591A JPH0537515A JP H0537515 A JPH0537515 A JP H0537515A JP 3190475 A JP3190475 A JP 3190475A JP 19047591 A JP19047591 A JP 19047591A JP H0537515 A JPH0537515 A JP H0537515A
Authority
JP
Japan
Prior art keywords
synchronization
circuit
information
timing signal
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3190475A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yasui
宏幸 安井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3190475A priority Critical patent/JPH0537515A/en
Publication of JPH0537515A publication Critical patent/JPH0537515A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain optimum synchronization control by detecting quickly the state of pseudo synchronization. CONSTITUTION:A synchronization pulling-in circuit 102 outputs 1st information (a) resulting from retrieving a synchronization bit inserted into an input signal 101 by using the 1st timing signal of a timing signal generating circuit 103. A backward protective circuit 104 outputs synchronization information (b) when the synchronization bit is at the same position consecutively for the prescribed number of times cosnecutively based on the 1st information (a). A sub synchronization pulling-in circuit 107 outputs it as 2nd information (c) when other synchronization bit is retrieved in the input signal 101 based on the synchronization information (a) and the 2nd timing signal. A decision circuit 111 compares the number of errors detected from the 1st and 2nd pieces of information by error checking circuits 106, 110 and outputs a control instruction (d) when the synchronization pulling-in circuit 102 making the decision is in the pseudo synchronization state. A control circuit 112 controls the phase of the 1st timing signal based on the control instruction (d).

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は伝送通信における同期回
路に関し、特に擬似同期の防止回路を有する同期回路に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit in transmission communication, and more particularly to a synchronizing circuit having a pseudo sync preventing circuit.

【0002】[0002]

【従来の技術】従来、この種の擬似同期防止回路を含ん
だ同期回路は、伝送路エラー検出回路の出力をトリガー
にして同期をはずし、再ハンチング(同期調整)を行う
か、伝送路エラー検出回路の出力で副同期回路を動作さ
せ副同期回路が同期をつかまえたところを新たな同期位
置とする処理を行っていた。
2. Description of the Related Art Conventionally, a synchronous circuit including a pseudo-synchronization prevention circuit of this type uses the output of a transmission line error detection circuit as a trigger to remove synchronization and perform re-hunting (synchronization adjustment) or transmission line error detection. The sub-synchronization circuit is operated by the output of the circuit, and the process where the sub-synchronization circuit catches the synchronization is set as a new synchronization position.

【0003】[0003]

【発明が解決しようとする課題】上述した従来の同期回
路では伝送路エラーをトリガとし擬似同期の検出を行っ
ており、実際の伝送路のエラーと擬似同期とにより2次
的に表われたエラーの区別がつかない。そこで擬似同期
の検出確率を上げる為、低いエラーレートで同期ビット
の再ハンティングを行う様にすると実際の伝送路エラー
で同期がはずれるという問題がおこり、その保護の為に
エラー監視の時間を伸ばすと逆になかなか擬似同期から
抜けられなくなるという問題点があった。
In the above-mentioned conventional synchronous circuit, the transmission line error is used as a trigger to detect the pseudo synchronization, and an error secondary to the actual transmission line error and the pseudo synchronization is detected. Cannot be distinguished. Therefore, in order to increase the detection probability of pseudo synchronization, if the synchronization bit is re-hunted at a low error rate, there will be a problem that synchronization will be lost due to an actual transmission line error, and if the error monitoring time is extended to protect it, On the contrary, there was a problem that it was difficult to get out of pseudo synchronization.

【0004】[0004]

【課題を解決するための手段】本発明の同期回路は、入
力信号に挿入されている同期ビットを第1のタイミング
信号により検索し第1の情報として出力する同期引き込
み回路と、前記第1の情報により前記同期ビットが所定
回数連続して同じ位置にあるとき同期情報を出力する後
方保護回路と、前記同期情報と第2のタイミング信号に
より前記入力信号の中に他の前記ビットを検索したとき
第2の情報として出力する副同期引き込み回路と、前記
第1と第2の情報から検出された誤りの数を比較し前記
同期引き込み回路が擬似同期状態にあるとき制御命令を
出力する判定回路と、前記制御命令により前記第1のタ
イミング信号を前記第2のタイミング信号の位相に制御
する制御回路とを有する。
A synchronizing circuit according to the present invention includes a sync pull-in circuit for searching a sync bit inserted in an input signal by a first timing signal and outputting the sync bit as first information. A backward protection circuit that outputs synchronization information when the synchronization bit is continuously at the same position for a predetermined number of times according to information, and when the other bit is searched for in the input signal by the synchronization information and a second timing signal. A sub-sync pull-in circuit that outputs as second information, and a determination circuit that compares the number of errors detected from the first and second information and outputs a control command when the sync-pull-in circuit is in a pseudo sync state. And a control circuit that controls the first timing signal to have a phase of the second timing signal according to the control command.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例のブロック図である。
The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

【0006】同期引き込み回路102は入力信号101
の中に周期的に挿入されている同期ビットをタイミング
信号発生回路103から与えられるタイミング信号に従
い検索し、その結果の第1の情報aを出力する。
The sync pull-in circuit 102 receives the input signal 101.
The synchronization bits periodically inserted in the search signal are searched according to the timing signal supplied from the timing signal generation circuit 103, and the first information a as the result is output.

【0007】後方保護回路104は第1の情報aにより
入力信号101中の同期ビットが所定の回数以上連続し
て同じ位置にあることを確認し同期情報bを出力する。
The rear protection circuit 104 confirms that the synchronization bit in the input signal 101 is at the same position for a predetermined number of times or more by the first information a and outputs the synchronization information b.

【0008】副同期引き込み回路107は同期情報bに
より入力信号101中の他に同期ビットの候補がないか
を同期引き込み回路102がつかまえた同期ビットの次
の位置から副タイミング信号発生回路108から与えら
れるタイミング信号に従い検索し、その結果の第2の情
報cを出力する。判定回路111は、副同期引き込み回
路107が新たに同期ビットの候補を見つけ副後方保護
回路109で同期ビットの条件を満たすことが確認さ
れ、かつ同期引き込み回路102でつかまえている同期
ビットと異なる場合にはエラー検出回路106と副エラ
ー検出回路110とで計算したエラーの数を比較する。
The sub-synchronization pull-in circuit 107 gives from the sub-timing signal generation circuit 108 from the position next to the sync bit caught by the sync pull-in circuit 102 whether there is any other sync bit candidate in the input signal 101 according to the sync information b. The search is performed in accordance with the received timing signal, and the second information c as a result is output. The determination circuit 111 finds that the sub-sync pull-in circuit 107 has newly found a sync-bit candidate and that the sub-back protection circuit 109 has confirmed that the condition of the sync bit is satisfied, and is different from the sync bit caught by the sync pull-in circuit 102. For comparison, the numbers of errors calculated by the error detection circuit 106 and the sub error detection circuit 110 are compared.

【0009】また、判定回路111はふたつのエラー検
出回路の比較結果でエラー検出回路106の方にエラー
が多い場合には同期引き込み回路102は擬似同期状態
にあると判断し、制御回路112に対して制御命令dを
出力する。制御回路112は制御命令dに従い副タイミ
ング信号発生回路108のカウンタ値eをタイミング信
号発生回路103経由で転送し、同期引き込み回路10
2では副同期引き込み回路107がつかまえている同期
ビットを新たな同期位置とするように制御を行う。この
とき、前方保護回路105の計数は進まないので、同期
はずれがなく、新たな同期位置に移る。
Further, the judging circuit 111 judges that the sync pull-in circuit 102 is in the pseudo-synchronous state when the error detecting circuit 106 has more errors based on the comparison result of the two error detecting circuits. To output the control command d. The control circuit 112 transfers the counter value e of the sub timing signal generation circuit 108 via the timing signal generation circuit 103 in accordance with the control instruction d, and the synchronization pull-in circuit 10
In 2, the control is performed so that the sync bit caught by the sub sync pull-in circuit 107 becomes a new sync position. At this time, since the count of the front protection circuit 105 does not proceed, the synchronization is not lost, and the process moves to a new synchronization position.

【0010】また、副エラー検出回路110の方にエラ
ーが多い場合には判定回路111は副同期引き込み回路
107に制御をかけ現在つかまえている同期ビットの次
の位置から再度同期ビットの検索を行う。
If there are more errors in the sub-error detection circuit 110, the decision circuit 111 controls the sub-sync pull-in circuit 107 to search for the sync bit again from the position next to the sync bit currently caught. .

【0011】[0011]

【発明の効果】以上説明したように本発明は、副同期回
路が伝送路のエラーに関係なく起動されることにより、
擬似同期の状態を迅速に検出することができる。また擬
似同期の判定を2つのエラー検出回路の比較で判定の基
準に重みづけを行うことにより、伝送路エラーの劣化に
よる同期調整を最適に制御することができる。
As described above, according to the present invention, the sub-synchronization circuit is activated regardless of the error in the transmission line.
The state of pseudo synchronization can be detected quickly. Further, by weighting the determination of pseudo-synchronization based on the determination by comparing two error detection circuits, it is possible to optimally control the synchronization adjustment due to the deterioration of the transmission path error.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

101 入力信号 102 同期引き込み回路 103 タイミング信号発生回路 104 後方保護回路 105 前方保護回路 106 エラー検出回路 107 副同期引き込み回路 108 副タイミング信号発生回路 109 副後方保護回路 110 副エラー検出回路 111 判定回路 112 制御回路 101 Input signal 102 Sync pull-in circuit 103 Timing signal generating circuit 104 Back protection circuit 105 Front protection circuit 106 Error detection circuit 107 Sub sync pull-in circuit 108 Sub timing signal generation circuit 109 Sub back protection circuit 110 Sub error detection circuit 111 Judgment circuit 112 Control circuit

Claims (1)

【特許請求の範囲】 【請求項1】 入力信号に挿入されている同期ビットを
第1のタイミング信号により検索し第1の情報として出
力する同期引き込み回路と、前記第1の情報により前記
同期ビットが所定回数連続して同じ位置にあるとき同期
情報を出力する後方保護回路と、前記同期情報と第2の
タイミング信号により前記入力信号の中に他の前記同期
ビットを検索したとき第2の情報として出力する副同期
引き込み回路と、前記第1と第2の情報から検出された
誤りの数を比較し前記同期引き込み回路が擬似同期状態
にあるとき制御命令を出力する判定回路と、前記制御命
令により前記第1のタイミング信号を前記第2のタイミ
ング信号の位相に制御する制御回路とを有することを特
徴とする同期回路。
Claim: What is claimed is: 1. A synchronization pull-in circuit for searching a synchronization bit inserted in an input signal with a first timing signal and outputting it as first information, and the synchronization bit with the first information. A rear protection circuit that outputs synchronization information when the same position is continuously present a predetermined number of times, and second information when the other synchronization bit is searched for in the input signal by the synchronization information and the second timing signal. A sub-synchronization pull-in circuit that outputs the control instruction and a determination circuit that compares the number of errors detected from the first and second information and outputs a control instruction when the synchronization pull-in circuit is in a pseudo-synchronous state. And a control circuit for controlling the first timing signal to the phase of the second timing signal according to the above.
JP3190475A 1991-07-31 1991-07-31 Synchronous circuit Pending JPH0537515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3190475A JPH0537515A (en) 1991-07-31 1991-07-31 Synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3190475A JPH0537515A (en) 1991-07-31 1991-07-31 Synchronous circuit

Publications (1)

Publication Number Publication Date
JPH0537515A true JPH0537515A (en) 1993-02-12

Family

ID=16258732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3190475A Pending JPH0537515A (en) 1991-07-31 1991-07-31 Synchronous circuit

Country Status (1)

Country Link
JP (1) JPH0537515A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6865240B1 (en) 1999-09-20 2005-03-08 Fujitsu Limited Frame synchronizing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6865240B1 (en) 1999-09-20 2005-03-08 Fujitsu Limited Frame synchronizing circuit

Similar Documents

Publication Publication Date Title
US4541104A (en) Framing circuit for digital system
US5018140A (en) Reframe circuit in a synchronous multiplexing device
US6266349B1 (en) Method and apparatus for detecting frame in data stream
JP2861932B2 (en) Burst frame phase synchronization circuit
JPH0537515A (en) Synchronous circuit
JPH0634298B2 (en) Address circuit
US5588030A (en) Apparatus and method for the synchronization of data in a bit stream
JP2944319B2 (en) Parallel deployment type frame synchronization method
JPS6178239A (en) Frame synchronizing circuit
US6163423A (en) Synchronizing signal detector for magnetic recording/reproducing apparatus and synchronizing signal detecting method thereof
JPH05114898A (en) Frame synchronizing circuit for digital transmission system
JP3565206B2 (en) Transmission data frame synchronization circuit and transmission data frame synchronization method
KR100235332B1 (en) Synchronous signal detecting device
JPH07235920A (en) Frame synchronizing circuit
JPH06152582A (en) Synchronizing protection circuit
JP2576273B2 (en) Synchronous protection circuit
JPH04297153A (en) Frame synchronizing protection circuit
JP2601172B2 (en) Clock signal surplus pulse detection circuit
JPH05316095A (en) Frame synchronization circuit
JPH08242392A (en) Synchronous processing circuit
JPS60160778A (en) Synchronizing signal protecting method
JPS59161144A (en) Frame synchronizing circuit
JPH08212705A (en) Synchronizing circuit
JPH0983503A (en) Frame synchronizing device
JPH03261234A (en) Frame synchronizing method, frame synchronizing circuit and multiplex converter