JPH04365239A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain the frame synchronizing circuit which can detect a frame pattern and can lock a phase after serial/parallel conversion. CONSTITUTION:This circuit is equipped with a serial/parallel conversion part 2 connected to a data input part, delay part 3, parallel frame pattern detection part 4 to detect the frame pattern of parallel data and channel selection part 5, and parallel received data outputted from the serial/parallel conversion part 2 are delayed for the required number of clocks by the delay part 3. The plural channels of different phases are generated, the frame patterns are parallelly detected at the same time for the respective plural channels, and the frame synchronizing circuit selects the channel with the successful frame pattern detection.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit used in a receiving section of a digital time division multiplex transmission apparatus.

0002

2. Description of the Related Art FIG. 2 shows the configuration of a conventional frame synchronization circuit. In FIG. 2, 8 is a data input terminal to which received data is input. Reference numeral 9 denotes a phase shift circuit to which input data is sent and whose phase is shifted, and is composed of flip-flops that can control a clock. 10
11 is a serial/parallel conversion circuit that rearranges serial data into a parallel structure, and 11 is a frame pattern detection and synchronization protection circuit that performs frame pattern detection and synchronization protection processing. 12 is a data output terminal to which frame-synchronized data is output.

The operation of the frame synchronization circuit configured as described above will be explained below. First, when the frame pattern detection unit of the frame pattern detection and synchronization protection circuit 11 detects the frame pattern itself, frame synchronization is performed as is. On the other hand, when the frame pattern detection section detects a bit-shifted pattern of the frame pattern, it issues a phase shift instruction to the phase shift circuit 9. Then, the phase shift circuit 9 shifts the phase by 1 bit. This process is repeated until the frame pattern detection and synchronization protection circuit 11 detects a correct frame pattern. In this manner, in the conventional frame synchronization circuit described above, frame synchronization can be established by repeating the phase shift operation.

0004

However, the conventional frame synchronization circuit described above has a problem in that it requires a logic circuit that operates at high speed because it is configured to perform phase shifting in series stages.

SUMMARY OF THE INVENTION The present invention is intended to solve these conventional problems, and aims to provide an excellent frame synchronization circuit that can detect frame patterns and perform phase synchronization after serial-to-parallel conversion.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a serial-to-parallel conversion section, a delay section, a parallel frame pattern detection section, and a channel selection section, and outputs an output from the serial-to-parallel conversion section. By delaying the parallelized received data by the required number of clocks in the delay unit, generating multiple channels with different phases, simultaneously detecting parallel frame patterns on each channel, and selecting the channel for which the frame pattern has been successfully detected. All operations related to frame synchronization are performed after serial-to-parallel conversion.

[0007]

[Operation] Therefore, according to the present invention, by performing frame pattern detection and phase synchronization in the parallel stages in the receiving section of the digital time division transmission device, a frame synchronization circuit is implemented using a low-speed logic circuit that operates at the speed of the parallel stages. This contributes to ease of circuit configuration and cost reduction.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the structure of an embodiment of the present invention. In FIG. 1, 1 is a data input terminal to which received data is input. Reference numeral 2 denotes a serial-to-parallel conversion unit that rearranges serial data into a parallel structure, and can be configured by a shift register or the like. 3 is a delay section, which is composed of a D flip-flop. Reference numeral 4 denotes a parallel frame pattern detection section, which is composed of logic gates corresponding to frame synchronization patterns. Reference numeral 5 denotes a channel selection section, which is composed of an exclusive control section 5a for instructing channel selection and a channel selection logic gate 5b. Reference numeral 6 denotes a synchronization protection section, which is composed of a contention counter and the like. 7
is a data output terminal to which data decomposed into each channel and frame-synchronized is output.

Next, the operation of the frame synchronization circuit having such a configuration will be explained. In this embodiment, serially structured received data inputted from a data input terminal 1 is parallelized in a serial-to-parallel converter 2. All data processing from here on is performed at parallel stage speed. The parallelized data is delayed by the required number of clocks according to the frame pattern length in the delay unit 3, and a plurality of data channels having different phases are generated. A parallel frame pattern detection section 4 simultaneously performs frame pattern detection on the data of each phase, and the channel selection section 5 selects the phase channel for which pattern detection was successful first.
Output from Channel selection is valid while frame synchronization is protected by the synchronization protector 6.

Therefore, according to this embodiment, frame pattern detection and phase synchronization can be performed after serial-to-parallel conversion of received data, and all processing can be performed by a low-speed logic circuit.

[0011]

[Effects of the Invention] As explained above, according to the present invention,
By performing frame pattern detection and phase synchronization in parallel stages in the receiving section of the digital time division transmission device, the frame synchronization circuit can be configured with a low-speed logic circuit that operates at the speed of the parallel stages. This has the effect of contributing to ease of circuit configuration and cost reduction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a frame synchronization circuit in an embodiment of the present invention.

[Figure 2] Schematic block diagram of a conventional frame synchronization circuit

[Explanation of symbols]

1 Data input terminal 2 Serial-to-parallel converter 3 Delay section 4 Parallel frame pattern detection section 5 Channel selection section 6 Synchronization protection section 7 Data output terminal

Claims (1)

[Claims] 1. A serial-to-parallel converter connected to a data input section of a digital time division multiplex transmission device, a delay section, a frame pattern detection section for detecting a frame pattern of parallel data, and a channel selection section, The parallelized received data output from the serial-to-parallel converter is delayed by the required number of clocks in the delay unit to generate multiple channels with different phases, and parallel frame pattern detection is performed simultaneously on each of the multiple channels to determine the frame pattern. A frame synchronization circuit characterized in that all operations related to frame synchronization are performed after serial-to-parallel conversion by selecting a successfully detected channel.