JPH07226731A - Coincidence detection output circuit for multi-frame data - Google Patents

Abstract

PURPOSE:To provide a coincidence detection output circuit for multi-frame data whose processing time is short without the need for data transfer with respect to the coincidence detection output circuit for multi-frame data outputting an output of the multi-frame data when same multi-frame data are consecutive for n-times in the case of reception of the multi-frame data of multi-frame configuration where m-frame is equal to 1 multi-frame. CONSTITUTION:RAMs are formed to be of double buffer configuration and both RAMs 1, 2 are used to detect the coincidence of multi-frame data where m-frames are equal to 1 multi-frame simultaneously over all frames, a data mis-match detection circuit 5 always monitors outputs of m-frame coincidence detection circuits 3, 4 to compare data coincidenct consecutively for n-times in the unit of multi-frames with data coincident consecutively for n-times newly thereby detecting dissidence thereby outputting multi-frame data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-frame data coincidence detection output circuit for outputting multi-frame data when the same multi-frame data is input n times when data of m frame = 1 multi-frame structure is input. Regarding improvement.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram of a conventional multi-frame data coincidence detection output circuit, and FIG. 14 is a time chart of each part of FIG. 13. Input data is multi-frame data A, B, and C, respectively. When the same multi-frame data is input three times consecutively and the same multi-frame data is input three times, the multi-frame data A, B and C are output from the output, and three consecutive multi-frame data and the next three consecutive multi-frame data are output. Is a case where the data mismatch information is output.

When the data shown in the RAM write data of FIG. 14 and the write signal shown in the WE signal are input to the RAM1 and written in the RAM1, the output of the RAM1 is as shown in FIG.
The data will be as shown in the output of RAM1.

In the m-frame match detection circuit 3, the RAM 1
The multi-frame data to be written to and the multi-frame data output from the RAM 1 are compared for each frame, and if all the frames match, a match detection pulse as shown in the m-frame match detection circuit output pulse in FIG. 14 is output. , N
It is input to the continuous hit detection circuit 30.

The n-th consecutive coincidence detection circuit 30 counts the coincidence detection pulses, and if the count value is 2 as shown in the output value of the n-th consecutive coincidence detection circuit in FIG. 14, it is assumed that the same multi-frame data is input three consecutive times. Write control circuit 31
To send a write signal to the RAM shown in FIG.
One multi-frame data is written in the RAM 32 as shown by 32 write data.

In the match comparison circuit 33, the data written in the RAM 32 and the read data shown in the output of the RAM 32 of FIG. 14 are compared, and if they do not match, an H level signal is output as shown in the output of the match comparison 33 of FIG. Output, and output nothing if they match.

A RAM shown in the RAM 32 output of FIG.
The read data from 32 is output as an output.

[0008]

However, in the conventional multiframe data coincidence detection output circuit, a RAM is used.
The data must be transferred to the RAM 32 from 1, and there is a problem in that it takes time to transfer and the processing time becomes long particularly when the number of frames is large, and the address of each frame of the multi-frame to be written in the RAM 32 is When it is not constant and changes in the middle, there is a problem that control is difficult for comparison.

An object of the present invention is to provide a coincidence detection output circuit for multi-frame data which does not require data transfer and has a short processing time.

[0010]

FIG. 1 is a block diagram of a multiframe data coincidence detection output circuit according to an embodiment of the present invention, and FIG. 3 is a multiframe data coincidence detection output circuit according to another embodiment of the present invention. It is a block diagram.

As shown in FIG. 1, the first and second RAMs 1 and 2 for writing the input data in units of one multiframe by the write signals switched by the write signal switching unit 7.
And the 1-multiframe data written in the first or second RAM and the 1-multiframe input data to be input next are compared for each frame, and when all the frames match, a match signal To output the first and second m frame coincidence detection circuits 3 and 4 and the outputs of the first and second m frame coincidence detection circuits 3 and 4, and to input the same multi-frame data n times consecutively. Is detected, and if the data that has been detected n times in succession in multiframe units the previous time is not the same as the data that has been detected n times in succession in the next multiframe units, a data mismatch is detected. When the data mismatch detection circuit 5 outputs the mismatch information and inputs it to the switching signal output section 6 and the data mismatch information, the write signal switching section 7 and the selector 8
The switching signal output unit 6 for sending a switching signal to the
Outputs of the first and second RAMs 1 and 2 input to the second m-frame coincidence detection circuits 3 and 4 are input and switched by a switching signal of the output of the switching signal output unit 6, and either input is output. The selector 8 and the write signal switching unit 7 that switches the write signal to the write signal to the first or second RAM according to the switching signal of the output of the switching signal output unit 6.

Alternatively, as shown in FIG. 3, the first and second m
When the frame matching detection circuits 3 and 4 compare the data of one multi-frame written in the first or second RAM with the data of one multi-frame to be input next for each frame, they are compared. A mask circuit 9 is provided on the output side of the write signal switching section 7 so as not to write the frame data to the first or second RAM when the frame data match.

[0013]

According to the present invention, when the same multi-frame data input n times in succession and the same multi-frame data input next n times are different, the input data is switched to the write signal. With the write signal switched by the unit 7, the first or second RAM is set in units of one multiframe.
1 and 2 data written in the first and second m-frame coincidence detection circuits 3 and 4 and 1 multiframe data written in the first or second RAM 1 or 2 and the input data to be input next. 1 multi-frame data is compared for each frame, and when all the frames match, a match signal is output to the data mismatch detection circuit 5.

In the data mismatch detection circuit 5,
The output of the second m-frame coincidence detection circuits 3 and 4 detects that the same multi-frame data has been received n times in succession, and the data obtained by performing the previous n-time continuous coincidence detection in multi-frame units. If the data that has been subjected to the next n-time continuous match detection in units of multiframes is not the same, a data mismatch is detected and the data mismatch information is output and also input to the switching signal output unit 6.

Then, the switching signal output unit 6 sends the switching signal to the write signal switching unit 7, and the first or second RAM.
The writing of the input data in units of 1 multiframe to 1 and 2 is switched.

Further, the switching signal is sent to the first and second RAMs.
The outputs of 1 and 2 are also sent to the selector 8 which is input, and the output is switched to the output of the first or second RAM. In this way, data transfer between RAMs is eliminated, the processing time is shortened, and complicated control is not required to obtain the mismatch information.

As shown in FIG. 3, a mask circuit 9 is provided next to the write signal switching unit 7 of the multi-frame data coincidence detection output circuit shown in FIG. 1, and the first and second m-frame coincidence detection circuits 3 are provided. , 4, when comparing the multi-frame data written in the first or the second RAM with the multi-frame data to be input next for each frame, the frame data to be compared are the same. In this case, even if the frame data is not written to the first or second RAM, the comparing operation does not change and the writing operation is reduced. Therefore, in addition to the effect in the case of FIG. ,
The power consumption can be reduced accordingly.

[0018]

1 is a block diagram of a coincidence detection output circuit for multi-frame data according to an embodiment of the present invention, FIG. 2 is a time chart of each portion of FIG. 1, and FIG. 3 is multi-frame data according to another embodiment of the present invention. Block diagram of the match detection output circuit of FIG.
Is a time chart of the operation of the m-frame match detection circuit and the mask circuit of FIG. 3, FIG. 5 is a block diagram of the data mismatch detection circuit of the embodiment of the present invention, and FIG. 6 is the decoder A of FIG.
State transition diagram of ^{i + 1} , B ^{i + 1} , FIG. 7 shows m of the embodiment of the present invention.
8 is a block diagram of the frame match detection circuit, FIG. 8 is a time chart of each part of FIG. 7, FIG. 9 is a block diagram of an m frame match detection circuit of another embodiment of the present invention, and FIG. 10 is a time chart of each part of FIG. FIG. 11 is a block diagram from the sync detection protection to the coincidence detection output circuit of multi-frame data according to the embodiment of the present invention, and FIG. 12 is a time chart of each part of FIG.

As in the case of FIG. 13, up to FIG. 10, the input data is the multi-frame data A, B and C which are continuously input three times respectively, and when the same multi-frame data is input three times, the multi-frame data is output from the output. An example will be described in which data mismatch information is output when A, B, and C are output, and when three consecutive multiframe data do not match the next three consecutive multiframe data.

When the input data shown in the RAM write data in FIG. 2 and the write signal shown in the WE signal in FIG. 1 are input,
The input data is input to the m frame coincidence detection circuits 3 and 4,
When the same multi-frame data input three times in succession and the same multi-frame data input three times in succession are different, switching is performed by the write signal switching unit 7, R in FIG.
The write signal shown by the AMWE signal and the RAMWE signal is used to write the data shown in FIG.

Then, the output data of the RAMs 1 and 2 become the data shown in the RAM output and the RAM output of FIG. 2, and are input to the m frame coincidence detection circuits 3 and 4, respectively. The m-frame coincidence detection circuits 3 and 4 compare both inputs, and if all the frames coincide, the m-frame coincidence detection output pulse and the m-frame coincidence detection output pulse shown in FIG. 2 are output, and the data mismatch detection circuit. Enter in 5.

In the data mismatch detection circuit 5, the RAM is
If it is written in 1, the m-frame match detection circuit 3
When the output of is selected and written in RAM2, m
When the output of the frame coincidence detection circuit 4 is selected and both of the m frame coincidence detection circuits 3 and 4 are outputting, the coincidence detection pulse is not output. Therefore, the number of coincidence detections is n in FIG.
As shown in the continuous consecutive detection, as the data mismatch information, the information as shown in the data mismatch detection in FIG. 2 is output and also input to the switching signal output unit 6.

The switching signal output unit 6 outputs a pulse as shown in the switching output of FIG. 2 and sends it to the AND circuits 10 and 11 of the selector 8 and the writing signal switching unit 7 to write signals to the RAMs 1 and 2. 2 RAMWE signal, RAMW
As indicated by the E signal.

The read data of the RAMs 1 and 2 is input to the selector 8, the selection is switched by the output of the switching signal output unit 6, and the multi-frame data as shown in the RAM read data of FIG. 2 is output.

In this way, data transfer between RAMs is eliminated, the processing time is shortened, and complicated control is not required to obtain the mismatch information. Since the mask circuit 9 including AND circuits 12 and 13 is added to the circuit of FIG. 1 in FIG. 3, the effect of using the mask circuit 9 will be described with reference to FIG.

The frame data shown in the RAM write data of FIG. 4 is replaced with the address shown in the RAM write address of FIG.
When the data shown in the RAM read data written and read by the signal shown in the RAMWE signal in FIG. 4 is compared with the input data and if they do not match, the same data is read out. At this time, m The pulse shown in the frame match detection result of FIG. 4 which is issued by the frame match detection circuits 3 and 4 is input to the AND circuit 12 or 13, and R of FIG.
Masking is performed as shown by the AMWE signal so that writing is not performed.

Of course, when the input data and the read data from the RAMs 1 and 2 do not match, a write signal is output and written as shown by the RAMWE signal in FIG. By doing so, the comparison operation does not change, and the number of write operations is reduced. Therefore, in addition to the effect of FIG. 1, the power consumption can be further reduced by this amount.

Next, the operation of the data mismatch detection circuit will be described with reference to FIGS. Both the match detection output pulses of the m-frame match detection circuits 3 and 4 are monitored, and when the switching signal shown in the switching output of FIG.
At 3, the output of the m-frame coincidence detection circuit 3 is selected and three consecutive coincidence detections are performed. When the output is at H level, the output of the m-frame coincidence detection circuit 4 is selected and three consecutive coincidence detections are performed.

However, when the output pulses are output from the m-frame coincidence detection circuits 3 and 4, it is going to detect the data for which three consecutive coincidences are detected in multiframe units and the next three consecutive coincidence detections in multiframe units. Since the data is the same, the AND circuits 21 and 22 mask the data so that it is not included in the three consecutive coincidence detection operation.

By doing so, when three consecutive coincidence detections are performed, the data for which three consecutive consecutive coincidence detections are performed for each multi-frame unit and the next three consecutive consecutive coincidence detections for one multi-frame unit are performed. Data can be defined as a data mismatch, and a data mismatch can be detected.

Next, the operation of the decoders A ^{i + 1} , B ^{i + 1} and the FFs 26, 27 in the case of performing continuous coincidence detection three times will be described with reference to FIG. 6A is a state transition diagram at points A and B in FIG. 5, and FIG. 6B is a diagram showing transitions according to conditions. The state at points A and B in FIG. As shown in (B) of 6, 0,0,0,1,1,0,1,1 [however, 0 of A
Indicates that there is no multi-frame phase comparison pulse, 1 indicates that there is a multi-frame phase comparison pulse, 0 of B indicates that there is no match detection pulse, and 1 indicates that there is a match detection pulse.
For each state of A and B, the multi-frame phase comparison pulse and the coincidence detection pulse are 0, 0, 0, 1, 1, 0, 1, 1
(0 means no pulse, 1 means pulse).

When the above conditions are satisfied in each of the states A and B, the states of the next decoders A ^{i + 1} and B ^{i + 1} are as shown in the next state of FIG. 6B. At first, as shown at 0 times in FIG. 6A, both A and B are 0, 0, but when 0, 1, 1, 0 do not transition, 1, 1 (with multi-frame phase comparison pulse) , There is a coincidence detection pulse), the state transits to once and becomes (0, 1), indicating multiframe data coincidence.
Here, when the condition is 0 or X, no transition occurs, and when the condition is 1,0, the condition returns to 0 times, and when the condition becomes 1,1, the condition transits to 2 times (1,0) and 3 multiframes. Indicates continuous data matching.

Here, since three consecutive matches have been detected, when the condition is 1, X, the transition is made to 0 times. In this way, continuous agreement of 3 multi-frame data is detected.

Next, an embodiment of the m frame coincidence detection circuit will be described with reference to FIGS. Data to be written in RAM1 or RAM2 shown in the RAM write data of FIG.
At the address shown in the RAM write address of FIG.
The data written and written by the write signal indicated by the E signal is compared with the data read from the RAM indicated by the RAM read data of FIG. 8 by the comparator 17, and the comparison result is indicated by the AND circuit 18. The coincidence detection timing pulse shown in FIG. 8 is ANDed, re-timed as shown in the frame coincidence detection result of FIG. 8, and input to the m + 1 counter 19, and as shown in the coincidence detection frame count value of FIG.
After counting up to m, all the m frames are determined to be coincident, the pulse is input to the decoder 34, a pulse as shown in the decoding of the count value m in FIG. 8 is output, and when the pulse shown in the m frame coincidence detection pulse in FIG. The AND circuit 35 outputs an m frame coincidence detection pulse.

Next, another embodiment of the m-frame coincidence detecting circuit will be described with reference to FIGS. In FIG. 9, the comparator 1
At 7, the data written in RAM 1 or 2 and
Next, the data to be written in the RAM 1 or 2 is compared, and if they match each other, at the timing shown by the match detection timing pulse in FIG. 10, it becomes H level as shown in the frame match detection result in FIG. 10, but becomes L level when they do not match, NAND circuit 1
Input in 8-1.

Therefore, the output of the NAND circuit 18-1 is input to the non-coincidence latch circuit 20 at H level when they do not match and at L level when they match. In the mismatch latch circuit 20, when the output of the NAND circuit 18-1 is at the H level,
H level as indicated by the mismatch detection chich information.

FIG. 10 shows the case where the mismatch is detected in the m-1th frame and the case where the mismatch is detected in the second frame, which is shown in the multi-frame FP of FIG.
When the frame pulse of the multi-frame is input, if the output is H level, the output of the AND circuit 35 becomes H level, and if the output is L level, the output of the AND circuit 35 is at L level and all the m frames match. Show.

Next, the steps from the synchronization detection protection of the input data to the coincidence detection output circuit of the multi-frame data will be described with reference to FIGS. 11 and 12. In FIG. 11 and FIG. 12, 6 of the input 64 frames = 1 multi-frame data
The synchronization pattern is inserted in the 3rd and 64th frames,
The synchronization detection protection unit 41 protects the multi-frame data in the front three stages and the rear three stages, and does not write the hunting data in the RAMs 1 and 2. Further, the number of times of coincidence of the coincidence detection output circuit of multi-frame data is set to 3 as in FIG.

The lowercase letters of the alphabet shown in (A), (I), and (J) of FIG. 12 indicate incomplete multi-frame data that cannot be synchronized. , C is synchronous, d is 1 step backward, o is 2 steps backward, and c is hunting. In (1), write data to RAM1, read data from RAM2, and in (2) RAM.
2 shows the timing when data is written in 2 and the data is read from RAM 1.

When the input data shown in FIG. 12A is input to the sync detection protection section 41, the sync pattern shown in FIG. 12B is detected, and the multiframe phase comparison pulse shown in FIG. RAM for total data shown in (I)
Write data corresponding to the write data is output from the RAM control unit 40 and is input to the same multiframe data match detection output circuit as shown in FIG.

The time charts of the operation of the coincidence detection output circuit of the multi-frame data are shown in FIGS. 12F to 12P, and the operation is the same as that described with reference to FIG.

[0042]

As described above in detail, according to the present invention, the RAM has a double buffer structure and m frames =
Match detection for all frames of one multi-frame data is performed simultaneously in both RAMs 1 and 2, and the data mismatch detection circuit 5 constantly monitors the outputs of the m-frame match detection circuits 3 and 4 for n consecutive times in multi-frame units. Since the matched data is compared with the data which is newly matched n times continuously, the mismatch is detected and the multi-frame data is output, the data transfer is not required.
The processing time is shortened, and complicated control is not required to obtain the mismatch information.

[Brief description of drawings]

FIG. 1 is a block diagram of a match detection output circuit for multi-frame data according to an embodiment of the present invention,

2 is a time chart of each part of FIG.

FIG. 3 is a block diagram of a match detection output circuit for multi-frame data according to another embodiment of the present invention,

FIG. 4 is a time chart of the operation of the m-frame coincidence detection circuit and mask circuit of FIG.

FIG. 5 is a block diagram of a data mismatch detection circuit according to an embodiment of the present invention,

6 is a state transition diagram of the decoders A ^{i + 1} and B ^{i + 1} in FIG.

FIG. 7 is a block diagram of an m-frame match detection circuit according to an embodiment of the present invention,

FIG. 8 is a time chart of each part of FIG.

FIG. 9 is a block diagram of an m-frame coincidence detection circuit according to another embodiment of the present invention,

10 is a time chart of each part of FIG. 9,

FIG. 11 is a block diagram from the sync detection protection circuit to the multi-frame data match detection output circuit according to the embodiment of the present invention;

12 is a time chart of each part of FIG.

FIG. 13 is a block diagram of a conventional multi-frame data match detection output circuit;

FIG. 14 is a time chart of each part of FIG.

[Explanation of Codes] 1, 2 RAM, 3, 4 m frame match detection circuit, 5 data mismatch detection circuit, 6 switching signal output section, 7 write signal switching section, 8 and 23 selector, 9 Mask circuit, 10 to 13, 18, 21, 22, 28 and 35 are AND circuits, 17 is a comparator, 18-1 is a NAND circuit, 19 is a counter, 20 is a mismatch latch circuit, 24, 25 and 34 are decoders, Reference numerals 26 to 29 denote flip-flops.

Claims (2)

[Claims] 1. A write signal switching unit in a multi-frame data coincidence detection output circuit which outputs multi-frame data when the same multi-frame data is input n times when data constituting one multi-frame in m frames is input. Write the input data in units of one multi-frame with each of the write signals switched in (7).
Second RAM (1) (2) and the first or second RAM
The 1-multi-frame data written in 1 and the 1-multi-frame input data to be input next are compared for each frame, and a match signal is output when all the frames match with each other. Frame match detection circuit (3) (4)
And the first and second m-frame coincidence detection circuits (3)
By inputting the output of (4), it is detected that the same multi-frame data has been received n times in succession, and the data for which the previous multi-frame unit coincidence detection is performed n times and the next multi-frame unit When the data that has been subjected to the continuous match detection n times is not the same, the data mismatch information is output as data mismatch information and the data mismatch detection circuit (5) to be input to the switching signal output unit (6) and the data mismatch information are input. Then, the switching signal output unit (6) that sends a switching signal to the write signal switching unit (7) and the selector (8).
And the first and second m-frame coincidence detection circuits (3)
A selector that inputs the outputs of the first and second RAMs (1) and (2) that are input to (4), and switches by the switching signal of the output of the switching signal output unit (6), and outputs either input. (8) and the write signal switching unit (7) for switching the write signal to the write signal for the first or second RAM according to the output switching signal of the switching signal output unit (6). Match detection output circuit of the characteristic multi-frame data. 2. The multi-frame data written in the first or second RAM by the first and second m-frame coincidence detection circuits (3) and (4) and the next input 1
When comparing multi-frame data for each frame, when the frame data to be compared match each other, a mask circuit (9) for preventing writing of the frame data to the first or second RAM. ) Is provided on the output side of the write signal switching unit (7), and the coincidence detection output circuit for multi-frame data according to claim 1.