JPS6086938A - Synchronism detecting circuit - Google Patents

Abstract

PURPOSE:To continue a synchronism detecting status and to prevent the generation of erroneous synchronism by detecting a preset signal generated within a PN code generating part and suppressing the synchronism detection status in case said preset signal is produced in the timing other than the prescribed one. CONSTITUTION:A switching logical circuit 8 is provided to a synchronizing circuit 10 of a synchronism detecting circuit, and the output of an RS type FF4 which uses the input data and a reset signal as its input is supplied to the circuit 8. The data containing a PN bit code given from the circuit 8 is applied to a 10- bit shift register 1 constituting a PN code generating part. An exclusive logic is obtained between the output of the register 1 and the input data by exclusive logical circuits 6 and 7. The output of the circuit 7 is applied to a 41-notation counter 3. The FF4 is inverted by the output of the counter 3, and the circuit 8 is switched to detect the synchronizm. While the output of the circuit 6 is applied to a 1,023-notation counter 5 and an exclusive logical circuit 9 via a decimal counter 2. Thus it is possible to suppress the synchronism detection status generated in the timing other than the prescribed one.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a synchronization detection circuit for data transmission using a PN code as a frame synchronization pattern.
The present invention relates to a synchronization detection circuit suitable for preventing erroneous synchronization when "0" occurs continuously.

[Background of the invention]

In conventional synchronization detection circuits of this type, the so-called logic "0"
If input data was input continuously over a long period of time, a problem occurred in which synchronization could occur incorrectly.

[Purpose of the invention]

An object of the present invention is to provide a synchronization detection circuit that does not cause erroneous synchronization when input data of logic 60'' is continuously input for a long time when detecting synchronization of input data including a PN code as a synchronization pattern. It is in.

[Summary of the invention]

In the present invention, if we look at consecutive N bits in the synchronization pattern of a -2-1 (N is a positive integer) bit PN code,
Taking advantage of the fact that the same pattern is seen only once in one period of the N code synchronization pattern, by confirming that a certain pattern appears at 2-1 bit intervals - it is possible to accidentally synchronize. This is a synchronization detection circuit that prevents this from happening.

[Embodiments of the invention]

An embodiment of the present invention will be explained below with reference to the drawings, which are circuit diagrams showing two embodiments of the synchronization detection circuit according to the present invention.
The code used is 2101.

In the figure, 1 is a 10-bit shift register that forms a PN code generator, 2 is a decimal counter, 3 is a 41-bit counter, 4 is an l (S flip 70 block, 5 is a 1026-bit counter, and 6.7 is an exclusive logic J !!In the first circuit, 8 is a switching logic circuit, 9 is an exclusive logic 40 circuit, and 10 is a conventional synchronous circuit.

With this configuration, the one frame synchronization pattern is 21°-1 (
1023) When input data including a PN code of bits is inputted via the switching logic circuit 8 of the conventional synchronous circuit 10 to the 10-bit shift register 1 forming the PN code generating section, the input data and the above PN code forming the PN code generating section are input. The output from the exclusive OR circuit 6 of the 10-bit shift register 1 is compared bit by bit in the exclusive OR circuit 7, and if a certain number of matching results are obtained in succession, for example, 41 pits, the output is converted to 41 decimal notation. The output of the counter 3 inverts the RS flip-flop 4 and switches the switching logic circuit 8 to detect synchronization. On the other hand, the decimal counter 2 is connected to the exclusive logic circuit 6.
For example, 10 consecutive bits of logic "1" are detected over one cycle of the PN code from the output preset signal via the 1023 decimal counter 5 which is reset by the signal from the decimal counter 2.
When 6 bits are counted, a carry signal is output from the 6-1025 decimal counter 5, so if the operation of the conventional synchronous circuit 10 is correct at the time of this output, the decimal counter 2 should also output a signal again. - Therefore, when these two signals are compared by the exclusive OR circuit 9 and an error is detected, the S flip-flop 4 is reset and the synchronization detection state is continued. 10 false synchronizations can be prevented.

Note that although the above embodiment uses a 210-1 bit PN code, it may generally be a 2-1 bit PN code, and although 10 bits consecutively with logic ``1'' is detected, other It may be a fixed pattern.

In this way, according to this embodiment, by providing a simple additional circuit to the conventional synchronous circuit, it is detected that the image value from the -IQ base counter 2 has disappeared, and the conventional synchronous circuit is Erroneous synchronization of the synchronization circuit can be prevented.

〔Effect of the invention〕

According to the synchronization detection circuit of the present invention as described above.

When detecting synchronization of input data using a PN code as a synchronization pattern, it is possible to detect false synchronization due to consecutive data of logic "o" and prevent malfunction of the synchronization circuit.

[Brief explanation of the drawing]

1... 10-bit shift register forming a PN code generator, 2... Decimal counter, 3... Δ1 counter, 4... RS flip 70 block, 5... 10234
Counter, 6.7... Exclusive OR circuit, 8... Switching logic circuit, 9... Exclusive OR circuit, 10... Synchronous circuit. Representative Patent Attorney Akio Takahashi Procedural Amendment (Method) Indication of Case 1982 Patent Application No. 194289 Name of Invention Person who corrects synchronization detection circuit Relationship with ifF+ Patent applicant and 1st name +5101 Stock Company 11 [1] Description (brief description of drawings) 1,
Page 5, line 18 of the specification is corrected as follows. [4. A simple explanatory diagram of the drawing is a circuit configuration diagram of a synchronization detection circuit which is an embodiment of the present invention. "that's all

Claims (1)

[Claims] PN which is input data including PN code which is synchronization pattern
A synchronizer comprising means for inputting the input data to the coco generator, and means for comparing the input data and the output of the PN coco generator bit by bit and detecting synchronization when a certain number of consecutive matching results are obtained. The detection circuit detects the preset signal generated in the PN code generation section, and when it is detected that the signal is not generated at the specified timing, it suppresses the synchronization detection status based on the detection and returns to the synchronization detection state. A synchronous prosecutor circuit characterized in that a means for continuing the process is provided.