JPH04196935A - Time division multiplexing circuit - Google Patents

Abstract

PURPOSE:To enable in-phase transmission for the several channels of a system by detecting the rise of an external clock synchronized to a parallel data, shifting the output of a rise detection circuit to generate pulses for several bits, and obtaining a latch pulse and a frame pulse. CONSTITUTION:When transmission velocity is defined as f0, the external clock at f0/2n[bps] synchronized to the parallel data is latched to an FF 110 by an f0 clock and latched to an FF 211 by the next f0 clock. Next, the output of a first rise detection circuit 4 is fed back to a 2 frequency divider circuit 3 and when the output of the circuit 4 is H and the output of the 2 frequency divider circuit 3 is L, the output phase is inverted. In a phase shift circuit 5, the latch pulse is obtained by delaying timing for the output of the detection circuit 4. In a frame pulse generating circuit 6, the frame pulse is generated by using the output from the phase shift circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division multiplex circuit used in one time division multiplex transmission.

[Prior Art 1] FIG. 9 is a configuration example of a conventional time division multiplexing circuit that converts parallel data into serial data and converts it into a 2-bit code on which a frame pulse is superimposed.

In the figure, (1) is a parallel data/serial data conversion circuit (hereinafter referred to as a P/S conversion circuit), (2) is a frame pulse superimposition transmission line encoding circuit (hereinafter referred to as an encoding circuit), f3). (7) is a ring counter circuit, and (6) is a frame pulse generation circuit.

Next, the operation will be explained. In FIG. 9, the externally input transmission rate f0 [bp
s] transmission lock to f. /2 [bps] serial data clock is generated.

It is input to the ring counter circuit (7). The ring counter circuit (7) divides the frequency of the fo /2 ['bps] clock by n to obtain a latch pulse. A frame pulse generation circuit (6) uses the negative output of the ring counter circuit (7) to generate a frame pulse synchronized with the transmission frame. On the other hand, the n-bit parallel data input to the P/S conversion circuit (1) is latched by the latch pulse and converted into serial data. The serial data is converted by an encoding circuit (2) into a transmission line code on which the frame pulse is superimposed.

Here, the data frame has n different phase states depending on the phase state of the ring counter.

[Problem to be solved by the invention] Since the conventional multiplexing circuit is configured as described above,
When operating several channels of the same system, the phase of data on each receiving side will be different, so there is a problem that the phases of each system must be made the same.

The present invention was made to solve one or more of the above problems, and an object of the present invention is to obtain a multiplexing circuit that can transmit a system of several channels in the same phase.

[Means for Solving the Problems] (1) The multiplexing circuit of the present invention detects the rising edge of an external clock synchronized with parallel data, shifts the output of a rising edge detection circuit that generates a pulse by several bits, and generates a latch pulse. , the input f is configured to obtain a frame pulse. /2n [bps] external clock to output a frame pattern having a constant phase.It is possible to output a frame pattern having a constant phase to an external clock.

(2) The multiplexing circuit in this invention detects the rising edge of an external clock synchronized with parallel data, and compares the output of a rising edge detection circuit that generates a pulse with the output of one of the internal ring counters. , latch pulse, and frame pulse, the external clock output in a frame pattern having a constant phase with respect to the input external clock of f o / 2 n [b p s ] This makes it possible to output a frame pattern with a constant phase, and also makes it difficult for data to be lost even if the clock disappears temporarily.

(3) The multiplexing circuit according to the present invention increases the clock jitter and reduces the skew between each channel by widening the pulse width of the output of the rising edge detection circuit that is compared with the output of one of the internally provided ring counters. This makes it possible to apply it to systems with less demanding requirements.

[Function] The multiplexing circuit according to the present invention generates constant latch pulses and frame pulses in response to an external clock synchronized with parallel data, making it possible to obtain a multiplexing circuit capable of transmitting several channel systems in the same phase. .

[Embodiment] FIG. 1 shows an embodiment of a time division multiplexing circuit according to the present invention. (1) is a P/S conversion circuit, (2) is an encoding circuit, (3) is a divide-by-2 circuit, (4) is a first rise detection circuit, (5) is a phase shift circuit, and (6) is a This is a frame pulse generation circuit.

FIG. 2 shows the internal circuit of the first rise detection circuit (4) of the embodiment shown in FIG. (io) is the first flip-flop (hereinafter referred to as FFI), (11) is the second flip-flop (hereinafter referred to as FF2), (
12) is an inverter, and (13) is a first AND gate.

FIG. 3 shows a timing chart showing the operation of the embodiment shown in FIG.

FIG. 4 is a diagram showing another embodiment of the time division multiplexing circuit according to the present invention. (7) is a ring counter circuit, (8
) is a synchronization protection circuit.

FIG. 5 shows a timing chart showing the operation of the embodiment shown in FIG.

FIG. 6 shows another embodiment of the same time division multiplexing circuit according to the present invention. (9) is a second rise detection circuit.

FIG. 7 shows the internal circuits of the first rise detection circuit (4) and the second rise detection circuit [9] of the embodiment shown in FIG. (10) is FFI, (11) is FF2゜(14)
is the third flip-flop (hereinafter referred to as FF3),
(15) is the fourth flip-flop (hereinafter referred to as FF4), (12) is the inverter, (13)
is the first AND gate, and (16) is the second AND gate.

FIG. 8 shows a timing chart showing the operation of the circuit of FIG. 7.

Next, the operation will be explained. In FIG.

The externally input transmission speed f0 is determined by the divide-by-2 circuit (3).
[bpsl transmission lock to f. A serial data clock of /2 [bpsl is generated. Here, the first rise detection circuit (4) is.

It has the configuration shown in FIG. 2, and its operation is f synchronized with parallel data as shown in FIG. / 2 n [bps
l's external clock is f. F F 1 (
10) is latched to the ninth order f. Due to the clock, FF2
(11) is latched. When fo/2n clock rises, FFI (10) is “H”.

F F 2 (11) Force becomes L''', AND game)
- The output of (13) becomes "H". Next, the output of the first rise detection circuit (4) is fed back to the divide-by-2 circuit (3), and when the output of the first rise detection circuit (4) is "H", the output of the divide-by-2 circuit (3) is When the output is "L"', the output phase is inverted in the divide-by-2 circuit (3). Further, the 9-phase shift circuit (5) obtains a latch pulse by delaying the output of the first rise detection circuit (4) to a timing that facilitates data capture. 1 phase shift circuit (5) in frame pulse generation circuit (6)
Generate a frame pulse using the output from on the other hand,
The n-bit parallel data input to the P/S conversion circuit (1) is latched by the latch pulse and converted into serial data. The serial data is converted by an encoding circuit (2) into a CMI/CRV code on which the frame pulse is superimposed.

In FIG. 4, the phase shift circuit (5) in FIG. 1 is replaced with an n-bit ring counter circuit (7) and a synchronization protection circuit (8) to generate a latch pulse. As shown in Figure 5, in the ring counter circuit (7), the frequency divider circuit (3)
The output f. /2 [bps] clock is divided by n to obtain a latch pulse. In the synchronization protection circuit (8), the output of the first rise detection circuit (4) and the ring counter circuit (7
) among the outputs of the first rise detection circuit (4), which should match in phase with the f0/2 clock, and if they do not match once or several times, The phase of the ring counter circuit (7) is shifted until they match. Feedback for determining the phase of the divide-by-2 circuit (3) is provided by the synchronization protection circuit (
8). This circuit is effective against data loss due to temporary clock loss.

FIG. 6 shows a configuration in which a second rise detection circuit (9) is provided in FIG. 4. Here, the second rise detection circuit (9) has the configuration shown in FIG. 7, and its operation is as follows.
As shown in FIG. 8, when FFI is 'H' and FF3 is 'L', the second AND game (16) outputs 'H'. Therefore, the first rise detection circuit (4)
Compared to the output of , it becomes ``H'' for one clock around 9 at fa [bps] clock. In the synchronization protection circuit (8), the phase of the output of the second rise detection circuit (9) and the output of the first rise detection circuit (4) among the outputs of the ring counter circuit (7) should match. One output of and f
. /2 clock and when they do not match once or several times, the ring counter circuit (7) is used until the phase matches with the output of the first rising detection circuit (4).
Shifts the phase of This circuit compares the phase with the second rising edge detection circuit (9), so even if the rising edge of the clock deviates by I clock, synchronization will not be lost, and this circuit is effective for systems with large clock jitter. In this embodiment, the output of the second rise detection circuit (9).

Compared to the output of the first rise detection circuit (4).

fo [bps] clock “H” for 1 clock before and after 1
However, it is possible to make the pulse several bits wider, around 9, depending on the margin of skew between channels.

Any of the embodiments can be used depending on the system design and produce similar effects.

[Effects of the Invention] As described above, the time division multiplexing circuit according to the present invention has the following effects:
Since it is equipped with a circuit that generates latch pulses and frame pulses based on an external clock that is synchronized with parallel data, it has the effect of providing a time division multiplexing circuit that can transmit several channel systems in the same phase. be.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the multiplexing circuit of the present invention, FIG. 2 is a diagram showing the internal circuit of the first rise detection circuit of the embodiment of FIG. 1, and FIG. FIG. 4 is a diagram showing another embodiment of the multiplexing circuit of the present invention, FIG. 5 is a timing chart showing the operation of the embodiment of FIG. 4, and FIG. The diagrams are the same (a diagram showing another embodiment of the multiplexing circuit of the present invention; FIG. 7 is a diagram showing the internal circuits of the first rise detection circuit and the second rise detection circuit of the embodiment of FIG. 6). , FIG. 8 is a timing chart showing the operation of the circuit in FIG. 7, and FIG. 9 is a diagram showing a conventional time division multiplexing circuit.
) is a P/S conversion circuit. (2) is an encoding circuit, (3) is a divide-by-2 circuit, (4) is a second rising edge detection circuit, (5) is a phase shift circuit, (
6) is a frame pulse generation circuit, (7) is a ring counter circuit, (8) is a synchronization protection circuit, and (9) is a second rising edge detection circuit. In Figure 1, the same reference numerals indicate the same or equivalent parts. Fig. 1 2 Encoding date 32 minutes Biguchi 4: *+ sentence inspection report times 5 a phase shift bn 6 claim pulse now I]! '& Figure 2, Figure 4, Figure 3. re, Jl且几几厊－一－－－－－－－－上几几几'J９－－－－１１－－－pair=``1 し Act 7;
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Claims (3)

[Claims] (1) Parallel data/serial data conversion in a time division multiplex transmission method that converts n-bit parallel data into serial data and encodes it into a 2-bit 1 code with a frame synchronization pulse synchronized with the serial data for data transmission. circuit, a frame pulse superimposition transmission line encoding circuit connected to the parallel data/serial data conversion circuit, and an f synchronized with the parallel data.
A first rising detection circuit detects the rising edge of an external clock of _0/2n [bps] and generates a pulse with a width of one clock; A divide-by-2 circuit outputs an f_0/2 [bps] clock having a predetermined phase with respect to the output of the detection circuit, and the output pulse of the first rise detection circuit is input, and the parallel data/serial data is a phase shift circuit that outputs a latch pulse with timing suitable for latching parallel data to be input to the conversion circuit; and a phase shift circuit connected to the phase shift circuit;
and a frame pulse generation circuit that generates a frame synchronization pulse according to a predetermined frame synchronization pattern to be input to the frame pulse superimposition transmission line encoding circuit, and the input f_0/2n [bps
] A time division multiplexing circuit characterized by outputting serial data in a frame pattern having a constant phase with respect to an external clock. (2) Parallel data/serial data conversion in a time division multiplex transmission method in which data is transmitted by converting n-bit parallel data into serial data and encoding it into a 2-bit 1 code with a frame synchronization pulse synchronized with the serial data. circuit, a frame pulse superimposition transmission line encoding circuit connected to the parallel data/serial data conversion circuit, and an f synchronized with the parallel data.
A first rising detection circuit detects the rising edge of an external clock of _0/2n [bps] and generates a pulse with a width of one clock; a divide-by-2 circuit that outputs an f_0/2 [bps] clock having a predetermined phase with respect to the output of the detection circuit;
] A ring counter circuit that divides the clock by n and outputs a latch pulse, and compares the phase of one output of the ring counter circuit with the output phase of the first rise detection circuit, once or several times in succession. a synchronization protection circuit that generates a control signal that shifts the phase of the ring counter circuit to match the output phase of the first rise detection circuit when the output phase of the first rise detection circuit does not match; and a frame pulse generation circuit that generates frame synchronization pulses according to a predetermined frame synchronization pattern to be input to the pulse superimposition transmission line encoding circuit, and the input f_0/2n[
A time division multiplexing circuit characterized in that it outputs serial data in a frame pattern having a constant phase with respect to an external clock of [bps]. (3) Parallel data/serial data conversion in a time division multiplex transmission method that converts n-bit parallel data into serial data, encodes it into a 2-bit 1 code with a synchronized frame synchronization pulse superimposed on the serial data, and transmits the data. circuit, a frame pulse superimposition transmission line encoding circuit connected to the parallel data/serial data conversion circuit, and an f synchronized with the parallel data.
A first rise detection circuit that detects the rise of an external clock of _0/2n [bps] and generates a pulse with a width of one clock, and a signal that is several clocks wide before or after the output of the first rise detection circuit. A second rise detection circuit that outputs a pulse and a transmission speed f_0[b
ps] is divided by two, and has a phase determined with respect to the output of the first rise detection circuit.
A divide-by-2 circuit that outputs a _0/2 [bps] clock,
A ring counter circuit divides the frequency of the f_0/2n [bps] clock by n and outputs a latch pulse, and compares the phase of one output of the ring counter circuit with the output phase of the second rise detection circuit, a synchronization protection circuit that generates a control signal that shifts the phase of the ring counter circuit to match the output phase of the first rising edge detection circuit when the phase does not match one or several times in a row; and a frame pulse generation circuit that generates a frame synchronization pulse according to a predetermined frame synchronization pattern to be input to the frame pulse superimposition transmission line encoding circuit, and the input f_0/2n [bps ] A time division multiplexing circuit characterized by outputting serial data in a frame pattern having a constant phase with respect to an external clock.