JPH03183229A - Synchronization error generation circuit - Google Patents

Abstract

PURPOSE:To surely generate the set number of error bits by converting an error bit generating instruction synchronizing with a processor clock into the instruction synchronizing with a transmission line clock, and afterwards, generating an error bit setting pulse by delaying the instruction by two bits portion of the transmission line clock, and taking an exclusive OR with transmission line data. CONSTITUTION:Flip flops 21, 22 and a latch circuit 23 are the constituent part of a clock switching part 2, and the flip flops 31, 32, 34 and an EX-OR gate 33 are the constituent part of an error bit generating part 3. The error bit generating instruction synchronizing with the processor clock is converted into the instruction synchronizing with the transmission line clock by the clock switching part 2. Then, at the error bit generating part 3, after the error bit generating instruction synchronizing with the transmission line clock is delayed, and the error bit setting pulse is obtained, the check bits which are in-phase with a specified data bit are generated by the designated number of bits by taking the exclusive OR of this error bits setting pulse and the transmission line data, and are sent as the error bits. Thus, the set number of the error bits are surely generated.

Description

[Detailed Description of the Invention] [Summary] To ensure that a set number of error bits are generated in a synchronization error generation circuit used when testing the synchronization protection function of equipment using nB1C codes. With the purpose of Using bits (
In a transmission system that performs synchronization protection for n+1) bits, a clock transfer section synchronizes an input error bit generation command with the transmission line clock, and an output of the clock transfer section,
After obtaining the error bit number setting pulse by delaying it by the number of synchronization protection stages using the transmission line clock, the specific data bit is set by the set number of bits using the error bit number setting pulse and the specific data bit. and an error bit generation section that generates error bits in phase with the error bits.

[Industrial application field]

The present invention relates to a synchronization error generation circuit used when testing the synchronization protection function of equipment using nBlc codes.

For example, when transmitting 8-bit data using a LAN with a transmission speed of 100 Mb/s or more, the 88IC code is sometimes used.

This 8BIC code inverts the data of the 8th bit and adds it to the 9th bit as a check bit to ensure the mark rate of the data is 1/8 or more. It is possible to take synchronization protection (hereinafter, this protection is referred to as word synchronization) using the check bit of .

Here, the synchronization protection normally used is only frame synchronization protection, but the above-mentioned word synchronization is useful for improving the quality of the transmission path.

This is because, in the case of frame synchronization, the number of bits included in an e-frame is large, and even if a bit error occurs near the center, this error will not be noticed unless it affects the frame synchronization pattern.

However, in the case of word synchronization, out-of-synchronization is detected every (8+1) bits, so if a bit error occurs, it can be detected more quickly than in the case of frame synchronization, and a prompt response can be taken.

Now, it is necessary to remove the synchronization and check the synchronization protection function to see if the word synchronization protection circuit is functioning properly. At this time, it is necessary to ensure that the set number of error bits are generated. is necessary.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example, and FIG. 5 is an explanatory diagram of the operation of FIG. 4.

Here, transmission line data 0 to 6 in FIG. 4 are represented by one transmission line data. Also.

The symbols on the left side of FIG. 5 indicate the waveforms of the portions with the same symbols in FIG.

Hereinafter, the operation of FIG. 4 will be explained with reference to FIG. 5, assuming that the number of forward protection stages is two.

First, the input transmission line data O to 6 and 7 are input to the corresponding flip-flops (hereinafter abbreviated as FF) 11.
．． 12, the data is punched out using the transmission line clock and sent out as output data 0 to 6 and output data 7 (Fig.
(See ■, ■, ■: Transmission path data 7 only).

Next, when an error bit generation command is input from a processor (not shown) in 9, the FF 13 punches out using a processor clock that is asynchronous to the transmission line clock.

The inverted output is taken out and sent to the EX-OR gate 14 (see Figure 5 - ■, ■, ■).

On the other hand, transmission line data 7 is also added here, so
By taking the exclusive OR of the two data, an output as shown in Figure 5-■ is obtained, and when further punched out using the transmission line clock by FF 15, output data 8 as shown in Figure 5-■ is obtained.
(check bit) is obtained.

That is, as an 8BIC code, output data 8 is a bit obtained by inverting output data 7 (see other than A and B in Figure 5-■ and ■), but due to the error bit generation command, the bits in Figure 5-■ and ■ are inverted. As shown in A and B, as many in-phase bits (erroneous bits) as there are front protective films are generated.

As a result, the synchronization protection circuit (not shown) in the forward protection mode loses synchronization twice in a row, so the forward protection is removed and the circuit goes into an asynchronous state.

[Problem to be solved by the invention]

As mentioned above, in order to remove the synchronization protection of the two stages of forward protection, the states of the two bits of output data 7 and 8 must be made the same, as shown in A and B in Figure 5--.

However, since the processor clock and the transmission line clock are asynchronous, there is a problem in that the set number of error bits is not guaranteed to occur.

For this reason, there is a possibility that the synchronization will be lost an indefinite number of times, and when the synchronization becomes out of synchronization, the synchronization protection may be forcibly removed by a command from the processor, or the synchronization protection may be removed due to an error that occurred in the transmission path. It was difficult to determine whether

An object of the present invention is to ensure that a set number of error bits are generated.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 2 is a clock transfer part that synchronizes the input error bit generation command with the transmission line clock, and 3 is a clock transfer part that delays the output of the clock transfer part by the number of synchronization protection films using the transmission line clock. After obtaining the error bit number setting pulse, the error bit generation part generates error bits having the same phase as the specific data bit by the set number of bits using the error bit number setting pulse and the specific data bit.

[Effect]

The present invention uses a clock transfer circuit to convert an error bit generating instruction synchronized with a processor clock into an instruction synchronized with a transmission line clock.

In the error bit generation section, the error bit generation command synchronized with the transmission line clock is delayed to obtain an error bit setting pulse, and then the error bit setting pulse and the transmission line data are exclusive-ORed and specified. Check bits having the same phase as the specified data bit are generated and sent as error bits.

This ensures that the set number of error bits are generated.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2.

The transmission line data O to 6 in FIG. 2 are represented by one transmission line data, and the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG. 2. Also, the same reference numerals indicate the same objects throughout the figures.

Here, flip 70 knobs 21.22. Latch circuit 23
is a component of clock transfer section 2, flip-flop 3
1.32.34. The BX-OR gate 33 is a component of the error bit generation section.

Hereinafter, the operation shown in FIG. 2 will be explained with reference to FIG. 3 as the second stage of front protection.

First, the input transmission line data 0 to 6 and 7 are punched out by the corresponding flip-flops FF 11 and 12 using the transmission line clock and sent out as output data 0 to 6 and output data 7 (Fig. 3). −■, ■, [phase] Reference:
transmission path data 7 only).

Next, when an error bit generation command is input from a processor (not shown), the FF 21 delays by one pit of the processor clock and obtains a delayed output.

The output of this FF 21 is further processed by the processor in FF 22.
The clock is delayed by 1 pit, then inverted by 7, and the inverted output is sent to the reset terminal of the FF 21 and the terminal S of the latch circuit 23.
(See Figure 3 - ■, ■).

Therefore, the FF 21 is reset, and the error bit generation instruction transferred to the transmission line clock as shown in FIGS.
1 (see Figure 3 - ■, ■).

This error bit generation instruction is FF31. Transmission line clock 2 with 32 FF 2 stages (equal to the number of forward protection stages)
After a delay of one clock, the FF as shown in Figure 3-■
The inverted output of 32 is applied to terminal R of the latch circuit and EX-OR gate 33.

Therefore, the latch circuit 23 is reset and outputs an L level, but as a result, the synchronization protection is removed only once for each command from the processor.

In addition, since the transmission line data shown in Figure 3-■ is also added to the EX-OR gate 33, after the exclusive OR of the two signals is taken, the FF 34 further outputs the transmission line clock data for 11 minutes. , the output as shown in FIG. 3-0 is taken out as output data 8.

Here, when comparing the output data 7 and the output data 8 shown in FIG. 3-[Phase], (2), it is found that the A and H portions are in the same phase and two error bits occur.

That is, after converting an error bit generation instruction synchronized with the processor clock into an instruction synchronized with the transmission line clock, this instruction is delayed by two bits of the transmission line clock to generate an error bit setting pulse.

Then, by taking the exclusive OR of this setting pulse and the transmission line data, a set number of error bits are reliably generated.

In addition, when the number of protection stages is 3, FF 31.32 FF
You can change the 2 tiers to 3 tiers.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an effect that a set number of error bits are reliably generated.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is a block diagram of a conventional example, and Fig. 5 is a block diagram of an embodiment of the present invention. The operation explanatory diagram of FIG. 4 is shown. In the figure, 2 indicates a clock transfer section, and 3 indicates an error bit generation section.

Claims (1)

[Claims] Using an nB1C code that adds a check bit, which is an inversion of a specific data bit within the n bits, to every n data bits (n is a positive integer) synchronized with the transmission line clock. In a transmission method that transmits data and protects the synchronization of (n+1) bits using the inverted check bit, a clock transfer part (2) that synchronizes the input error bit generation command with the transmission line clock and the clock transfer After obtaining the error bit number setting pulse by delaying the output of the part by the number of synchronization protection stages using the transmission line clock, the bit number set using the error bit number setting pulse and the specific data bit. 1. A synchronous error generation circuit comprising: an error bit generation section (3) that generates an error bit that is in phase with the specific data bit.