JPH0467819B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a digital synchronization protection circuit using a competition counter, which is used in digital equipment. [Prior Art] Conventionally, as shown in FIG. 4, this type of synchronization protection circuit includes a synchronization input detection circuit 1 that generates a coincidence pulse every time a synchronization signal is input at a correct synchronization time point.
, an inverter 2 that outputs a synchronization mismatch pulse a, counters 3 and 4 that count the synchronization mismatch pulse a and a match pulse, respectively, and when the counter 3 reaches the set value _N1 , the output is set and the counter 4 Flip-flop 5, which is reset when reaches the set value _N3 , and flip-flop 5
an AND gate 6 which outputs a hunting pulse every time a mismatch pulse a is input when the is in a set state;
It consists of an OR gate 7 which outputs a signal to reset the counter 3 and counter 4 when the counter 3 reaches the set value _N1 , the counter 4 reaches the set value _N2 , or a hunting pulse is output. In the steady state, since there are almost only matching pulses, the counter 4 operates, and even if the counter 3 happens to operate due to a code error, the counter 4 is reset soon. When errors occur intensively due to loss of synchronization, the probability of occurrence of mismatched pulses increases, so counters 3 and 4 compete with each other, and when the concentration increases, counter 3 decreases to the set value.
When N ₁ is reached, flip-flop 5 is operated,
Generates a hunting pulse for synchronization pull-in. FIG. 5 is a timing chart showing the operation of the synchronization protection circuit of FIG. 4. Initially, the synchronization protection circuit is in a steady state, with almost only coincidence pulses, and counter 4 is at the set value.
The reset operation is repeated every time N ₂ =5 is reached. Then, after time t=t1 _, when the number of mismatched pulses a starts to increase due to synchronization loss, counter 3 reaches the set value _N1 =3 at time _t2 before counter 4, and flip-flop 5 is set and counter 3 , the counter 4 is reset by the output of the OR gate 7. Therefore, every time the mismatch pulse a is input to the AND gate 6, a hunting pulse is output to perform synchronization pull-in, and the output of the OR gate 7 resets the counters 3 and 4. Due to the synchronization pull-in, no coincidence pulses are generated after t= _t3 , and when the count value of the counter 4 reaches _N3 =3 at time t= _t4 , the flip-flop 5 is reset and from then on, a mismatch pulse a is input. However, synchronous pull-in is not performed. As can be seen from the above explanation, the forward protection characteristics are determined by the set values N ₁ and N ₂ of the counters 3 and 4, and the rear protection characteristics are determined by the output from the level of the set value N ₃ of the counter 4. It is given by resetting the flip-flop 5 that represents the state, and its protection time is approximately equal to _N3 (see above, Sanpo Publishing "PCM Communication Technology" P116~
P117). [Problems to be Solved by the Invention] In the conventional synchronization protection circuit described above, when the calculation setting value _N1 of the mismatch counter is made small, even if a minute error occurs in the transmission path, the synchronization signal is still being sent. However, the value of N ₁ cannot be made small because there is a high probability that the signal will be misidentified as not being a synchronized signal.On the other hand, if N ₁ is too large, it will be difficult to follow the loss of synchronization. [Means for Solving the Problems] The present invention focuses on the fact that a synchronization pattern with a sharp autocorrelation function is selected for the synchronization signal. For example, 0111,
When 16 bits of 1010, 1100, and 1000 are selected, the number of synchronized matching bits on the hour is, of course, 16, as shown in Table 1 (○ indicates matching bits, × indicates data bits) and Figure 3. If the synchronization pattern deviates within two clocks, the number of bits that match the synchronization pattern is
Approximately 9 pieces or less. In other words, the number of matching bits is 10
If the number is more than 1, it is considered that the synchronization is on the hour, but part of the synchronization pattern has changed due to the transmission path.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the synchronization protection circuit of the present invention, and FIG. 2 is a timing chart showing its operation. This embodiment uses a synchronization pattern (hereinafter E
Abbreviated as pattern. ) and an E pattern detection circuit 8 that detects the E pattern, and every time a synchronization signal having a mismatch pattern other than the E pattern is input at the correct synchronization point, a mismatch pulse that is the output of the inverter 2 is detected. It is equipped with a gate circuit 9 that outputs a to the counter 3. Next, the operation of this embodiment will be explained with reference to the timing chart of FIG. Among the mismatched pulses in FIG. 2, two marked E are mismatched pulses corresponding to the E-pattern synchronization signal. The E pattern detection circuit 8 identifies this signal as an E pattern, closes the gate circuit 9, and excludes this E pattern pulse from the input pulses of the counter 3. Therefore, if the count value of counter 3, that is, the number of mismatched pulses excluding E pattern pulses, reaches N ₁ = 3 before the count value of counter 4 reaches N ₂ due to loss of synchronization, the flip-flop 5 is set and synchronous pull-in is performed. The above operation prevents a signal considered to be a synchronization signal (E pattern signal) from being misunderstood as not being a synchronization signal and causing synchronization pull-in, thereby improving the forward protection capability. [Effects of the Invention] As explained above, the present invention identifies the content of the number of the mismatch counter by detecting the E pattern, and even if the pattern is mismatched with the synchronization pattern, it can be regarded as the synchronization pattern. By subtracting the number of signals from the number of discrepancies counters,
This has the effect of strengthening forward synchronization protection.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the synchronization protection circuit of the present invention, FIG. 2 is a timing chart showing the operation of the synchronization protection circuit of FIG. 1, and FIG. 3 is a diagram showing the operation of the synchronization protection circuit of FIG. A graph showing the relationship between the reception timing shift and the number of bits that match the synchronization pattern. Figure 4 is a block diagram of a conventional synchronization protection circuit. Figure 5 is a timing chart showing the operation of the synchronization protection circuit shown in Figure 4. It is. 1... Synchronous input detection circuit, 2... Inverter,
3... Counter of unmatched pulses, 4... Counter of matched pulses, 5... Flip-flop, 6...
...AND gate, 7...OR gate, 8...E pattern detection circuit, 9...gate circuit.

Claims (1)

[Claims] 1. In a synchronization protection circuit using a contention counter consisting of a coincidence pulse counter that counts synchronization coincidence pulses and a mismatch pulse counter that counts synchronization mismatch pulses, the synchronization pattern is compared with a synchronization pattern used for a synchronization signal. a detection means for detecting a mismatch pattern in which the number of mismatched bits is several bits or less; and a detection means for normally outputting the input mismatch pulse to a mismatch pulse counter; A synchronization protection circuit comprising gate means for not outputting a mismatch pulse to the mismatch pulse counter.