JPS6247234A - Synchronism protecting circuit - Google Patents

Abstract

PURPOSE:To enhance forward synchronism protection by subtracting the number of signals, which have patterns which do not coincide with a synchronizing pattern but are regarded as the synchronizing pattern, from the counted value of a dissident counter. CONSTITUTION:Two pulses marked with E out of dissident pulses corresponding to the synchronizing signal of a pattern E. An E pattern detecting circuit 8 identifies this signal as the pattern E and closes a gate circuit 9 to eliminate these pattern E pulses from input pulses of a counter 3. Consequently, if step out occurs and the counted value of the counter 3, namely, the number of dissident pulses except pattern E pulses reaches N1=3 before the counted value of a counter 4 reaches N2, a flip flop 5 is set to acquire synchronism. By this operation, signals (pattern E signals) considered as the synchronizing signal are prevented from being erroneously recognized as not the synchronizing signal to acquire synchronism, thereby improving forward protection capability. Thus, the number of signals, which have patterns which are regarded as the synchronizing pattern though they do not coincide with the synchronizing pattern, is subtracted from the counted value of the dissident counter to enhance forward synchronism protection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital synchronization protection circuit using a contention counter, which is used in digital equipment.

[Conventional technology]

Conventionally, this type of synchronization protection circuit, as shown in Figure 4,
Each time a synchronization signal is input at a correct synchronization time point, a synchronization input detection circuit 1 generates a coincidence pulse i, an inverter 2 outputs a synchronization mismatch pulse a, and a counter that counts the synchronization mismatch pulse mi and coincidence pulse a, respectively. 3, 4 and
The output of the flip-flop 5 is set when the counter 3 reaches the set value N, and is reset when the counter 4 reaches the set value, and every time the mismatch pulse a is input when the flip-flop 5 is in the set state. The AND gate 6 outputs a changing pulse and the counter 3 outputs a set value N.
1, when the counter 4 reaches the set value N, or when a changing pulse is output, the OR gate 7 outputs a signal to reset the counter 3 and the counter 4.

In the steady state, since there is almost only the coincidence pulse i, the counter 4 operates, and even if the counter 3 happens to operate due to a code error, it will be reset soon by the operation of the counter 4. If errors occur intensively due to loss of synchronization, the probability of occurrence of mismatched pulses i increases, so counter 3
and the counter 4 compete with each other, and when the concentration becomes large, the counter 3 reaches the set value N, operating the flip-flop 5 and generating a steering pulse for synchronization pull-in.

FIG. 5 is a timing chart showing the operation of the synchronization protection circuit of FIG. 4.

Initially, the synchronization protection circuit is in a steady state, with only the coincidence pulse i, and the counter 4 is repeatedly reset every time it reaches the set value N,=5. And time 1 = 1. After that, when the number of mismatched pulses a starts to increase due to synchronization, the counter 3 reaches time t8 before the counter 4.
reaches the set value N1-3, the flip-flop 5 is set, and the counters 3 and 4 are set to the OR gate 7.
It is reset by the output of Therefore, every time the mismatch pulse a is input to the AND gate 6, a hunting pulse is output and synchronous pull-in is performed, and the OR gate 7
Counters 3 and 4 are reset by the output. 1 = 1 due to synchronous pull-in. After that, the coincidence pulse i is no longer generated, and time 1 = 1. The count value of counter 4 is N1.
When the value reaches -3, the flip-flop 5 is reset, and thereafter synchronization pull-in is not performed even if a mismatch pulse a is input.

As can be seen, the forward protection characteristics of the above fins are not determined by the set values N, , N, of counter 3.4.
The rear protection characteristic is given by resetting the flip-flop 5 representing the hunting state by the output from the level of the set value N of the counter 4, and the protection time is approximately equal to N. [PCM communication technology-IP116 to P-117).

[Problem that the invention seeks to solve]

"In the conventional dual synchronization protection circuit, if the set number N1 of the mismatch counter is made small, even if a slight error occurs in the transmission path, it will be mistaken as a synchronization signal even though it is being sent. Since the probability that NI occurs becomes high, the value of NI cannot be made small.On the other hand, if N is too large, it becomes difficult to follow the synchronization network.

[Means for solving problems]

The present invention focuses on the fact that a synchronization pattern with a sharp autocorrelation function is selected for the synchronization signal. As a synchronization pattern, for example, 0111, 1010°1100.
When 16 pits of 1000 are selected, as shown in Table 1 (○ indicates a coincidence pit, × indicates a data bit) and Figure 3 (the number of coincidence bits at the hour of two synchronizations is 1ris, but 2 clocks) If the deviation is within the range, the number of bits that match the synchronization pattern will be approximately 9 or less. In other words,
If the number of matching bits is 10 or more, synchronization is on the hour, but it is considered that part of the synchronization pattern has changed due to the transmission path.

Table 1 The synchronization protection circuit of the present invention includes a detection means for detecting a mismatch pattern that differs by several bits from a synchronization pattern used for a synchronization signal, and 1. Normally, an input mismatch pulse is output to a counter that counts the pulse. However, a gate circuit is provided which does not output the mismatch pulse to the counter I when the mismatch pattern is detected by the detection means.

In this way, by identifying the content of the mismatch pattern and subtracting the number of signals that can be considered as a synchronization pattern even if the pattern does not match the synchronization pattern from the count value of the mismatch counter, forward Synchronization protection can be strengthened.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the synchronization protection circuit of the present invention, and FIG. 2 is a timing chart showing its operation.

This embodiment uses an E pattern detection circuit 8 for detecting a pattern (hereinafter abbreviated as E pattern) that differs by several bits from the same pattern used for synchronization signals in the conventional synchronization protection circuit shown in FIG. is controlled by the E pattern detection circuit 8, and every time a synchronization signal having a mismatch pattern other than the E pattern is input at the correct time point j, ≦2,
The inconsistency pulse a, which is the output of inverter 2, is sent to counter 3.
(=It is equipped with a gate circuit 9 for output.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

Among the mismatched pulses in FIG. 2, two marked as F] are E
This is the mismatch pulse that corresponds to the synchronization signal of the pattern. E
The pattern detection circuit 8 classifies this signal as an E pattern, closes the gate circuit 9, and excludes this E pattern pulse from the input pulses of the counter 3. Therefore, if the itt h value of counter 3, that is, the number of mismatched pulses excluding E pattern pulses, reaches N, = 3 before the synchronization loss occurs and the single number value of counter 4 reaches N,
Flip-flop 5 is set and synchronous pull-in is performed.

The above operation prevents a signal considered to be a synchronization signal (E pattern signal) from being misunderstood as not being a synchronization signal and causing synchronization pull-in, thereby improving the forward protection capability.

〔Effect of the invention〕

As explained above, the present invention identifies the content of the number of mismatched kakuntas by detecting the E pattern, and determines the number of signals that can be regarded as a synchronization pattern even if the pattern does not match the synchronization pattern. Subtracting this from the number of mismatched kakuntas has the effect of strengthening forward synchronization protection.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the synchronization protection circuit of the present invention, Fig. 2 is a timing chart showing the operation of the synchronization protection circuit of the $1 figure, and Fig. 3 is a synchronization pattern of 011110.
A graph showing the relationship between the reception timing shift and the number of pits that match the synchronization pattern when 1011001000 is selected. Figure 4 is a block diagram of a conventional synchronization protection circuit. Figure 5 is the synchronization of Figure 4. 5 is a timing chart showing the operation of the protection circuit. 1... Synchronous input detection circuit 2... Imper 3... Mismatched pulse counter 4...
Coincidence pulse counter 5...Flip-flop 6...AND gate 7...OR gate 8...E pattern detection circuit 9...・・・The same road as the gate.

Claims (1)

[Claims] A synchronization protection circuit using a contention counter includes a detection means for detecting a mismatch pattern that differs by several bits from a synchronization pattern used for a synchronization signal, and a detection means for detecting a mismatch pattern that is different by several bits from a synchronization pattern used for a synchronization signal, and a detection means that normally counts input mismatch pulses. 1. A synchronization protection circuit comprising gate means that outputs the mismatch pulse to a counter that detects the mismatch pattern, but does not output the mismatch pulse to the counter when the mismatch pattern is detected by the detection means.