JPH05260038A - Block synchronizing selection control circuit - Google Patents

Abstract

PURPOSE:To perform the exact selection control of block synchronization with a little count values. CONSTITUTION:This circuit is provided with an inhibit pattern detection circuit 2 to detect an inhibit pattern from received data, first counter 7 to count the number of generated inhibit patterns, and second counter 8 to count intervals to generate the inhibit patterns and when the first counter 7 carries out before the second counter 8 carries out, a clock input to a ring counter 11 to output a block synchronizing pulse by an inverter 9 is stopped for one clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit in a system for transmitting a combination of time slots of a continuous data string as a unit of information by using an optical fiber or the like, and more particularly to an accurate block synchronization on the receiving side. It concerns selection technology.

[0002]

SUMMARY OF THE INVENTION According to the present invention, when a digital signal is transmitted on a transmission line such as an optical fiber using a block code having a combination of a plurality of time slots as a unit of information,
Even if a code error occurs on the transmission line, it relates to a block synchronization selection control circuit for receiving information accurately on the receiving side.If the block synchronization is not correctly selected on the receiving side, or if a code error occurs on the transmission line. The occurrence interval and the occurrence number of a specific pattern that occurs when they occur are counted, and the block synchronization is controlled based on the counting result. By doing this, it is possible to select the correct block synchronization reliably and in a short time when the block synchronization is not correctly selected, and to maintain the correct block synchronization even in the situation where an error occurs on the transmission path. It was made possible.

[0003]

2. Description of the Related Art The information transmission method using a combination of time slots of consecutive data strings as a unit can increase transmission capacity or secure timing components, but on the other hand, many code errors occur on the transmission path. In this case, if the block synchronization is lost on the receiving side, the transmission may be broken.

In order to improve this point, conventionally, for example, a period for inspection is determined in advance, the number of prohibited patterns generated is counted within this period, and when this number exceeds a certain threshold value. , It is determined that the block synchronization is not in the correct state, and the state is changed to another state.

[0005]

However, if the frequency of occurrence of code errors on the transmission path is high, the inspection period must be set long in order to accurately perform block synchronization selection control using the above method. In that case, there is a drawback that the control time becomes long. In addition, when the generation of the prohibited pattern extends over two inspection periods, the number of generated prohibited patterns is underestimated.

The present invention has been made to solve such a problem, and an object thereof is to perform accurate selection control of block synchronization with a small count value.

[0007]

In order to achieve the above object, the present invention provides data transmitted by using a combination of k (k is an integer of 2 or more) time slots in a continuous data string as a unit of information. Upon reception, detection means for detecting a specific pattern that does not occur in a correct combination of time slots in received data but occurs in an incorrect combination of time slots, and the occurrence of the specific pattern detected by the detecting means. The present invention is characterized by comprising counting means for counting the number of occurrences and the occurring intervals, and control means for selectively controlling the correct block synchronization based on the counting result of the counting means.

[0008]

According to the present invention, when the block synchronization is not correctly selected on the receiving side, or when a code error occurs on the transmission path, the interval and the number of occurrence of a specific pattern are counted, and The block synchronization is controlled based on the counting result.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, a case where a 2-digit binary signal is encoded into a 2-digit ternary (-0, 0, +1) signal and transmitted will be described below. The present invention is not limited to this code.

There are four kinds of bit patterns of the 2-digit binary signal, 00, 01, 10 and 11, and these bit patterns are converted into 2-digit ternary signals as shown in Table 1 for transmission.

[0011]

[Table 1]

As can be seen from Table 1, the transmission codes do not include codes (+1, +1), (0, 0), (-1, -1) (hereinafter, these are referred to as prohibited patterns). .. It is assumed that a bit pattern of 00, 11, 01, 10 is continuously transmitted using this transmission code.

At this time, if the correct block synchronization is selected on the receiving side, (-1, + 1) (+ 1, -1)
It is received as (-1,0) (+1,0) and is decoded into a correct bit pattern based on the rules of Table 1.

On the other hand, if wrong block synchronization is selected on the receiving side, (x, -1) (+1, +1) (-
1, -1) (0, +1) (0, x) is received, the prohibition pattern is detected, and the original bit pattern cannot be obtained even if it is decoded, which causes a failure in transmission.

Further, even when the correct block synchronization is selected on the receiving side, the prohibition pattern may be detected due to a code error on the transmission path. In the above transmission example, a code (-
Suppose that (1,0) is incorrect to (-1, -1). The code string received at this time is (-1, + 1) (+ 1, -1) (-
(-1, -1) (+1,0), and the prohibited pattern (-1,
-1) appears, but other codes are correctly decoded.

Therefore, it is necessary to accurately determine whether the prohibition pattern detected on the receiving side is caused by incorrect selection of the time slot on the receiving side or due to an error on the transmission path.

The present invention is intended to surely make this judgment with a small count value, and one embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a serial-parallel converter, 2
Is an inhibition pattern detection circuit, 3, 4 and 10 are AND gates, 5 and 6 are OR gates, 7 and 8 are programmable counters with reset, 9 is an inverter, and 11 is a ring counter.

The serial-parallel converter 1 converts the input data into a parallel signal at the timing of the block synchronization signal pulse from the ring counter 11. When the timing of this block synchronization signal pulse is incorrect, the prohibited pattern is detected even if the received data is correct, and the Q output of the prohibited pattern detection circuit 2 becomes "H". Further, when the prohibited pattern is not detected, the inversion Q of the prohibited pattern detection circuit 2 is performed.
The output becomes "H". In order to count these numbers in the subsequent first and second counters 7 and 8 in block code units, AN
The D gates 3 and 4 are used to AND the block synchronizing signal pulse.

The first counter 7 is for counting the number of prohibited patterns. The second counter 8 counts the number of non-prohibited patterns. Appropriate values are selected for the count values N1 and N2 of the first and second counters 7 and 8 depending on the block code used and the code error rate characteristic of the transmission path. When the prohibition pattern occurs, the output of the AND gate 3 becomes "H", and the count value of the second counter 8 is reset to 0 at the same time as being counted by the first counter 7. Further, when the non-prohibited pattern occurs, the output of the AND gate 4 becomes "H" and is counted by the second counter.

Assuming that the preset value of the second counter 8 is N2, the carry output of the second counter 8 becomes "H" only when N2 non-prohibited patterns are continuously generated, and the first and second counters 7 are , 8 are reset to 0. When the number of generated prohibited patterns reaches N1 when the number of consecutive non-inhibited patterns is less than N2, the first
The Carry output of the counter 7 becomes “H”, the first counter 7 is reset to the count value 0, the output of the inverter 9 becomes “L”, the clock input to the ring counter 11 is stopped for one clock, and the ring counter is stopped. 11
Carry output, that is, the phase of the block synchronization signal pulse changes to a state delayed by one clock.

FIG. 2 shows a time chart of the circuit operation when the block synchronization signal is incorrect. When the block synchronization signal is incorrect, the inhibition pattern may be generated successively within a certain period (in this case, N2 is equivalent to the number of pulses indicating the number of continuous non-inhibition patterns). In this state, the carry output of the second counter 8 does not become "H", so the first counter 7 continues the counting operation without being reset. The count value of the first counter 7 is N
When it reaches 1, the carry output of the first counter 7 becomes "H", and this signal delays the phase of the block synchronization signal pulse by one clock.

FIG. 3 shows a time chart in the case where the block synchronization signal is correct, but an inhibition pattern occurs on the transmission line due to a code error. Due to an error on the transmission path, even if two consecutive prohibition patterns are detected with a non-prohibited pattern occurrence interval of less than N2, immediately after that, N2 consecutive non-prohibited patterns result in Ca of the second counter 8.
Since the rry output becomes “H” and the count value of the first counter 7 is reset to 0, the carry output of the first counter 7 does not become “H” and the phase of the block synchronization signal pulse does not change.

[0024]

As described above, the present invention can be realized with a small count value of the counter because the block synchronizing signal selection control operation is performed based on the number and interval of occurrence of a specific pattern. Further, it is possible to realize a block synchronization selection control circuit according to the block code used and the characteristics of the transmission path.

[Brief description of drawings]

FIG. 1 is a block diagram of a block synchronization selection control circuit according to the present invention.

FIG. 2 is a diagram showing a time chart of the operation when the block synchronization signal is incorrect.

FIG. 3 is a diagram showing a time chart of an operation in which a block synchronization signal is not erroneously selected even when an error occurs on a transmission line.

[Explanation of symbols]

 1 Serial-parallel converter 2 Prohibited pattern detection circuit 3, 4, 10 AND gate 5, 6 OR gate 7, 8 Programmable counter with reset 9 Inverter 11 Ring counter

Claims (2)

[Claims] 1. In a continuous data string, k (k is 2)
A specific pattern that does not occur in the correct combination of time slots in the received data when receiving data transmitted with a combination of time slots of (integer) Detecting means, a counting means for counting the number of occurrences and an interval of occurrence of the specific pattern detected by the detection means, and control for selectively controlling correct block synchronization based on the counting result of the counting means. And a block synchronization selection control circuit. 2. The control means sets the count value of the number of occurrences of the specific pattern to another predetermined value when the count value of the interval at which the specific pattern occurs in the counting means is less than a predetermined value. 2. A means for changing the block synchronization to another state when the value is reached.
The block synchronization selection control circuit described in 1.