JPH06164571A - Synchronism detection circuit - Google Patents

Abstract

PURPOSE:To establish word synchronism from parallel data and parallel clocks before low speed word synchronism by taking the AND of the storage output of the presence or absence of the realization of an auxiliary code relation and the corresponding bits of exclusive OR gates. CONSTITUTION:A serial transmission signal is converted into a parallel signal A without being word-synchronized in an S/P conversion circuit, and it is inputted to a synchronism detection circuit. The signal A is latched by the parallel clock B synchronized with parallel data in the latch means 1, and it is set to be the signal of the (K+2) bit of C1-Ck+1. The signals C0-Ck+1 are inputted to the (K+1)-number of exclusive OR gates 2 recognizing the auxiliary relation of the adjacent bits, and the result is supplied to the (K+1)-number of latch means 4 through AND gates 3. All the bits of the means 4 are preset to '1' by a timing signal. Thus, a pair of bits where the auxiliary code relation is continuously realized for a prescribed period are detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detection circuit in serial transmission using code conversion of digital signals by complementary codes.

[0002]

2. Description of the Related Art In the serial digital transmission system,
Various methods are used to prevent the same code continuation for a long period of time, and as one of them, a method of inserting the complementary code between original data is known. In the transmission method using the complementary code, it is necessary for the receiving side to establish the word synchronization by using the complementary code. As a method for this, as shown in FIG. There is a method of inputting to the shift register 1 and monitoring the complementary sign relation of the bits separated by (L-1) bits at every (K + 1) clock by the exclusive OR gate 3. In addition, in FIG.
2, 6, 9, and 12 are gate circuits, 4 is a 1 / (K + 1) frequency dividing circuit, 7 is a 1 / M frequency dividing counter, 8 is a 1 / P frequency dividing counter, 10 and 13 are flip-flop circuits, and 11 is It is a shift register (see Japanese Patent Laid-Open No. 62-48144).

[0003]

However, in this method, since the synchronous circuit has a portion for handling serial data and serial clock, when considering the LSI of the synchronous circuit, a very high speed process is used. However, the LSI is expensive and consumes a large amount of power. This tendency is particularly noticeable when a complex algorithm is adopted in the synchronization protection part.

[0004]

In order to solve such a problem, according to the present invention, first latch means for latching parallel data before word synchronization, an output of the first latch means and the parallel data are provided. Out of consecutive (K + 1 + L) bits on the serial data, the (K + 1) exclusive OR gates for checking the complementary sign relation of the bits separated from each other by (L-1) bits and the complementary sign relation A second (K + 1) -bit latch means for storing the presence / absence of the condition, and a logical product of the output of the second latch means and the corresponding bits of the exclusive OR gate is input to the second latch means. (K + 1) AND gates and preset means for setting all the bits of the second latch means to 1.

[0005]

By the above means, according to the present invention, the high-speed serial clock and serial data are not directly handled,
It is possible to establish word synchronization from low-speed parallel data before word synchronization and a parallel clock.

[0006]

EXAMPLE An example of the present invention will be described below. FIG. 1 shows an embodiment of the synchronization detection circuit in the case where L = 1, that is, the complementary code of the least significant bit is inserted before it and transmitted. FIG. 2 shows a schematic block diagram of the entire synchronizer using this synchronization detecting circuit, and FIG. 3 shows the signal contents of the synchronizer when K = 6 and L = 1 as an example.

The serial transmission signal P is sent to the S / P conversion circuit 10
Is converted into a (K + 1) -bit parallel signal A without word synchronization at
Input to 1. In FIG. 1, in the synchronization detection circuit 11, the parallel signal A is latched by the latch means 1 at the timing of the parallel clock B synchronized with the parallel data, whereby the (K + 2) bits of C _{0 to} C _{k + 1} are latched. The signal is obtained. The synchronization detection circuit 1 is a latch means 1.
It is composed of a and 1b. The signals C _{0 to} C _{k + 1} are
It is input to (K + 1) exclusive-OR gates 2 for confirming the complementary relationship of adjacent bits, and the result is (K +).
It is latched by (K + 1) latch means 4 via 1) AND gates 3.

The timing circuit 5 generates the timing signal F once every N cycles of the parallel clock B, and the timing signal F sets all the bits of the latch means 4. After that, since the logical product of the output of the latch means 4 and the output of the exclusive OR gate 2 for confirming the complementary sign relation is latched by the latch means 4 every parallel clock, immediately before the timing of the next timing signal F. Then, during the N cycles of the parallel clock, only the output of the latch means 4 corresponding to the bit pair for which the complementary sign relationship is always established becomes 1 and the other outputs become 0.

Therefore, the complementary code position in the parallel data can be known by using the complementary code position detection output D of the latch means 6 which latches the output of the latch means 4 at the timing immediately before the timing signal F. ,
After the synchronization protection circuit 12 performs the synchronization protection of the complementary code position detection output D, the barrel shifter 13 restores the word synchronization and the parallel data T with the word synchronization can be obtained.

[0010]

As described above, according to the present invention, the word synchronization can be established from the parallel data and the parallel clock before the low-speed word synchronization without directly handling the high-speed serial clock and serial data. Therefore, when considering an LSI, it is sufficient to use a high-speed process only for the S / P conversion portion, and all the other blocks including the synchronization detection circuit can be realized by a low-speed process. Therefore, an inexpensive and low power consumption synchronizer can be configured. Further, the parallel signal after recovery of synchronization is usually subjected to another processing such as multiplexing and demultiplexing, and it is possible to include a synchronous circuit portion in an LSI that performs these processing.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a synchronization detection circuit in the case where a complementary code of a least significant bit is inserted before and transmitted in the present invention.

FIG. 2 is a block diagram of a synchronization device using the synchronization detection circuit of the present invention.

FIG. 3 is an explanatory diagram of signals of respective parts of the synchronizer shown in FIG.

FIG. 4 is a configuration diagram showing an example of a conventional synchronization detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 latch means 2 exclusive OR gate 3 AND gate 4 latch means 5 timing generation circuit 6 latch means 10 S / P conversion means 11 sync detection circuit 12 sync protection circuit 13 barrel shifter

Claims (1)

[Claims] 1. A K-bit (K is an integer of 1 or more) is defined as one word, and a complementary code of the L-th (L is an integer of 1 or more and K or less) information is inserted and serially converted and transmitted. In the transmission method, first latch means for latching parallel data before word synchronization, continuous (K + 1 +) on serial data among the output of the first latch means and the parallel data.
L) bits are taken out and (K + 1) exclusive-OR gates for checking the complementary sign relation of the bits separated from each other by (L-1) bits and the existence of the complementary sign relation are stored (K + 1). The second latch means for the bit, and (K + 1) AND gates which take the logical product of the output of the second latch means and the corresponding bits of the exclusive OR gate and are the input of the second latch means. A preset circuit for setting all bits of the second latch circuit to 1; and a timing circuit for supplying a preset timing signal to the preset circuit at regular intervals. 1 for every bit in the latch means
The sync detecting circuit detects a bit pair for which a complementary sign relationship is established continuously for a certain period of time by setting to.