JPS636942A - Data receiving circuit - Google Patents

Abstract

PURPOSE:To receive NRZI code type data by detecting a latch output with an inverting clock from an inverting means to invert a clock signal. CONSTITUTION:An FF32 latches the output of an exclusive 'or' gate (XOR) 33 at every leading of a clock (b), inverts this and outputs it. In such case, since the latching of the data of FF31 and 32 or an XOR output is respectively executed by using the same clock, the H level output of the XOR 33 is latched with an H level by the clock before the trailing thereof. By inverting and outputting a synchronizing clock, (b) with an inverter 34, the clock is delayed by an 1/2 period, and by receiving the inverting output (e) of the FF32 with an LSL 35 for data communication with this as a new clock (f), an NRZI code is converted to an NRZ code and can be inputted to the LSI 35 for data communication. Thus, the data of the NRZI code can be received.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data receiving circuit used, for example, in a transmission path monitor device that receives and displays serial data.

[Conventional technology]

Generally, the data receiving circuit of a serial transmission line monitor device is known to use a commercially available communication LSI (Large Scale Integrated Circuit), and is of a synchronous type.

It is required to be compatible not only with the asynchronous method but also with a wide range of other methods. Due to the demand for faster and more reliable transmission data, recently Q HDL has been introduced.
C (Highlevel Data Link Con
Trol) procedure or 5DLC (5Ynchrono
Transmission based on the US Data Link Control (US Data Link Control) procedure is common, and in particular the 5DLC procedure is based on the SNA (System Network Control) procedure.
Since the protocol, which is a hierarchical transmission format called ``Transmission Architecture'', is in full use, it is predicted that it will continue to be widely adopted in the future.

-On the other hand, communication LSIs that are compatible with a variety of protocols have become available, making it possible to use a single LSI to support synchronous, start-stop synchronous, or HDLC procedures. It's coming.

[Problem that the invention seeks to solve]

However, although communication LSIs have become multi-protocol compatible, the number of data formats that can be received is N.
Most of them are of the RZ (Non Return to Zero) type. For example, in the 5DLC procedure described above, %RZ I (
NonReturn to Zero Inversi
On) type data is handled, so there is a problem in that commercially available communication LSIs cannot monitor it.

Therefore, an object of the present invention is to enable a data receiving circuit using a commercially available communication LSI to receive NRZI code type data as well.

[Means for solving problems]

A storage means that receives NRZ I code type data and a clock signal and stores the state of this data 1/2 clock before, and detects that the input data has changed and outputs a 1/2 clock width signal. A detecting means, a latch means for latching the state immediately before input data changes, and an inverting means for inverting a clock signal are provided, and the latch output is detected using the inverted clock from the inverting means.

[Effect]

Communication LSI that can only receive data in NRZ code format
By adding each of the above-mentioned means to the previous stage, it is possible to receive data in the K, D, and NRZI code formats, thereby expanding the scope of its application.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a block diagram showing a specific example of a serial transmission line monitor device to which the present invention is applied. It is.

First, explanation will be given starting from FIG. In addition, in the figure, l is a processing unit (CPU), 2 is an operation keyboard, 3 is a data receiving circuit, 4 is an internal memory device, 5 is an internal display device, 6 is a display output circuit, 7 is an external display device, 8 is an external memory input/output circuit, and 9 is an external memory device.

The CPU 1 receives serial transmission data via the data receiving circuit 3. The received data is subjected to predetermined data processing according to the contents set as is or by pressing a key included in the operation keyboard 2 in advance), and is stored in an internal memory device 4 consisting of a random access memory (RAM) or the like. . Next, the CPU 1 reads the data from the internal memory device 4 and performs predetermined processing so that it becomes display data, either as is or according to a protocol or data format previously set by pressing a key included in the operation keyboard 2. , internal display device 5 or display output circuit 6fr: Output to external display device 7 through. The CPU 1 also has a surface for reading data from the internal memory device 4 and outputting it to an external memory device 9 such as a cassette tape recorder via an external memory input/output circuit 8.

Next, reference is made to FIG. This specifically shows the data receiving circuit 3 shown in FIG.
) 31, 32, and Exclusive or Gate (XO
R) 33, inverter (INV) 34, and communication LS
It is composed of r35 and resistors R and %R. FIG. 2 shows the timing of each part of this data receiving circuit 3 when data I of the KNRZI code and a clock are input. Note that the NRZI code is "1'" as shown in Figure 2 (c) K.
This is an encoding method in which the level does not change when 0, and the level is inverted only when 0.

Assuming that the FF 31 latches data every time the clock rises as shown in FIG. 2(b), its output C has the timing shown in FIG. 2(c). Exclusive OR Gate (XOR) 33 is FF
Since we take the exclusive OR of '31 and data input a, FF
If the output of 31 and the level of data input a are different, then iυ
If "0" is the data input, it outputs "H". As a result, the output d of XoR33 has the timing shown in Figure 2).FF32 outputs X0R3 at every rising edge of clock b.
Since the output of No. 3 is latched, inverted, and output, the timing is as shown in FIG. 2 (E). At this time, FF31,
32 data or XOR outputs are latched using the same clock, so XOR33
The H level output of is latched at H level by the clock before it falls. Then, by inverting and outputting the synchronized clock b by the inverter (INV) 34, the clock is delayed by 1/2 cycle as shown in Fig. 2 (f), and this is used as a new lock (f) to be inverted and output from the FF 32. By receiving e on the data communication LSI 35,
The NRZI code can be converted into the NRZ code and input to the data communication L135, making it possible to receive data in the NRZI code. In addition, the data for the NR2 model is
It goes without saying that the data is received by the direct communication LSI '35 using the clock b, and that the received data is processed as explained in FIG.

As described above, by adding a simple circuit to the front stage of the data communication LSI f), it becomes possible to monitor data in the NRZI code format.

〔Effect of the invention〕

According to this invention, by simply adding a simple circuit to the front stage of a data communication LSI that cannot receive data in the NRZI code format, data in the NRZI code format can also be received, making it possible to monitor 5DLC measures. This brings about the advantage that the scope of application of the monitoring device can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a block diagram showing a specific example of a serial transmission line monitor device to which the present invention is applied. It is. Description of symbols 1... Arithmetic processing unit (CPU), 2... Keyboard, 3... Data receiving circuit, 4... Internal memory device,
5... Internal display device, 6... Display output circuit, 7...
・External display device, 8...external memory manual/output circuit,
9... External memory device, 31.32... Flip-flop (FF'), 33... Exclusive OR gate (XOR), 34... Inverter, 35... Communication LSI.

Claims (1)

[Scope of Claims] A data receiving circuit that receives serial data in NRZ code format, comprising: a storage means for storing input data in NRZI code format in synchronization with a clock signal; a detection means for outputting a signal, a latch means for latching the state immediately before the input data changes, and an inversion means for inverting the clock signal, and the output from the inversion means is used to detect the output of the latch means. A data receiving circuit is characterized in that it can also receive data in NRZI code format by detecting .