JPH0242821A - Decoding device - Google Patents

Abstract

PURPOSE:To automatically correspond to any one of plural recording systems and to attain normal decoding by providing a delay type FF, an exclusive OR gate, a deciding circuit and a selecting circuit, etc., and discriminating the recording system from an input code train itself. CONSTITUTION:The continuity of '1' in the code train, which is inputted from a code train input edge 1, is decided by a deciding circuit 8 and when the '1' is not continuous, 0 is outputted as an output signal (d). Then, when the '1' is continuous, 1 is outputted as the signal (d). The input code train is housed to a delay type FF3 by a clock, which is inputted from a clock input terminal 2 and a signal (a) to be delayed by one clock is outputted. Then, the signal (a) and 0 are selectively outputted as an output signal (c) by a selecting circuit 7 in correspondence to the signal (d). An exclusive OR gate 4 outputs exclusive OR between the input code train and output signal (c) of the circuit 7 as a signal (b). Thus, in the case of any one of an NRZ(non-return to zero) system and an NRI(non-return to I system), as the signal (b), a wholly same signal can be obtained. Then, operation automatically corresponds to the respective systems and the normal decoding can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital data decoding device that converts a binary encoded data string into another data string according to a predetermined rule.

2. Description of the Related Art In recent years, there has been active development of devices for recording and reproducing binary encoded digital data on various media, and in particular, development of recording and reproducing devices for optical discs has been very notable.

When recording digital data on a medium - for boat fishing,
It is extremely rare to apply the original data such as "0" and "1" as is, but by performing some kind of code conversion and recording, the frequency band of the recorded signal is limited, or when playing back, it is possible to create a signal that is synchronized with the data from the playback signal. Efforts are made to make extraction easier. Various methods have been proposed for this code conversion, and one of them, for example, is the patent publication
There is a run-length limited code conversion as shown in No. 74, which is currently commonly used in optical disk recording and reproducing devices.

Here, code conversion refers to generating a code string corresponding to an original digital data string according to the following rules, and run-length restriction refers to the coded bit string, that is, the "1" and "1" in the code string. '' is limited to a minimum of d and a maximum of k. Such a run-length limited code is expressed as a (d,k) RLL code.

The earlier patent publication "Sho 58-5774" has d=2. ni=
A (2.7) RLL code of 7 is shown, and the correspondence between data and codes in this case is as shown in the table below.

Through the code conversion described above, each original data string is recorded as a corresponding code string, and upon reproduction, the code string is decoded into an original data string.

However, even when the same code conversion is used, there are two types of actual recording and reproduction on a medium: In other words, the NR records "1" and "0" of the code string in terms of levels.
There are the Z (non-return to zero) method and the NRZI (non-return to zero eye) method, which records "1" in a code string as a change in state. In Figure 9, the original data string ro1
0001110" and the code string corresponding to NRZ, N
Recording/reproducing signals and synchronization clocks according to each RZI system are shown. As is clear from Figure 9, the recording/reproduction signals are completely different between NRZ and NRZI, and in the case of the NRZ method, decoding is easily done by directly connecting it to a decoding circuit that conforms to the specified conversion law, but in the case of the NRZI method In this case, it is necessary to identify the code string as a preprocessing for decoding.

An example of a conventional decoding device for the NRZI system will be described below with reference to the drawings. FIG. 7 shows the configuration of a decoding device for the conventional NRZI system, and FIG. 8 shows signal waveforms at various parts. In FIG. 7, 1 is a code string input terminal, 2 is a periodic clock input terminal, 3 is a delay type flip-flop, 4 is an exclusive OR gate, 5 is a decoding circuit, and 6 is a data output terminal. a is the output signal of the delay type flip-flop 3, and b is the output signal of the exclusive OR gate 4.

The operation of the conventional decoding apparatus for the NRZI system configured as described above will be explained.

First, as shown in FIG. 8, when an input code string and a clock synchronized with the code string are applied to the delay type flip-flop 3 in FIG. 7, its output is shown as a in FIG. The signal is output with a delay of one clock. Next, the output of the delay type flip-flop 3 and the input code string are input to the exclusive OR gate 4 as shown in FIG. 7, and the output is as shown by b in FIG. can be identified as a conversion code string. Therefore, the seventh
As shown in the figure, by inputting the output of the exclusive OR gate 4 and the clock to the decoding circuit 5, the original digital data string is output as shown in FIG. 8 according to the prescribed code conversion law, and the decoding is completed.

Problems to be Solved by the Invention However, the above configuration is compatible only with the NRZI system and cannot perform normal decoding with the NRZ system. That is, as shown in FIG. 9, since the recording and reproducing signals for NRZ and NRZI are completely different, the decoding device must deal with each separately or rely on circuit switching.

Furthermore, the circuit switching can be done by the operator if the recording method is NRZ.
Either NRZI or NRZI is determined and set, or it is set based on recording system discrimination information stored in a special area on the medium, as in the case of optical discs, for example. In either case, there is a problem in that special information other than the input code string is required.

In view of the above problems, the present invention provides a decoding device that automatically supports any recording format and enables normal decoding by determining the recording format (NRZ or NRZI) from the input code string itself. This is what we provide.

Means for Solving the Problems In order to solve the above problems, the decoding device of the present invention includes a circuit that determines the recording method, a circuit that selects input to the exclusive OR gate according to the determination result, .

It is equipped with a delay type flip-flop that delays an input code string by one clock and outputs it, and a circuit that decodes according to a prescribed rule.

Operation The present invention, with the above-described configuration, can determine the recording method from the input code string itself, and select the signal sequence corresponding to the recording method according to the result, so that it can be used for either the NRZ method or the NRZI method. In addition to enabling normal decoding operation,
There is no need for any special information other than the input code string to determine the recording method.

Embodiment Hereinafter, a decoding device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a decoding device in an embodiment of the present invention. In FIG. 1, 1 is a code string input terminal, 2 is a synchronous clock input terminal, 3 is a delay type flip-flop, and 4
5 is an exclusive OR gate, 5 is a decoding circuit, and 6 is a data string output terminal, which is the same configuration as the conventional example. 7 is a selection circuit, 8 is a determination circuit, and 9 is a reset signal input terminal. a is the output signal of the delay type flip-flop 3, b is the output signal of the exclusive OR gate 4, C is the output signal of the selection circuit 7, and d is the output signal of the determination circuit 8.

The decoding device configured as described above will be explained using FIG. 1, FIG. 2, and FIG. 3. Figure 2 shows the signal waveforms of each part of the configuration shown in Figure 1 when a signal according to the NRZ system is given as an input code string, and Figure 3 shows a signal according to the NRZI system when a signal according to the NRZI system is given as an input code string. 2 shows signal waveforms of each part of the configuration shown in FIG. 1 in the case of FIG.

First, in FIG. 1, it is assumed that the determination circuit 8 is initialized by a reset signal inputted from the reset signal input terminal 9 at least at the time of starting decoding, and the output signal d outputs "0". It is also assumed that the reset operates with negative logic. Next, the determination circuit 8 determines the continuity of "1" contained in the code string input from the code string input terminal 1. That is, as is clear from FIG. 9 above (in code conversion with run-length restrictions, "1"s do not exist consecutively in the code string in the case of recording and reproducing according to the NRZ system).

Conversely, in the case of the NRZ system, "1" always lasts only one cycle of the synchronization clock. On the other hand, in the case of recording and reproducing according to the NRZI method, "1" always lasts for two cycles or more of the synchronization clock. Therefore, by determining the continuity of "1"s included in the input code string, it is possible to determine whether the code string is based on the NRZ method or the NRZI method.

Based on the above operating principle, the determination circuit 8 outputs "0" as the output signal d when "1"s are not consecutive in the input code string, that is, when the NRZ system is used. Further, the determination circuit 8 determines that if "1" continues in the input code string, that is, NR
When using the ZI method, "1" is output as the output signal d. The above is as shown as the signal waveform d in FIGS. 2 and 3.

On the other hand, the input code string is stored in the delay type flip-flop 3 according to a clock synchronized with the code string inputted from the clock input terminal 2, and becomes the output signal a as a signal delayed by one clock. Next, the selection circuit 7 selectively outputs the output signal a of the delay type flip-flop 3 and "0" according to the output signal d of the determination circuit 8. That is, when the signal d is "o", the selection circuit 7 outputs "o" as the output signal C, and when the signal d is "1", the selection circuit 7 outputs the output signal a of the delay type flip-flop 3 as the output signal C. Select and output. Subsequently, the exclusive OR gate 4 outputs the exclusive OR of the input code string and the output signal C of the selection circuit 7 as a signal. Based on the above operation, it can be seen that exactly the same signal is obtained as the output signal of the exclusive OR gate in both the case of the NRZ method shown in Fig. 2 and the case of the NRZI method shown in Fig. 3. .

Therefore, in FIG. 1, the output signal of the exclusive OR gate 4 is decoded into original data by passing through the decoding circuit 5 according to the prescribed decoding conversion rule, and is outputted to the output terminal 6 as a data string. Become.

As described above, according to this embodiment, "
By providing a circuit that determines the continuity of "1" and a circuit that selects a signal to be input to one side of the exclusive OR gate according to the determination result, normal decoding is possible regardless of the recording/reproducing method. At the same time, it is possible to eliminate the need for any special information other than the input code string for determining the recording/reproduction method.

A specific embodiment of the determination circuit according to the present invention will be described below with reference to the drawings. FIG. 4 shows the configuration of a specific embodiment of the determination circuit. In the figure, 81 is a first delay type flip-flop, 82 is a second delay type flip-flop,
83 is a NAND gate, and 84 is an RS flip-flop.

The operation of the determination circuit configured as described above will be explained below. In FIG. 4, the input code string is sequentially stored in cascade-coupled delay type flip-flops 81 and 82 in synchronization with a clock. Next, delay type flip-flops 81 and 8
A NAND gate 83 outputs the negative logical product of each output of 2. As a result, the output of the NAND gate 83 becomes "o" when "1" continues for at least two clocks in the code string, and becomes "1" otherwise. The RS flip-flop 84 is reset by a reset signal before starting decoding and outputs r□ as an output d. Next, if "IJ" is not consecutive in the code string, that is, in the case of the NRZ system, the NAND gate 83 maintains "1", so the RS flip-flop 84 is not set, and the output d is "
0" is maintained. In addition, when "1" continues in the code string, that is, in the case of the NRZI method, the NAND gate 83 outputs "0", and the RS flip-flop 84 is set and outputs rl as the output d. It holds "1" until it is initialized again by a reset signal. As described above, with this configuration, it is possible to determine the recording/reproduction method from the input code string itself.

Note that in the configuration shown in FIG. 4, rl for two consecutive clocks included in the code string is determined, but it is also possible to determine continuous rl for three or more clocks. In that case, it can be easily realized by setting the number of cascaded delay flip-flops to three stages and using a three-power element as the NAND gate.

Next, regarding a specific embodiment of the selection circuit in the present invention,
This will be explained with reference to the drawings. FIG. 5 shows the configuration of a specific embodiment of the selection circuit according to the present invention, in which 3 is a delay type flip-flop and 4 is an exclusive OR gate, which is the same as the embodiment of the present invention shown in FIG. The composition is as follows. 71 is A
This is an ND gate, and in this embodiment, the selection circuit is realized only by the AND gate 71.

In FIG. 5, an AND gate 71 outputs the logical product of the output signal a of the delay type flip-flop 3 and the determination circuit output d as an output C. Therefore, the output d of the determination circuit is "0"
In the case of , that is, when the input code string depends on the NRZ method, A
The output of the ND gate 71, that is, the output C of the selection circuit is "0".
”, and when the output d of the determination circuit is “1”, that is, when the input code string is based on the NRZI method, the AND gate 71
, that is, the output C of the selection circuit is the same as the output signal a of the delay type flip-flop 3. As described above, the selection circuit constituted by the AND gate 71 can select between "0" and the output signal a of the delay type flip-flop 3 in accordance with the output signal of the determination circuit.

FIG. 6 shows the configuration of another specific embodiment of the selection circuit according to the present invention, in which 3 is a delay type flip-flop and 4 is an exclusive OR gate, which is similar to the configuration in FIG. 1. .

72 is an analog switch with one circuit and two contacts.

In FIG. 6, one input of the analog switch 72 is given the output signal a of the delay type flip-flop 3, and the other input is connected to the circuit ground and given a signal of "0". There is. Further, the output signal d of the determination circuit is given as a signal for controlling the connection state of the switch.

Therefore, the analog switch 72 determines that the output d of the determination circuit is "
Depending on whether it is "0" or "1", the output signal C of the selection circuit is selectively switched between "O" and the output signal a of the delay type flip-flop.

Effects of the Invention As described above, the present invention includes a delay type flip-flop, an exclusive OR gate, a circuit for determining the continuity of "1" contained in an input code string, and a By providing a circuit that selects the output signal of the delay type flip-flop and "0", if the code conversion rules are the same, it can be automatically determined regardless of the recording/reproduction method, and normal decoding can be performed. The present invention provides an excellent decoding device that does not require any special information for determining the recording/reproducing method in order to determine the recording/reproducing method from the input code string itself.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a decoding device in an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams showing signals of each part in FIG. 1, and FIG. 4 is a diagram of a determination circuit in the present invention. A block diagram of a specific embodiment, FIG. 5 is a block diagram of a first specific embodiment of the selection circuit in the present invention, and FIG. 6 is a block diagram of a second specific embodiment of the selection circuit in the present invention. Fig. 7 is a block diagram of a conventional decoding device, Fig. 8 is a waveform diagram showing various signals of Fig. 7, and Fig. 9 is a waveform diagram for explaining code conversion and recording/reproducing method. be. 1... code string input end, 2... clock input end, 3... delay type flip-flop, 4...
...Exclusive OR gate, 5...Decoding circuit, 6...Data string output end, 7...Selection circuit, 8... Judgment circuit, 9... Reset signal input terminal. Name of agent: Patent attorney Shigetaka Awano

Claims (4)

[Claims] (1) A delay type flip-flop that stores a binary code string based on run-length limited encoding using a clock synchronized with the code string; a determination circuit that inputs a code string and a clock and determines the continuity of binary codes "1" included in the code string; and a determination circuit that determines the continuity of binary codes "1" included in the code string; A selection circuit that selects "0"; a logic gate that outputs the exclusive OR of the output of the selection circuit and the code string; and a logic gate that outputs the exclusive OR of the output of the selection circuit and the code string; A decoding device comprising: a decoding circuit for decoding. (2) The determination circuit includes two stages of delay type flip-flops connected in cascade, a logic gate that outputs the negative AND of the output of each delay type flip-flop, and a reset signal that is set by the logic gate output signal. 2. The decoding device according to claim 1, further comprising a set/reset type flip-flop which is reset by a set/reset type flip-flop. (3) The decoding device according to claim 1, wherein the selection circuit is a logic gate that outputs an AND of the output of the delay type flip-flop and the output of the determination circuit. (4) The decoding device according to claim (1), wherein the selection circuit is an analog switch that switches between the output of the delay type flip-flop and the binary code "0" according to the output state of the determination circuit.