CA1140998A

CA1140998A - Dc free encoding for data transmission including limited look-ahead means

Info

Publication number: CA1140998A
Application number: CA000335059A
Authority: CA
Inventors: Jerry W. Miller; Paul J. Rudnick
Original assignee: Ampex Corp
Current assignee: Ampex Corp
Priority date: 1978-10-05
Filing date: 1979-09-05
Publication date: 1983-02-08
Also published as: IT7950446A0; FR2438388B1; DE2940488A1; IT1164050B; JPS55159659A; BE879124A; DE2940488C2; GB2032228A; FR2438388A1; NL7907383A; GB2032228B

Abstract

ABSTRACT OF THE DISCLOSURE

A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., O's, are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., l's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed. The onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission is detected by counting first bit states and producing a first indicating signal when the count is of parity indicating such sequence, and in response to the first indicating signal, a current bit and an adjacent bit the transmission of signal transitions is modified from the onset of such sequence to eliminate any DC component.
Preferably, the possibly troublesome sequences are encoded by encoding pairs of second bit states by a single transition early in the first bit cell of the pair.

Description

Further, a limited look-ahead means is provided which is responsive to the first indicating signal, a current bit and a limited number of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within the limited number of next succeedinb bits and would not introduce such DC component with normal transmission. In addition, means responsive to the disabling signal is provided for disabling the transition modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence that would not introduce such DC component with normal transmission.

114~998 This invention relates to the transmission of data in binary form serially ~hrough an information channel~
~ore particularly it relates to a method and system for transmittinr~ signals that are self-clocking and still more particularly to such method and system for transr~lission through an information channel having no response at zero frequency. The invention relates to the encoding and decoding of particular ~inary codes. The invention finds partïcular application ~7here the information channel comprises a mag-netic tape recorder.
Data or information in binary form is comprised ofdata bits ~lherein tlle information in each bit is in the form of one or the other o two states. Such states are often referred to as logical "l" and logical "Q". In operating with information in 7~inary form it is necessary to recognize the respective logic states for each bit. ~hether these bits are recorded on tape or are otherwise recorded or are transmitted, each bit of information may be said to be maintai.ned in a ~it cell which represents an interval in time or space con-

2~ taining the respective ~it of information. The logic statesmay ~e recognized or referred to variously as "yes" or "no", "~" or "-", "up" or "down", and "true" or "not true", and t!;e like. ~lnere the information is recorded on a tape ~ ,~
A ~eoe~d~, the states may ~e of opposite magnetic polarization.
It is also common to have one state a reference level ard the otner state a different level, in ~7hich case i.-ld~c!'.ior.
of the second state may be provided by a recognizable signal .~7hile the firs' state is indicated hy absence of such signal.

,8 ~

There is positive logic and negative logic. Furtller, it makes no difference for the purposes of this invention which of the two states is called "l" and which is called "0".
As noted, the present invention finds particular applicability to information channels such as magnetic re-cording channels which have no response at zero frequency;
that is, they do not transmit at DC. In general it is de-sirable to record data bits as closely together as possible wnile produciny errors so infrequently as to be tolerable.
Various recording formats or binary data codes llave been de-veloped for recording binary data. Some codes desirably perMit self-clocking; that is, the hit cell intervals may be identified in the recorded bit data ~.~ithout the need for separate timing pulses.
In information channels wllich do not transmit DC, ~inar~ ave forms suffer distortions of peak amplitucle value and zero-crossing location which cannot be removed by means of linear response compensation networks unless tlle channel affords substantial response at frequencies at least as great a,s t~e bit rate. Tllese distortions are commonly described as baseline ~ander and act to reduce the effective signal-to-noise ratio and thus degrade the reliability of detection of tlle recorded signals.
A common transmission format or data code is that u~-ilized in the recording and reproducing system disclosed in ~iller U.S. Patent `lo. 3,108,261, issued October 22, 1~3 for ~ecording and/or ~eproducing System. In the ~iller Code, logical l's are represented by signal transitions at a ~artic-ular location in the respective bit cells, specificall~,~ at mia-cell, and logical 0's are represented by signal transitior.s 114~398at a different particular location in the respective cells, specifically at the beginning or leading edge of each bit cell.
The Miller format involves the suppression of any transition occurring at the beginning of one bit interval following an interval containing a transition at its center. A diffi-culty arises from the asymmetry of the waveform generated by these rules, for it introduces DC into the information channel.
A code based upon the Miller code but wit~ the DC component eliminated is described by A.M. Patel in "Zero-Modulation Encoding in ~agnetic Recording", IBM J. Res.
Develop., Vol. 19, No. 4, July 1975. Such format, commonly called 2M, is based upon the Miller format for most input sequences but sequences of the form 0111---110 having an even number of l~s are coded by special rules. While this code eliminates the DC content in the encoded waveform, it does so at the expense of requiring that each sequence to be specially coded be recognized in advance of encoding any part of the sequence. This requirement for look-ahead sequence scanning implies a coding delay (and coder memory) nearly as long as the longest possible sequence of the indicated type. To avoid requiring "infinite" memory, the Patel system provides for dividing input sequences periodically by in-serting additional suitably chosen parity bits. Practically this requires a rate change to accommodate the inserted bits.
Further the bits necessarily occupy some of the space avail-able for recording.
Another code based upon the Miller code with the DC
component eliminated is described in Miller U.S. Patent ~o.

4,027,335, issued May 31, 1977 for DC Free Encoding for Data Transmission System. Such format, sometimes called Miller-Miller, Miller2 or Miller-squared, is also based upon the original Miller forrnat for most input sequences, and sequences that would introduce a DC component are coded by special rules. However, in the Miller format it is unnecessary to look forward more than one bit interval, and, hence, long memory and extra parity bits are not required.
In the Miller format, it is noted at the beginning of a sequence of l's whether or not the sequence might be of the sort that produces a DC component and if, upon reaching the end of such sequence, it is found that the sequence indeed would produce a DC component under the regular Miller format, the encoding is modified to drop the transition that would have .caused DC imbalance.
The format of the present invention is also based upon the basic Miller code and is an alternative to the Miller format in that it, too, eliminates any DC component without requiring a long memory or extra parity bits. In accordance with the present invention, it is also noted at the beginning of a sequence of l's whether or not the sequence might be of the sort that produces a DC component, but instead of waiting to see how the sequence turns out, the encoding is modified at the onset of the sequence of l's to correct any possible imbalance. The encoding is then modified at the end of the sequence of l's as necessary to return to the regular ~iller format without introducing DC.
In accordance with the present invention a binary input data stream of rate l/T bits per second is encoded into a binary waveform having a minimum interval between transitions of T seconds, a maximum between transitions of 2.5 T seconds, no DC content, and a maximum value for the running integral of the waveform of l. 5 T seconds times half the magnitude of a transition. The encoding procedure requires no rate change and need entail an encoding delay of only 2 T seconds.
Decoding need require inspection of no more than 2.5 successive bit intervals; hence limiting the propagation of errors.
The format utilized in the present invention is an alternative to the Miller2 format, and like Miller achieves the high fre-quency response requirements of the Miller code with the DC-free characteristic of the Z.~ code without the rate change and a~ded redundancy of the latter and without requiring long memory. The present format is an improvement over Miller in producing no more than 2.5 T between transitions, Miller2 producing up to 3 T between transitions. A further improvement of the present format is the cancellation of any accumulated DC charge sooner in many cases than in the Miller2 format and in no cases later. Thus, the low frequency content of this format is less than that in the Miller2 format.
Although the simple form of the present invention does not require any long memory, the invention en-compasses a format with limited look-ahead requirements as may be used to reduce the bandwidth requirements of the attendant transmission system. More particularly, the basic format of the present invention produces times between transitions of 2.5 T in terminating certain sequences; whereas, in the Miller format the maximum time between transmissions is only 2 T.
As the 2.5 T times between transitions occur only upon sequences when there would not have been a net DC component under the standard Miller format, the present format introduces a problem that did not exist with Miller. The need for additional band-width would be lessened if the present format were used only when there would otherwise be a DC component, for then the maximum time between transitions is 2 T.
(Miller2 produces 3 T between transitions in encoding bit sequences that would otherwise introduce a DC component.) This, however, would require infinite look-ahead capability - to see whether or not there is going to be a problem before starting the encoding of a sequence. Obviously, infinite look-ahead capability is not possible, as it would require infinite delay in encoding. As a compromise, in one form of the invention a limited look-ahead capability ls provided, such as five bit look-ahead. The simple format of the present invention is then used only to encode the relatively few sequences exceeding the look-ahead length.
The present invention is used in a self-clocking transmlssion system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component. The apparatus comprises first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when ., :;'' ~ mb/ - 7 -9~8 the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC
component into the transmitted signal with normal transmission, transition modifying means responsive to the first indicating signal, a current bit of such sequence and an adjacent bit for modlfying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, limited look-ahead means responsive to the first indicating signal, a current bit and a limited number greater than two of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within the limited number of next succeeding bits and would not introduce such DC component with normal transmission, and means responslve to the disabling signal for disabling the transltlon modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence that would not introduce such DC component wlth normal transmis~ion.
In its method aspect the invention is used in a self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states of a sequence of data bit states are normally transmitted by signal transitions relatively early in respective bit cells and logical second bit states of the sequence of , data bit states are normally transmitted as signal ~- transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed. The method includes generating a first indicating signal when the number of first bit states ,:, ,., ~

mbj.. ~ - 7a -in the sequence of data bit states is of a predetermined parity, detecting the onset of a sequence of second bit states following a first bit state productive of the predetermined parity that might introduce a DC component into the transmitted signal with normal transmission, and in response to the first indicating signal, the state of a current bit and the state of an adjacent bit modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, the improvement comprising in response to the first indicating signal examining a limited number greater than two of bits next succeeding a current bit to determine at the onset of any such sequence if the sequence terminates within the limited number of next succeeding bits and would not lntroduce such DC component with normal transmission, and lnhibitlng the modifying of the transmission of signal tran~ltions corresponding to any of the second bit states of such seguence that would not introduce such DC
component with normal transmission.
$1ke the Miller2 format, the format of the present lnvention may be charac'cerized as a DC-free, self-clocking, non-return-to-zero format or DCF-SC-NRZ. It is sometimes reerred to as the Xerxes format. Thus a primary object of the present invention is to provide a system and method for transmitting binary data serially over an information I channel incapable of transmitting DC, although of course the system and method can be used ~ith information channels having DC capability. It is a further object of the invention to provide such system and method where the data are transmitted in seif-clocking form. It is still another object of the invention to provide such ., , , ~ mb/~ - 7b -system and method without the need for rate change or large memory. A still further object of the invention is to provide such system and method without as long a maximum time between transitions as is permitted by the Miller format. Yet another object of this invention is to provide such system and method that balances any accumulated charge sooner in many cases and in no case later than in the Miller2 format.
Other objects and advantages of the invention will become elear from the following detailed description, particularly when taken in conjunction with the appended drawings in which:
FIGURE 1 illustrates a number of binary signal wave-forms including those following the format according to the present invention and various formats of the prior art;
FIGURE 2 shows comparative waveforms utilizing the lS Miller format and a format aeeording to the present invention together with comparisons of the integrals of the transmitted signals;
FIGURE 3 is a block diagram of the system of the present invention;
FIGURE 4 is a schematic diagram of one form of encoder useful in the system shown in FIGURE 3;
FIGURE 5 is a timing diagram illustrating the opera-tion of the encoder of FIGURE 4;
FIGURE 6 is a schematic diagram illustrating one form of decoder and one form of transition detec-tor and 2F
eloek useful in the system illustrated in FIGURE 3;
FIGURE 7 is a timing diagram illustrating the opera-tion of the circuit of FIGURE 6;
FIGURE 8 is a schematic diagram illustrating look-ahead circuitry for another form of encoder useful in the system illustrated in FIGURE 3;

114q~g~8 FIGURE 9 is a schematic diagram illustrating encoding circuitry useful with the circuitry shown in FIGURE 8; and FIGURE 10 is a timing diayram illustrating the opera-tion of the circuits of FIGURES 8 and 9.
For an understanding of the present invent~on and its advantages, it will be helpful to consider various binary data formats utili~ed previously. In FIGURE 1 there are illus-trated a number of binary signal waveforms useful in trans-mi-tting or recording information serially in binary form.
Waveform lI utilizes the format of one form of the present invention. The waveforms of FIGURE 1 are divided into bit cells w1th each cell containing a bit of data in binary form;
that is, in each cell the binary information is in either state 1 or state 0. By way of example, FIGURE lA indicates the binary state of the information in a number of successive bit cells. This sa~e information is contained in various forms in the respective waveforms.
FIGURE lB illustrates a waveform following a return-to-zero (RZ) format wherein l's are indicated by upward or positive levels and O's are indicated by downward or negative levels, with the signal returning to a central or zero level between cells.
i~ ~ore commonly used format is the non-return-to-zero (NRZ) data code utilized Dy the waveforms shown in FIGURES lC and lD. rhe waveform of FIGURE lC, NRZ-L corresponds to the waveform of FIGURE lB, RZ, without the return to zero between bit cells. In this cGde, the signal remains at a 1 level or state for the entire cell containing a 1 bit and goes to the 0 level or state where there is a 0 bit in the bit cell.
Thus, there are transitions only when successive bit cells are in different states. In the waveform illustrated in FIGURE lD, NRZ-M, the code is a non-return-to-zero-mark code wherein each logical 1 is indicated by a transition between the two levels while a logical 0 is indicated by the absence of such transition. The difficulty with both of the NRZ codes is the very large possibility of timing errors, as the signal may remain in one state or the other for relatively long periods. It is therefore helpful to use self-clocking codes.
The waveforms illustrated in FIGURES lE and lF
follow so-called Manchester codes, also known as bi-phase-level (BI-~-L) and bi-phase-mark (BI-~-M), respectively. In the bi-phase-level code of FIGURE lE, the state of the bit is indicated by the direction of the transition in the middle of a bit cell. As shown in FIGURE lE, a transition upward at mid-cell indicates a logical 1, and a transition downward at mid-cell indicates a logical 0. In the bi-phase-mark code of FIGURE lF, a logical 1 is shown by a transition, either upward or do~n~ard, at mid-cell, while a logical 0 is indicated by absence of any transition at mid-cell. Self-clockiny of the bi-phase-level signal is achieved by utilization of the mid-cell transitions in each bit cell. Self-clocking of the bi-phase-mark signal is achieved by introducing a transition at the beginning of each bit cell. While the Manchester codes do not require a DC transmission capability, the addition of so many additional transitions materially increases the required bandwidth.
A waveform foliowing the format utilized in Miller U.S. Patent ~o. 3,108,261 is illustrated in FIGURE lG. As in the bi-phase-mark code, logical l's are indicated by ll~U~8 transitions in mid-cell,and logical O's are indicated by the absence of such transitions. In the Miller format, however, there are no timing transitions at the beginning of bit cells containing logical l's,and transitions are sup-pressed where they would otherwise occur at the beginning of respective bit cells following the respective mid-cell transition. In the basic Miller code this means that there is a transition at mid-cell for each logical 1 and at the beginning of each cell for each logical 0 except for the case when a logical 0 follows a logical 1. The suppressed transitions are indicated by X's on the waveform of FIGURE lG .
While the Miller code requires only the smaller bandwidth of the NRZ code and provides the self-clocking feature of the Manchester codes, it is not entirely free of DC. Certain sequences of logical l's and O's may unbalance the waveform following the Miller code. For example, in the waveform illustrated in FIGURE lG, the suppression of the transition between cells 11 and 12 may add a DC component that is not subsequently offset by suppression of an oppositely directed transition. If similar sequences are repeated, the DC com-ponent will grow, as will be described in yreater detail below in respect to FIGURE 2.
A waveform following the Miller format eliminates the DC component by suppressing another, but oppositely 2~ directed, transition. In accordance with the Miller format, it is a transition that can be subsequentl~ identified as having been suppressed by reason of the particular rules defining the format. More particularly, in accordance with ,' 114~8 a specific form of Miller , the next preceding transition is suppressed as indicated by an X on the waveform of FIGURE lH, this being the mid-cell transition in bit cell 11.
A waveform following the Xerxes format ls illustrated in FIGUR~ lI. The Xerxes format eliminates the DC component by restoring the transition suppressed in the Miller format in sequences where it would otherwise produce a DC component, as indicated by the transition marked by R in FIGU~E lI. Rather, it takes care of signal imbalance by encoding certain pairs of 9 10 1's as a single edge-cell transition at the beginning of the cell corresponding to the first 1 of the pair, as indicated by the transitions marked A in FIGURE lI, the transition in tne cell corresponding to the second 1 of the pair being suppressed, as indicated by an ~ in FIGURE lI.
An understanding of how the DC problem arises from use of the Miller code and how the problem is overcome by the use of the present invention will be facilltated by reference to FIGURE 2. In the ~liller code, the bi~s are identified by the phase of transition in level. With one exception, the 0 bits are identified by transitions in a relatively early part of a bit cell; whereas 1 bits are identified by transitions relatively late in tne bit cell. More specifically, in the illustrated waveforms, 0 bits are identified by transitions at the beginning of the cell, and 1 bits are identified by transitions at mid-cell. The one exception is that transitions are suppressed that would occur within one bit cell of any prior transition. The effect of this is tG suppress transi-tions identifying a 0 bit following a 1 b~t.

Referring to FIGURE 2, in FIG~RE 2A is indicated by way of example the binary state of successive bit cells in a data stream. FIGURE 2B indicates the type of various sequences identified below. The waveform of FIGURE 2C is a waveform of a signal identifying the bits of such data stream in accordance with the Miller format. FIGURE 2D represents the integral of the waveform of FIGURE 2C relative to the level of the mid-point of a transition. The transitions go one unit above and one unit below this mid-level. The length of each bit cell is time T. It may be noted that the integral returns to zero after each cycle of the Miller signal through bit cell 7. Thereafter, the integral remains negative, subsequently becoming more and more negative. This intro-duces the DC component previously mentioned, leading to errors where there is no DC transmission capability in the information channel, as in magnetic recording.
Reflection on the waveform of FIGURE 2C for the particular example of a data stream will reveal why this is so. For each bit cell containing a l bit the signal is balanced above and below the mid-level, making no net change in the integral. When the levels for successive 0 bits are in opposite directions, again the signal is balanced, making no net change in the integral. When successive 0 bits are separated by an odd number of l bits, the signal levels in the respective 0 bit cells are in opposite directions, and again the signal is balanced. A problem arises only where 0 bits are separated by an even number of 1 bits. In that case, the signal levels in the 0 bit cells are in the same direction, resulting in a net accumulated area under the curve and a ~' ll~V~98 net displacement of the integral from zero. Each time there - is a sequence of data in which two O bits are spaced by an even number of 1 bits, there is a net displacement of the integral. Of course, the displacement can be in either direction, and some of the time the displacement will return the integral toward zero. However, it is also possible that the areas accumulate, as shown in the example of FIGURE 2D.
The problem is obviously created by the suppression of the transition at the beginning of a O state following a succession of an even number of 1 states, making the signal asymmetrical. The solution to the problem, in accordance with the present invention is not to suppress certain l's transitions in addition to that transition, as in Miller2, but rather to encode certain pairs of l's by a single transition at the beginning of each pair, the result being that illustrated by the waveform of FIGURE 2E, where each restored transition is indicated by an R, each edge cell transition advanced to the edge of the first cell of such pair is indicate~ by an A, and each additionally suppre~sed transition is indicated by an X. As is evident from the integral of this waveform as shown in FIGURE 2F, there is then no net DC component. Of course, this is possible only if the suppressed and advanced transitions can be identified by a decoder. Otherwise, the information is lost. The present invention includes a method and system for identifying these suppressed and advanced transitions.
For an understanding of how such identification is achieved, the input data stream may be viewed as the con-catenation of se~uences of four types:

:, ',' .
~;

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~- - 14 -cg/ ~

1146~
(a) a ser-ies of l's; (b) a series of l's with a 0 at each end where the number of l's is even; (c) a series of l's with a 0 at each end where the number of l's is odd; and (Oo) a pair of O's. In this embodiment the number of O's from the beginning of transmission is counted. If the number of O's at the onset of a series of l's is even, the sequence is of type (a) and can present no DC problem; it may be encoded and decoded in accordance with the format of Miller U.S. Patent No. 3,108,261. It may be also noted that two successi~-e O's not part of a sequence of type (a), (b) Gr (c) are in sequence (00) and also leave the signal in balance. It is when the count of O's prior to a series of l's is odd that the 0 becomes part of a sequence (b) or (c) and may present a problem if the number of l's in the sequence turns out to be even, sequence (b). Thus, at the onset of a sequence, an indicator indicates whether or not the sequence of l's may present a problem. The encoder includes means for looking one bit cell ahead. If it is indicated that the sequence begins with a 0 and hence may present a problem, and upGn encoding the first l it is noted by lookiny ahead that the next bit is 1, the encoder immediately acts to correct for ?ossible imbalance by advancin~ the mid-cell transition that would occur for the first l in the series and produces a transition (A) at the front edge of the first 1 bit cell. The transition (X) is suppressed for the second of the two 1 bits. When the encoder seeks to encode the third bit, it looks to the succeeding fourth bit and again determines whether or not there is a pair of l bits. If so, the encoder proceeds as before to provide a transition at the beginning of the first of the two 1 bits and suppresses any transition for the second of the 1 bits. Whenever the sequence reaches a 0, if the number of 1 bits is even, indicating the sequence e d~e -ec to be of type (b), the following 0 bit is encoded by an e~
transition at the beginning of the bit. That is, the transition (R) is not suppressed,as it does not follow a mid-cell transition.
Examples of such encoding for sequences of type (b) appear in FIGURE lI, bit cells 9-12, and FIGURE 2E, bit cells 8-11 and 18-21.
With this encoding any even number of 1 bits bounded by 0 bits that are part of the sequence produces no DC component.
~n the other hand, when a series of 1 bits in a sequence of the type beginning with a 0 is encoded in accordance with this format and the encoder reaches the point of encoding a final 1 that is not part of a pai~ of ones, but rather is followed by the 0 endlng the sequence and indicating the sequence to be of type (c), that 1 is encoded by a mid-cell transition and the transition for the following 0 bit is suppressed as in the regular Miller format, again leaving the signal with no net DC component. Examples of such encoding for sequences of type (c) appear in FIGURE lI, bit cells 2-6, and PIGURE 2F, bit cells 5-7.
As explained above, if the Miller format is applied to these four sequence types, (a), (b), (c) or (00), the integral of the resulting waveform for sequence types (a), (c) or (00) always reaches zero at the end of the sequence. It is only the in~egral of the waveform for sequence type (b) ~hat does nct. Rather it reaches a value of +2T, the sign depending 114~98 on the sense of the last transition preceding the sequençe.
Further, if a sequence of type (b) is followed, after certain combinations of other sequence types, by another sequence of type (b), the integral of the concatenation of sequences may grow. For some choices of concatenated sequences, the running integral grows without bound, and this is the situation which yields DC content in the waveform, as illustrated by the wave-form of FIGURE 2D.
The present invention involves recognition of a sequence of type (b) and encoding it in a way eliminating any DC component. According to the present invention, sequences of types (a) and (00) are encoded according to the Miller format, and sequences of types (b) and (c) are encoded according to the special Xerxes rules. Sequences of types lS (a) and ~00) are distinguished from sequences of types (b) and ~c) by maintaining a count modulo-2 of logical 0's from the beginning of encoding. The distinction is based on the fact that all sequences have an even number of 0's. Sequences of type (a) have no 0's. Sequences of type (00) consist of two 01 3. Sequences of types (b) and (c), consisting of l's bounded by a 0 at each end, have two 0's. Thus, if the 0 count is even when a 1 appears for encoding, the sequence is of type (a). On the other hand, if the 0 count is odd when a 1 appears for encoding, the sequence is of type (b) or (c).
Of course, a sequence of type (b) cannot be distinquish-ed from a sequence of type (c) at the onset of a sequence, as the difference between the sequences is whether the count is odd or even when the sequence ends. Therefore, the special Xerxes coding is applied from the start of the l's in such sequences, and the encoding at the ends of the respective sequences is different depending on how the count turned out.
To this end a count modulo-2 of logical l's since the last odd 0 is maintaLned. The l's are encoded in pairs by a single transition (A) at the beginning of each pair until a 0 is reached, indicating the end of the sequence. When the l-count is odd at that time, the final l and the terminating 0 are en-coded in the usual Miller fashion. When the l-count is even, the 0 is encoded by an edge cell transition (R), which re-instateq a transition the Miller code would have suppressed, but may be said to be in accordance with Miller,as there was no mid-cell transition marking the preceding l. The type (c) sequence in bit cells 5, 6 and 7 (FIG. 2) contains only a single one bit and is encoded by the Xerxes coding rules since the one bit cell look-ahead detects the zero bit in cell 7. Thus, the %erxes format does have a look-ahead feature of one bit.
The Xerxes code provides a transmitted signal from which the original data can be decoded. Every mid-cell transition is decoded as l. An edge-cell transition in a bit cell followed by a cell having no transition is decoded as a 1 in each cell.
Any other edge-cell transition is decoded as a 0. Any other cell in which there is no transition is decoded as a 0. There may not be two successive cells without transitions, except upon loss of signal. That is not to say that there may not be longer intervals between transitions, for the termination of a sequence of type (c) may result in 2.5 T between transitions as shown in FIGURE lI, bit cells 3-5, where there is an edge-cell transition in cell 3, no transition in cell 4, and a mid-cell transition in cell 5. This is the longest interval permissible under the Xerxes format, absent signal loss.

1~4~9g8 - The method and system of the present invention thus provide for the transmission of data in binary form over an information channel incapable of transmitting DC, the in-formation being transmitted in self-clocking fashion. As mentioned earlier, it makes no difference which binary state is considered logical 1 and which binary state is considered logical 0. In the foregoing and following descriptions the state normally marked by mid-cell transitions is considered the 1 state, whereas the state normally indicated by edge-cell transitions is considered the 0 state. Further, theterm "mid-cell transition" is used to identify a transition relatively late in a bit cell, not necessarily in the center, and the term "edge-cell transition" is used to identify a transition relatively early in a bit cell, not necessarily at the very beginning.
In FIGURE 3 there is illustrated generally in block diagram form a system for encoding a data stream in serial binary bit form in accordance with the format described above, transmitting this information over an information channel, and decoding the received signals for subsequent utilization.
A data source 10 provides data in binary form serially to a path 12 when clocked by clock pulses applied over a path 14 .
from a clock 16. The data in the data source 10 can arise from any number of origins. ~lowever they arise, the data are converted by well known means into binary form and arranged to be clocked out serially, as by the clock pulses on the path 14.

- 114~998 The clock 16 produces clock pulses periodically at a frequency lF. The clock 16 may comprise a J-K flip-flop driven by double clock pulses applied over a path 17 from a clock 18 that develops double clock pulses at a frequency 2F.
The clock 18 may comprise any of a number of well-known oscillators. The clock and double clock pulses produced should have a fast rise time. Inasmuch as the transitions for signifying logical l's and logical O's occur at mid-cell and edge-cell or more generally at a later phase and an earlier phase, the clock 16 provides clock pulses in two phases, phase 1 (~l) and phase 2 (02). The clock pulses may be in the form of a square wave where the phase 2 pulses are inverted phase l pulses. Phase 1 (01) clock pulses are applied over the path 14 to clock the data source 10. Phase 2 (02) clock pulses appear lS on a path 20.
An encoder 22 receives the data in serial form from the data source 10 over the path 12 and also receives 01 clock pulses from the path 14 by way of a path 24 and 02 clock pulses over the path 20. Double clock pulses are received from the path 17 by way of a path 25. The encoder 22 operates upon the data as recsived in accordancé with the Xerxes format of the preisent invention, as described above. The encoded data are applied over a path 26 to an information channel 28 which may comprise a magnetic tape recorder where the informa-tion is recorded and later read out. The output of the information channel appears on a path 30. Transitions in the signal are noted by a transition detector 32 which produces signals on a path 34 indicative of the transitions.

A decoder 36 receives these transltion signals and decodes the information back to its original or a related form and provides the decoded information over a path 38 to a data utilization circuit 40. As mentioned earlier, the signal format of the present invention provides for self-clocking. That is, the decoder 36 must be time oriented to correspond with the original 01 and 02 signals to be able to recognize when in each bit cell the transition occurred.
This synchronization is achieved by utilization of a clock 42 which provides clock pulses at the double frequency 2F. To synchronize the clock, signals from the decoder may be applied over a path 44,or signals may be applied over a path 46 from the transition detector 32. In either event, appropriate timing signals are applied to the data utilization circuit 40;
they may be applied directly from the clock 42 over a path 50 or indirectly through the decoder 36 over a path 51. It may be noted that a path may comprise a plurality of conductors.
While a number of other circuits could be used, a preferred encoder 22 is illustrated in FIGU~E 4, with a timing diagram for that circuit being shown in FIGURE 5. (The points in the circuit of FIGURE 4 where the respective wave-forms shown in FIGURE 5 appear are identified by corresponding circled letters on FIGU~E 4.) The inputs to the encoder 22 are the phase 1 (01) and phase 2 (02) clock pulses applied from the clock 16 over paths 24 and 20, respectively, the double clock pulses applied from the 2F clock 18 over the path 25, and the data input I~DAT applied over path 12. There is also a reset pulse I applied over a path 52 from an initialization 9~8 pulse source 54. An input terminal 56 is coupled to the emitter terminal of a bipolar transistor Q10, with the base terminal thereof coupled to ground potential. The collector terminal of the transistor Q10 is coupled to input terminals of an AND gate 55 at a circuit junction point 57. The AN3 gate 55 functions to translate the voltage levels at the input terminals thereof to transistor-transistor logic level,s at the output thereof. The cathode terminal of a clamping ' diode D10 is coupled to the point 57 and the anode terminal of this diode is coupled to ground potential. A resistor R10 is coupled between the junction point 57 and a source of positive voltage to form in combination with the diode D10 a bias voltage circuit between the transistor Q10 and tAe AND gate 55. The initialization pulse source 5~ produces a reset pulse I upon application of an initialization signal INIT to the input terminal 56 thereof. The reset pulse I is applied to the encoder 22 to reset the various components thereof to a starting condition.
As illustrated,by FIGURE 5A, the ~1 clock pulses are uniform pulses occurring periodically with a period equal to one bit cell length and having fast rise and fall times and having a pulse length of one-half bit cell. The ~2 clock pulses are identical to the 01 clock pulses except dela~ed one-half bit cell. Thus, the 01 clock pulses rise at the beginning of each bit cell, and the 02 clock pulses rise at the midpoint of each bit cell. The ~1 and ~2 clock pulses may be produced by the clock circuit 16 illustrated in which double pulses from 2F clock 18 (as shown in FIGURE 5G) are applied over the path 17 to the CLK terminal or a JK flip-flop - 114~998 58. 01 clock pulses thereupon appear at frequency lF at the Q terminal of the flip-flop, and ~2 clock pulses appear at the Q terminal. In one embodiment of the invention, the 2F clock is equal to two (2) Megahertz and the lF clock is equal to one (l) Megahertz. Thus, the data bit rate is equal to one (1) Megabit per second.
The input data INDAT (FIGURE 5B) are applied in the form NR~-L to the D input terminal of a D flip-flop 60. The ~l clock pulses are applied to the clock terminal of the D flip-flop 60, whereby each positive-going transition of the ~l clock pulses (as shown in FIGURE 5A) causes the signal on the D
input terminal to be transferred to the Q output terminal.
The signal appearing at terminal Q of the D flip-flop 60 is -22-l/2-4~998 shown in FIGURE SC as- xk+l. This is the signal for the bit next to be encoded after the bit (k) being currently encoded.
At the same time, the inverted signal xk+l appears at the Q output terminal of the D flip-flop 60. The signal xk+l is applied to input terminal D of a D flip-flop 62 which transfers the signal to output terminal Q of the D flip-flop 62 upon the occurrence of the next 01 pulse applied to its clock terminal. The signal at termianl Q of the D flip-flop 62, shown in FIGURE 5D, is thus Xk, the signal for the bit being encoded, its inverse xk appearing at output terminal Q.
It is from these signals -k+l~ xk~l~ Xk~ an -k transitions for the encoded signals are fashioned.
Zero (0) parity is determined by a JK flip~flop 64.
To this end, the xk signal is applied to the J and K input terminals. When clocked by the 01 clock pulses, the Q ouput terminal provides a count modulo-2 of the number of zero (0) ~- blts from start (reset) up to the bit being encoded, that isr the count of 0 bits that have been encoded. Thus, when xk is O, the ~ flip-flop changes state when clocked by the next ~1 clock pulse to count a zero (0) bit. When xk is 1, the JK
flip flop remains in its same state. The output signal P(0) on the terminal Q, shown in ~IGURE 5E, is thus a parity count, being 1 when there has been an odd number of 0 bits and 0 when there has been an even number of 0 bits. The inverse P(0) appears on the output terminal Q.
One (1) parity is determined by a JK flip-flop 66 To this end, the xk signal is applied to the J input terminal, and no signal is applied to the K terminal. When a low logic level or 0 is applied to the J terminal, which occurs when the D flip-flop 62 has l's signal bits at its output terminal Q, the JK flip-flop 66 acts like the JK flip~flop ~ 1/

114~?998 64 and counts l's modulo-2 when clocked by the ~1 clock pulses. When a high logic level ~r l is applied to the J terminal, which occurs when the D flip-flop 62 has 0's signal bits at its output terminal Q, the count is reset to 0. Hence, the output signai P(l) on the output terminal Q, shown in FIGURE 5F, is ~ parity count, ~eing 1 when there has been an odd nu~ber of l's since the last pPeviOuS 0 bit and 0 when there h~s been - an even number of lls, The inve~se P~l) appea~s at the Q
output.
Encoding of the input data INDAT is effected b~
variously applying the signals developed b~ the D flip-flops 60 and 62 and by the JK flip-flops 64 and 66 to NO~ gates 72, 74, 76 and 78 which are enabled by 01 and ~2 clock pulses~
The understanding of the operation o~ these gates will ~e facilitated by determining when an output transition ~ulse is not to be created and considering that a transition pulse is produced for other conditions. It will also be helpful to consider the transition pulses as occurring in one of two parts OS the bit cell, a relatively early or edge-cell transition being considered an a transition and a rel~tively late or mid-cell transition being considered a b transition, Considering first the a tr~nsitlon, the primary signal is developed by the NOR gate 72~ to which there are three inputs. One input is xk from the Q terminal of the D
flip-flop 62. Another input i8 the 02 clock signal~ When the third input is 0, the output of the N~R gate is 1 when Xk is 0 and the 02 clock signal is 0. The ~2 clock pulse~
the inverse of the 01 clock sign~l shown in FIGURE 5A, is 0 during the first or a half of each bit period or bit cell.
Hence, a signal a, the inverse of a, the signal for the first cg/ ~fJ

1~4~398 half, will be 1 whenever xk is 0, hence when Xk, the signal being encoded, is 1. This means that an edge-cell a transition would appear otherwise, that is, when xk is 0, the normal en-coding of a 0 bit.
For the normal Miller format, it is necessary to suppress transitions (X in ~IGURE 1~) that occur less than a bit cell after a previous transition, that is, for 0 bits following a 1 bi~ in the normal Miller code. That is achieved by a D flip-flop 80, which has its Q output terminal connected to its D input terminal and is clocked by the 2F clock pulses (FIGURE 5G). The output of the NOR gate 72 is also connected to the D input terminal to form a so-called wired OR gate at a circuit junction point 81. The gates 72, 74, 76 and 78 and the flip-flop 80 are preferably of the emitter coupled logic family type. ~lowever, other logic family types may be employed when an OR gate is substituted for the so-called wired OR
gate at the junction 81.
As the D flip-flop 80 is clocked at the double fre-quency 2F, it is clocked in synchronism witn each half of the 2~ 01 and 02 clock pulses. The signal fed back from the Q output is thus the inverse of the signal previously clocked through in the next preceding half bit. As will be explained further below, when the ~OR gate 72 is enabled by the 02 clock pulse, the Q output of the D flip-flop 80 is the siynal encoded in the last half of the previous bit -k 1' that is, a 1 is fed back when there was a mid-cell transition in the previous bit cell. When added to the output of the NOR gate 72, this signal makes ak 1 when there was a mid-cell transition in the previous bit cell, hence making ak and suppressing an edge-cell transition when there was a mid-cell transition in the next preceding bit cell. This is in accordance with the 1~4~9!~8 standard Mlller format. This also provides for reinsertion of a transition (R in FIGURES lI and 2E) whenever the mid-cell - 114~9~8 transition of the prior 1 bit has been suppressed in accordance with the Xerxes format.
In accordance with the Xerxes format, it is also necessary to insert an edge-cell transition (A in FIGURES lI
and 2E) for the odd 1 of two l's of sequences of types (b) or (c). This is effected by the NOR gate 74. One input is xk+l from the Q output of the D flip-flop 60~ The signal xk+l is 0 when its inverse xk+l is l, indicating that the bit after that being encoded is 1. A second input is P(0) from the Q output of the JK flip-flop 64. The signal P(0) is 0 when its inverse P(0) is 1, signifying an odd number of 0's since the start and hence indicating a sequence of type (b) or (c). A third input is P(l) from the Q output of the JK
flip-flop 66. The signal P(l) is 0 when the bit being encoded is not an even number of l's since the last 0. The consequence of this is that the output of the NOR gate 74 is 1 only when encoding an odd 1 of a pair of l's in a sequence of type (b) or (c). This output is applied to the third input of the NOR
gate 72 to introduce the extra transition at the output of the NOR gate 72 under such conditions.
The signal ak (PIGURE 5H) applied to the D input to the D flip-flop 80 during the first half of a bit cell is therefore -k = bk-l -k ~ -~~- ~- ) (l) The term bk 1 is the Q output of the flip-flop 80, which Q
output provides both ak l and bk 1 in successive double fre-quency time slots. However, only -k 1 is provided for the above equation, and ak l is not used in the encoding operation.

114~998 As to the _ transition, the primary signal is developed by the NOR gate 76. One input is xk from the Q
output of the D flip-flop 62. The other input is the ~1 clock signal. When Xk, the signal being encoded, is O, the 01 clock pulse enables the NOR gate 76 during the second or b half of each bit cell. Hence, absent any other input, a signal b, the inverse of b, will be 1 whenever xk is 0. This means that a mid-cell b transition would appear otherwise, that is, when xk is l, the normal encoding of a l bit.
In accordance with the Xerxes format, it is necessary to suppress the transition (X in FIGURES lI and 2E) that would otherwise normally be produced in encoding the i~ e ~Jen pa ~) t~ ) second (or ~e~ even 1 of a pair of 1's in a sequence of type (b) or (c). This suppression is effected by the NOR gate 78. One input is ~(0) from the Q output of the JK flip-flop 64. The signal ~T~ is 0 when its inverse P(0) is l, signifying an odd number of 0's since the start and hence indicating a sequence of type (b) or (c). A second input is P(l) from the Q output of the JK flip-flop 66. The signal ~ is 0 when its inverse P(1) is 1, signifying that the previous bit encoded was a l. The third input is the 01 clock signal which enables the NOR gate 78 during the b half of the bit cell.
Thus, b is l and b 0 when an even parity l is encoded for sequences of types (b) and (c).
Also in accordance with the Xerxes format, it is necessary to advance the transition from mid cell to edge-cell (A in FIGURES lI and 2E) under certain conditions. The advanced transition is effected by the NOR gate 74, as described above. To complete the advance, it is necessary to suppress the mid-cell transition that would otherwise occur in the normal encoding of a l. This is effected by the D flip-flop 80. In this case, it is the ak signal that is fed back to the D input during the period that the NOR gates 76 and 78 are enabled. This makes bk 1 whenever ak is 1; hence it makes -k whenever ak is 1, suppressing a mid-cell transition in the same bit cell.
The signal b (FIGURE 5I) applied to the D input of the D flip-flop 80 during the second half of a bit cell is therefore:

bk ak ~ ~k + P(0) P(l) (2) The signals bk and ak are mutually exclusive in time as the former is 0 during the first half of a bit cell and the latter is 0 during the last half of a bit cell. This is because the respective enabling ~2 and 01 pulses are mutually exclusive. Thus, signals ak and bk are applied without inter-ference to the D input of the D flip-flop 80 where they are clocked successively to the Q output by the 2F clock pulses from the 2F clock 18, the inverse signals ak and bk being pro-duced at the Q output. The combined signal ab at the Q output terminal as shown in FIGURE 5J is, hence, one-half bit delayed from the inputs at terminal D. The delayed signal is fed back to the D input terminal as described above.
The inverted signal ak 1~ bk 1 at the Q output of the D flip-flop 80 is in NRZ-L form. It is applied to the J
an~ K terminals of a JK flip-flop 82 which is clocked by the 2F clock pulses (FIGURE SG) from the 2F clock 18. It is the function of the flip-flop 82 to provide transitions in response to the levels of the NRZ-L form of the data at the Q output of the flip-flop 80. The clock pulses cause a change of state at the Q output of the flip-flop 82 whenever the input level is 1 and leave the state the same whenever the input level is 0. This causes a change of state, that is, a transition, whenever -k 1~ bk 1 is 1 at a 2F clock pulse. This results in an out-put signal at the Q output in accordance with the ~erxes for-mat, as shown in FIGURE 5K.
The special tasks of the encoder shown in FIGURE 4 may be summarized as follows. It recognizes the beginning of each sequence of l's which may be of type (b). This is done in the encoder of FIGURE 4 by means of the D flip-flop 64 which toggles each time a 0 is encoded. Its Q output P(0) provides a parity count of whether O's are odd or even at the beginning of a sequence of l's. An odd count indicates a sequence of type (b) or type (c). The encoder recognizes at the end of such sequence whether it is of type (b) or of type (c). This is done in the encoder of FIG~RE 4 by means of the flip-flop 66 which toggles each time a 1 is encoded and which is cleared each time a 0 is encoded. Its Q output P(1) provides a count of whether l's are odd or even. If odd when a 0 is reached, the sequence is of type ~c); if even of type (b). Sequences of l's of type (b) or (c) are encoded by a transition at the edge of the first (odd parity) 1 of a pair of l's, with the last 1 of an odd sequence of l's of type (c) encoded in the standard Miller code of U. S. Patent No. 3,108,261. A11 other encoding follows the prescriptions of Miller U. S. Patent No. 3,108,261, keeping in mind that the standard Miller code would encode the 0 at the end of a sequence of type (b) with an edge-cell transition because there is no mid-cell transition for the preceding 1 in ~erxes.

~29-As indicated in FIGURE 3, the encoded information on the path 26 passes through the information channel 28 and then over the path 30 to the transition detector 32. The out-put of the transition detector is applied over the path 46 to the 2F clock 42 and over the path 34 to the decoder 36.
The output of the 2F clocX 42 is -applied to the decoder 36 over the path 48. Exemplary forms of the 2F clock 42, the decoder 36 and the transition detector 32 are shown in FIGURE 5. Timing diagrams for the circuit of FIGURE 6 are shown by the waveforms of FIGURE 7, with points in the circuit of FIGURE 6 where respective waveforms shown in FIGURE 7 appear being identified by respective circled letters.
Referring to FIGURE 6, a received signal of the form illustrated by the waveform shown in FIGURE 7A is applied on path 30 to the transition detector 32. The transition detector 32 comprises a limiter circuit 132 and a dif-ferentiating circuit 134. The limiter circuit 132 greatly amplifies the input signal and cuts the peaks off to produce a corresponding limiter output signal on the path 34 having sharp transitions at the zero crossings of the input signal, as shown by the waveform of FIGURE 7B. The inverted output signal from the limiter 132 is applied to the differentiating circuit 134, which develops signals of opposite phase in an amplifier 136. The two outputs of the amplifier 136 are applied to both of NOR gates 138 and 140 with the inverted signal being delayed slightly by a delay line 142 in its application to the NOR gate 138 and the non-inverted signal being delayed slightly by a delay line 144 in its application to the NOR gate 140. The differentiating circuit 134 thus provides on the path 46 a transition signal of the waveform 114~)~98 , , shown in FIGURE 7C, with a pulse for each transition in the .input signal of FIGURE 7A.
The 2F clock 42 in this embodiment comprises a ringing oscillator producing a signal in the form shown in FIGURE 7D, which, after amplifying and limiting, becomes a square wave on the path 48 as shown in FIGURE 7E. The integrated circuit A3 forming the clock 42 in the embodiment illustrated comprises a l`~otorola Triple Line Receiver MC10216 connected as indicated, with pins 1 and 16 grounded and pin 8 at -5.2v.
The phase of the pulses on the path 46, relative to the oscillations in the tank circuit of the oscillator, advances or retards the oscillations to synchronize the clock output on the path 48 with the transitions in the input information on the path 30. The phase of the clock output may be adjusted by a variable inductor 146 to place the clock pulses as shown in FIGURE 7E in appropriate relationship to the transitions in the limiter output signals as shown in FIGURE 7B.
The second output of the limiter 132 is coupled to the decoder 36 over the path 34 to the D input of a D flip-flop 148, which output signal is illustrated by FIGUR~ 7B.
The 2F clock pulses (FIGURE 7E) are applied over the path 48 from the clock circuit 42 to the clock input terminal of the D flip-flop 148. This clocks the data from the D input terminal to the Q output terminal of the D flip-flop 148, producing a signal as shown in FIGURE 7F, which corresponds to the input data of FIGURE 7A delayed by one-half cycle of the 2F clock pulses. The signal on the Q output terminal of the D flip-flop 148 is applied to the D input terminal of a D flip-flop 154. The 2F clock pulses are applied to the clock terminal of the D
flip-flop 154. The D flip-flop 154 thus clocks the Q

-- 114~998 output of the D flip-flop 148 and reproduces that output at the Q output terminal of the D flip-flop 154 (FIGURE 7G) with a delay of one 2F clock pulse, that is, with one-half bit cell displacement. The 2F clock pulses are al50 applied to the clock terminal of a JK flip-flop 160, the J terminal being held positive and the K terminal being held at ground. This toggles the JK flip-flop 160 to produce an output signal on its Q terminal as shown in FIGURE 7H. These are clock pulses of frequency lF, which comprises the bit cell rate of the data.
These clock pulses are applied to the path 51 as the output clock pulses to the data utilization circuit 40.
The D input and Q output terminals of the D flip-flops 148 and 154 are applied to an exclusive OR sate 172 which detects a difference between the clocked data signal (FIGURE
7F) and the clocked data signal delayed (FIGURE 7G). The output of the exclusive OR gate 172 thus indicates any transition in the input data occurring since a previous 2F clock pulse on the clock terminal of the D flip-flop 154. A 1 output of the exclusive OR gate 172 thus indicates a data transition, as shown in FIGURE 7I.
The data transition signals of FIGURE 7I are applied to the S input terminal of a 5-bit shift register 174. In the embodiment illustrated, the 5-bit shift register 174 com-prises a ~e~as Instruments type 7496 5-Bit Shift Register con-nected as shown in FIGURE 6 with the manufacturer's connecting pin numbers identified therewith. The shift register 174 is clocked by the 2F clock pulses (FIGURE 7E). The shift register serially clocks in the transition data from the gate 172 with each clock pulse and advances the data along the five output terminals one after the other. As the shift register 114~998 is clocked by 2F clock pulses, the shift register advances each half bit cell. 1'he bit cells follow successively at frequency lF, each bit cell having two halves, a and _, successively. The halves therefore occur at double frequency 2F, the clocking rate for the S-bit shift register. The data are clocked out of the decoder 36 to the path 38 at the bit rate lF, as will be explained further below. At the time of such clocking out of the decoded bit, the outputs QA' QBI QC ' QD and QE of the 5-bit shift register 174 contain the tran-sition data in respect to the half bit cells bk+l, ak+l, bk, ak and bk 1' respectively. What the outputs contain at the succeeding 2F clocking is immaterial, as the output is clocked out of the decoder only once per bit cell. Thus, the out-puts have been labeled in FIGURE 6 to indicate the condition lS at the time of ciocking out the decoded bit signal to the c-~utput path 38.
The five outputs of the 5-bit^shift register 174 are combined to develop the decoded signal. The signals are combined to identify l's, with each bit not a 1 being clecoded as 0. From the Xerxes encoding format explained above, there are three ways in which a 1 is encoded. ~ormally, l's are encoded by a mid-cell transition, i.e., ak is 0, bk is 1.
Where l's occur in a sequence of type (b) or (c), pairs of l's are encoded by an edge-cell transition for the first (odd parity) 1 of the two l's; thus, for the first (odd parity) 1 of these two l's ak is 1 and bk is 0, and ak+l is 0 and -k+l is 0, and for the second or even parity 1 of these two l's ak is 0 and bk is 0, and bk 1 is 0.

~l~U998 1 s The normal condition (i.e., cnc's encoded as mid-cell transitions) is sensed by an AND gate 176 to which are applied the inversion of the QB output ak (as inverted by an inverter 178 to ak) and the QC output bk, as shown in FIGURE 7J. The AND gate 176 thus provides a 1 output when ak is 0 (that is, ak is 1) and bk is 1. This signal is applied to a NOR gate 180 which produces a 0 output under these conditions.
A 1 that is the odd 1 of a palr of l's encoded according to the special Xerxes rules is sensed by an OR gate 182 and a NOR gate 184. The QA output bk+l and the QB output ak+l are applied to the OR gate 182. The OR gate 182 produces a 0 output only when both -k+l and ak+l are 0. This signal is applied to the NOR gate 184 together with the QC output bk and the inverted QD output ak. Thus, the NOR gate 184 pro-duces a 1 output only when bk+l and ak~l -k ak is 0 (that is, ak is 1). This corresponds to an edge-cell transition in a bit cell followed by a bit cell with no transition. This signal is also applied to the NOR gate 180 which produces a 0 output under these conditions.
A 1 that is the second of a pair of ones encoded according to the special Xerxes rules is sensed by a NOR cJate 186 to which are applied the QC output -k' the QD output ak and the QE output bk 1~ The output of the NOR gate 186 is 1 only when ak, bk and bk 1 are all 0 as occurs onl~ for the even 1 of a pair of l's encoded according to Xerxes. The output of the NOR gate 186 is also applied to the NOR gate 180 which produces a 0 under these conditions.
The NOR gate 180 thus produces a 0 output whenever any one of three conditions indicating a 1 e~ists. Otherwise, 9~8 its ou-tput is 1. The output of the NOR gate 180 is applied to the D input of a D flip-flop 188, which is clocked by the lF clock pulse (FIGURE 7H). Each clock pulse transfers the output of the NOR gate 180 to the Q output terminal of the D flip-flop 188, the inverse appearing at the Q output terminal. The Q output is thus 1 under the conditions where the 0 output of the NOR gate 180 indicates that a 1 has been decoded, and the Q output is otherwise 0. The Q output is applied to the path 38 in the form NRZ-L as indicated in FIGURE 7K.
As a brief summary, reference is made to TABLE I
below wherein X represents either a one or a zero.

TABLE I

bk-l ak bk a~,+l bk+l Xk ...... .
X 0 1 X X 1 by AND cJate 176 X 1 0 0 0 1 by gates 182 and 184 0 0 0 X X 1 by NOR gate 186 1 0 0 ,Y X G
X 1 1 X X Transmission Error 1 1 X X X Transmission Error 0 0 0 0 0 Transmission Error 0 0 0 Synchronization Error --` 114~998 The above description of the circuit of FIGURE 6 has assumed the clock 42 to be in proper synchronism with the edge-cell transitions. However, because the clock 42 has a basic frequency twice the bit cell frequency, it is possible for the clock to be in phase with the mid-cell transitions rather than with edge-cell transitions. In that case, the data out at the output terminal Q of the D flip-flop 188 would appear as shown in FIGURE 7L. The lack of synchronization may be detected by a synchronization detector l9O which recognizes certain impermissible output conditions. In the Xerxes format the longest permissible interval between transitions occurs at the end of sequence of type ~c) where the final three l's are encoded by an edge-cell transition for the first of the three l's, no transitions for the second of the three l's, and a mid-c011 transition for the last of the three l's.
Using the designations of FI~URE 6, this condition occurs when ak l and bk+l are both l and -k-l~ ak~ bk and ak+1 are all O. The condition is decoded by the NOR gate 186 -35-l/2-11~0998 when clocked out of the D flip-flop 188 by the lF clock pulse during an interval while the bk l signal appears at the QE output terminal of the 5-bit shift register 174.
Should the lF clock pulse be out of proper phase in relation to the 2F clock pulse, the D flip-flop 188 would be clocked out a half cycle prematurely. With the above transitions the outputs QA' Q ' QC and QD were all 0 a half cycle earlier.
To the decoder this would look like two successive bit cells without a transition in either half. However, this is not a possible condition under the Xerxes format. The only condition producing 2.5 T between transitions, that is, with four half-cells in a row without transition, is at the ter-mination of a sequence of type (c). In that case only the middle 1 of the last three l's is encoded without a transition in either half. Thus, a condition where terminals QA' QB' QC
and Q are all 0 at the time of clocking is an indication that the decoder is out of synchronization.
The synchronization detector 190 detects a lack of synchronization by noting the occurrence of the condition where the terminals QA' QB' QC and QD are all 0 at the time of clocking. To this end these terminals are connected to a NOR gate 192 which produces a 1 output only when all inputs are 0. The output of the NOR gate 192 is applied to the D
input terminal of a D flip-flop 194 clocked by the lF clock pulses (FIGURE 7H). This produces a 1 output on the Q output terminal of the D rlip-flop 194 at the next clock pulse when all of the terminals QA~ QB~ Q and Q are 0 simultaneously.
The output signal may be used in a number of ways, as to operate an indicator or means for placing the decoder in synchronism. The lF clock may be returned to synchronism in a number of ways, as by suppressing a 2F pulse to the JK flip-flop 160, in a manner similar to the synchronizing circuit described in Miller U.S. Patent No. 4,027,335. To assure synchronization, a special lead-in signal may be transmitted that includes at least one sequence of type (c), permittlng the synchronization detector 190 to identify lack of synchronization and permit remedial action at the outset.
This avoids losing data before the data bits themselves provide transitions revealing the error in synchronization.
It may be noted that a signal indicating lack of synchronization will also occur at the output of the synch-ronization detector 190 when there is a loss of signal on the path 30. This condition can be distinguished from the condition of lack of synchronization by noting the output signals from the 5-bit shift register 174. With loss of signal, all outputs will go to 0 simultaneously; whereas, in normal Xerxes encoding there can never be more than four half-cells in a row without a transition, and hence one of the outputs must be 1 whether the decoder is in or out of synchron-ization, so long as a signal is being received in the Xer~es format.
At the start of decoding the various components of the decoder may be reset by a reset pulse I from an initializa-tion pulse source 196 operating like the similar circuit 54 of the encoder.
As mentioned above, the longest interval between transitions under the Xerxes format is at the termination of a sequence of type (c); yet this is a sequence that could have been encoded under the standard Miller format 1~4~998 without introducing a DC component. As the long intervals without transitions require a greater bandwidth, the bandwidth requirements are lessened by using the standard Miller format to encode sequences of type (c). The diffi-culty with this is that sequences of types (b) and (c) cannot be distinguished at their onset. It is only upon termination of the sequence that the number of l's can be determined as odd or even. Thus, to encode sequences of type (c) in the standard Miller format, one must look ahead to the end of the sequence. As a sequence may be very long, this is impractical,as it requires almost infinite look-ahead capability. Therefore, in one embodiment of this invention a limited look-ahead capability is provided for looXing ahead some reasonable number or bits and encoding sequences that can thereby be identified as type (c) in the standard Miller format. Where the end of the sequence cannot be seen, the sequence is encoded under the Xerxes rules as set out above. An encoder with 5-bit look-ahead capability is shown in FIGURES 8 and 9. The look-ahead circuitry and parity counters are shown in FIGURE 8. The encodin~ circuitry is shown in FIGURE 9. Corresponding waveforms are illus-trated in FIGURE 10. Points in the circuits of FIGURES 8 and 9 where respective waveforms shown in FIGURE 10 appear are identified by respective circled letters.
The look-ahead circuitry of FIGURE 8 receives the same input signals as the encoder 22 shown in FIGURE 4, namely, 01 clock pulses on the path 24 (FIGURE lOA), the data input INDAT in form NRZ-L on the path 12 ~FIGURE lOC), and reset pulses I on the path 52. The other input signals to the -- 114~998 encoder 22 are applied to the circuit of FIGURE 9, namely 02 clock pulses on the path 20 and 2F clock pulses (FIGURE
10B) on the path 25. The 01 clock pulses and the reset pulses I are also applied to the circuit of FIGURE 9.
In the circuit of FIGURE 8, the input data signals INDAT (FIGURE lOC) are applied serially to the A and B
input terminals of an 8-bit shift register 196 (serial in/
parallel out), preferably Texas Instruments type 74164 connected as shown. The 8-bit shift register 196 provides a 7-bit delay to permit a look-ahead with respect to the data output from the shift register. That is, if the data output at the QH output terminal (FIGURE lOE) is the signal xk to be currently encoded, the signal on the QG output terminal is xk+l and so on to the QA output terminal which provides the signal seven bits after Xk, namely Xk+7. Should a sequer.ce occur which can be determined to be of type (c) by the time the first 1 of the sequence reaches the QH output, the entire sequence is encoded according to the standard Miller code.
The circuit shown in FIGURE 8 makes this determination and sets a flag G to modify the Xerxes encoding (FIG~RE 9) for a recognized se~uence of type (c).
The creation of the flag G begins with the signal Xk+7 (FIGURE lOD). The signal Xk+7 is applied to the K
input terminal of a JK flip-flop 198 with the signal xk+7 as inverted by an inverter 200 applied to the J input terminal. The JK ,lip-flop thus counts O's from the beginning of encoding at a time 7 bits before the signal Xk is available at the terminal QH for encoding. The JK

114~998 flip-flop 198 is clocked by the 01 clock pulses to produce a 0 parity count at the Q output terminal (FIGURE lOF).
The Q output of the JK flip-flop 198 is applied to the D
terminal of a D flip-flop 202 clocked by the ~l clock pulses.
S The Q outputs of the JK flip-flop 198 and the D flip-flop 202 are applied to a NAND gate 204 which thus provides a 1 output (FIGURE lOH) whenever the parity of O's at the - terminal QA is 0, that is, when there has been an even number of O's since the beginning.
Such 1 output is applied to the CLR terminal of a counter 206 which may be a counter of Texas Instruments type 74161 connected as shown having a l's output count at terminal QA (FIGURE lOI), a 2's output count at output terminal QB (FIGURE lOJ), and a 4's output count at output terminal QC (FIGURE lOK). When enabled by a 1 applied to its enabling terminal EN ~FIGURE lOG) the counter 206 counts 01 clock pulses applied to its CLK terminal. The enabling signal is produced by an AND gate 208 when its three input signals are all 1, that is, when (1) Xk~7 (FIGURE lOD) at the output terminal QA of the shift register 196 is 1, indicating a 1 in a series of l's, (2) the 0 parity count (FIGURE lOF) at the output terminal Q of the JK flip-flop 198 is 1, indicating that the sequence of l's began with a 0 and is thus of type (b) or type (c), and ~3) the output of a NAND gate 210 is 1, indicating that the counter 206 has not reached a count of 6. A count of 6 would make the QB and QC outputs of the counter 206 both 1, and hence both inputs to the NAND gate 210 would be l. The consequence of this is t~at the counter 206 counts (uptoamaximum of 6), the 01 clock pulses occurring whenever a sequence of l's occurs with 0 at odd parity, that is, whenever the l's are a part of a sequence of type (b) or type (c). If the counter 206 does not reach a count of 6 before a 0 is reached in the data stream, the counter will stop counting upon the occurrence of the first 0 at the output terminal QA of the shift register 196 ~FIGURE lOD), for that applies a 0 to the input of the enabling AND gate 208, making its output 0 (FIGURE lOG~ and disabling the counter 206. The parity counter JX flip-flop 198 also produces a 0 at its Q output terminal (FIGURE lOF) indicating an even number of O's and applies a 0 to the AND
gate 208 so that the counter remains disabled with subsequent l's in the data input. The even parity also resets the counter by way of the D flip-flop 202 and the NANDgate 204 (F~GURE lOH) as described above. A count of 6 in the counter 206 also disables the cou~ting by producing a 0 output from the NAND gate 210, which is applied to the enabling AND gate 208.
The determination of whether or not to create a flag G ig made by an AND gate 212. The signal from the l's output terminal QA (FIGURE lOI) of the counter 206 and the inverted signal Xk+7 from the inverter 200 (FIGURE lOD inverted) are applied to the AND gate 212. The l's output is 1 at the end of a sequence of l's only if the number of l's in the sequence is odd and less than 6. If the count is even and less than 6, the l's output is 0. If the number of l's in the sequence is 6 or more, the counter stops at 6, leaving the l's output at 0. Hence, it is only when the l's count by the counter 114C~998 206 is 1, 3 or 5 at the time of the next 0 at the terminal QA (FIGURE 10D) of the shift register 196 that the AND gate 212 produces a 1. This output (FIGURE lOL) is 1 whenever a flag G is to be created.
The output of the ~D gate 212 is applied to the enabling terminal EN of a demultiplexer 214, which may be of Texas Instruments type 74S138 connected as shown. When enabled by a 1 from the AND gate 212, the demultiplexer 214 transfers the input count applied from the counter 206 to a 6-line output, producing a 0 on the line corresponding to the final count. The rest of the output lines are at 1. For a count of 1, the 0 appears on output b; for a count of 3 on output d (FIGURE 10M); and for a count of 5 on output f (FIGURE lON). There can be no even counts since the AND gate 212 enables the demultiplexer only for a 1, 3 or 5 count as stated above.
The outputs of the demultiplexer 214 are applied to respective A~D gates 216, 218, 220, 222, 224 and 226. The outputs of these AND gates are applied to the input terminals of parallel access shift registers 228 and 230, which may be of Texas Instruments type 74195 connected as shown. AS 50 connected, upon application of each ~1 clock pulse (FIGURE lOA), the 0 applied from the demultiplexer shifts throuyh the shift register until it is provided as an output at terminal QC f the register 230. This 0 output is coupled to the input of a latch 2'2, which may comprise a Texas Instruments flip-flop 7476 connected as shown.
The application of 0 to the input terminal of the latch 232 produces the flag G (FIGURE lOQ) at the Q output terminal thereof at the time the first 1 of the series reaches output terminal QH of the shift register 196. Its inverse G
is produced at the Q output terminal of the latch 232. The flag G then remains set until the end of the sequence, when it is reset by the Q output P(0) (FIGURE lOP) of a 0 parity detector 234, which may be a Texas Instruments JK flip-flop of type 74109 connected as shown. The 0 parity detector 234 functions like the parity detector of the JK
flip-flop 198 to determine whether a number of O's from the beginning of encoding is even or odd, that is, whether or not a sequence of type (b) or type (c) may be commencing or ending. When a 0 ending a sequence of type (b) or (c) appears at output terminal QH of the shift register 196 (FIGURE lOE), xk is 0. Such signal is inverted to 1 by an inverter 236 to form Xk. Under these conditions, the 0 parity detector 234 counts a 0 upon each 01 clock pulse. When the count is even, P(0) is 0. When this occurs at the close of a sequence of l's at output QH, it acts to clear the latch 232, to return the encoding to the regular Xerxes encoding from the special circumstances of regular Miller coding of type (c) sequences having less than six l's. In addition to clearing the latch 232, the 0 parity signal P(0) (FIGURE lOP) and its inverse P(0), produced at the Q output terminal of the 0 parity detector 234, are used for encoding by the circuit of FIGURE 9.
A 1 parity detector 238, which may also be a Texas Instruments JK flip-flop of type 74109 connected as shown, functions like the parity detector of the JK flip-flop 66 to produce a 1 parity signal P(l) (FIGURE 10R) at the Q output terminal and its inverse -7~) at the Q output terminal.
The inverse 1 parity signal P(l) is used for encoding by the circuit of FIGURE 9.

1141~998 An inverter 240 is used to invert the signal xk+l to provide its inverse xk+l for use in encoding by the circuit of FIGURE 9.
The encoding circuit of FIG~RE 9 operates on the signals developed in the circuit of FIGURE 8 much as the encoding circuit of FIGURE 4. In this case, enabling AND
gates 242 and 244 are enabled by 01 and 02 clock pulses, respectively, at respective, mutually excluslve a and b parts of a bit cell to develop intexleaved ak and -k signals which are applied through an OR gate 246 to the D input of a D flip-flop 248 where they are successively clocked out by 2F clock pulses (FIGURE 10B), making the Q output terminal of the D flip-flop 248 a half bit behind the input at the time o clocking. ~Hence, the Q output signal is -k 1 at the lS time of encoding ak.
As in the case of the encoder of FIGURE 4, l's are normally encoded according to standard Miller by a mid-cell transition, that is, bk is 1. The normal encoding is effected by the AND gate 244 which produces a 1 when enabled by a 02 clock pulse and xk is 1, provided the third input is also 1. The third input is received from an OR gate 250.
This has two inputs, one from an OR gate 252 and the other from an AND gate 254. The OR gate 252 responds to P(0) or G to produce a 1 that operates through the OR gate 250 to enable the gate 244. When P(0) is 1, the sequence of l's is of type (a) to be encoded according to the normal Miller format. When G is 1, the sequence of l's is of type (c) but the sequence is less than six and hence is to be encoded - according to standard Miller. The only other time a 1 is to be encoded by a mid-cell transition is when it is the last of a sequence of l's of type (c). This is detected by the AND gate 254. It occurs when (1) P(0) is 1, signifyiny a sequence of type (b) or type (c), (2) P(l) is l, signifying an odd 1 is being encoded, and (3) xk~l is l signifying that the next bit is 0.
Also as in the case of the encoder of PIGURE 4, 0's are normally encoded according to standard Miller by an edge-cell transition, that is, ak is 1. The normal en-coding is effected by the AND gate 242 which produces a l when enabled by a ~1 clock pulse and the output of an OR
gate 256 is 1. The OR gate 256 produces such 1 output when the output of a NOR gate 258 is 1. The inputs of the NOR
gate 258 are the bit signal -k and the Q output of the D
flip-flop 248, such Q output being bk 1 at the time of encoding ak. Hence, the output of the NOR gate 258 operates by way of the OR gate 256 to enable the AND gate 242 to encode a 0 by an edge-cell transition ak when xk is 0, except when it follows a mid-cell transition encoding a next preceding 1.
According to the Xerxes format, an edge-cell tran-sition is also effected at the beginning of the odd parity l's of pairs of l's of sequences of l's of type (b) or type (c), except in the case where the look-ahead capability is not exceeded and the sequence can be determined at the onset to be of type (c). This encoding is effected by A~D gates 260 and 262. The AND gate 260 is enabled by the P(l) signal which is 1 when the 1 being encoded is the odd l of a pair.

)998 The AND gate 262 produces a 1 output only when (1) P(0) is 1, signifying a sequence of type (b) or type (c), (2) xk and

(3) xk+l are both l's, signifying a pair of successive l's, and (4) G iS 1, signifying that it is not a sequence of type (c) within the look-ahead capability. Thus, under these conditions, the l output of the AND gate 262 produces a l output of the AND gate 260 for the odd l's. This acts through the AND gate 260, the OR gate 256 and the AND gate 242 to make ak 1 and hence to produce an edge-cell transition.
The transitions in output signal are produced by a JK flip-flop 264, which may be a Texas Instrument JK flip-flop of type 74109 connected as shown. The transitions occur upon each 2F clock pulse when the Q output of the D flip-flop 248 is l, producing an output signal as shown in FIGURE lOS.
In FIGURE 10T is illustrated how the same signal would be encoded according to the Xerxes format when the look-ahead capability is only one. That is the case of the encoder of FIGURE 4 and would be the case if the latch 232 of the circuit of FIGURE 8 were disabled with G 0 (suppressed). It may be noted that when the look-ahead capability is e~ceeded (FIGURE
10T), there are 2.5 T between transitions, whereas the tran-sitions are otherwise (FIGURE lOS) no more than 2 T apart, reducing bandwidth re~uirements.
As in the case of the encoder of FIGURE 4, the various flip-flops and shift registers of the circuits of FIGURES 8 and 9 may be cleared at the outse-t of encoding by a reset pulse I.

While two specific encoding circuits have been shown and a specific decoding circuit operating on the same code has been discussed, it should be evident that other particular circuitry may be used for the same purposes. Further, other code formats may be used coming within the scope of the present invention. As to 0 parity, it makes little difference whether the controlling parity is even or odd; as imbalance cannot accumulate so long as a predetermined parity state is used for controlling encoding to distinguish sequences of type (a) from those of types (b) and (c). If odd parity were used instead of even parity to identify sequences of types (b) and (c), different sequences would be identified and encoded by the special Xerxes rule, but the same decoding system would accurately decode to the original data.
lS In summary, the invention encompasses a method and system wherein a data stream in binary serial form is considered as the concatenation of a plurality of types of sequences, some of which may create a DC imbalance if the code format of Miller U. S. Patent No. 3,108,261 were used. In accordance with the present invention, there is indicated at the onset of any sequence of l's whether or not the sequence is of the sort that could introduce DC imbalance. Responsive to this indication remedial action is taken at the onset of the sequence appropriate for eliminating any DC component. Preferably this is achieved by encoding sequences of type (b) or type (c) by providing a single edge-cell transition for the first of each pair of l's with no transition for the second 1. In one form of the invention, by looking ahead a limited number of states, it may be noted at the onset whether or not a particular sequence of l's ends within that limit and is of the sort that would not introduce a DC component into the transmission signal with normal Miller transmission, in which eventthe entire sequence is encoded normally.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a self-clocking transmission system for trans-mitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transi-tions relatively late in respective bit cells and any trans-sition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC component into the trans-mitted signal with normal transmission, transition modifying means responsive to said first indicating signal, a current bit of such sequence and an adjacent bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate and DC component, limited look-ahead means responsive to said first indicating signal, a current bit and a limited number greater than two of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and means responsive to said disabling signal for disabling said transition modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence

Claim 1. (Continued) that would not introduce such DC component with normal transmission.
Claim 2. Apparatus in accordance with Claim 1 wherein said transition modifying means modifies the trans-mission of signal transitions to provide a single transition corresponding to each pair of second bit states of such sequence where the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 3. In a self-clocking transmission system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transi-tions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transi-tion relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bits states is of predetermined parity indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission second indicating means responsive to bit states for producing a second indicating signal indicating whether the number of
Claim 3. (Continued) second bit states occurring in such sequence prior to a current bit is odd or even, transition modifying means responsive to said first and second indicating signals and to the current bit and an adjacent bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, limited look-ahead means responsive to said first indicating signal, a current bit and a limited number greater than two of next succeeding bits for producing a disabling signal at the onset of any such sequence that terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and means responsive to said disabling signal for disabling said transition modifying means for the transmission of signal transitions corresponding to all of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 4. Apparatus in accordance with Claim 3 wherein said transition modifying means modifies the transmission of signal transitions to provide a single transition corresponding to each pair of second bit states of such sequence where the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 5. Apparatus in accordance with claim 1 or claim 3 further including decoding means responsive to transmitted signal transitions for indicating the bit states of the binary data transmitted, said decoding means comprising synchronizing means responsive to transmitted signal transitions for providing timing signals identifying bit cell intervals, detection means responsive to said transmitted signal transitions and said timing signals by producing transition identifying signals identifying received signal transitions as relatively early or relatively late in respective bit cells, and bit state recognition means responsive to said transition identifying signals by indicating a bit cell as being in the second bit state under any of the conditions of (a) a relatively late transition for the respective cell, (b) a relatively early transition for the respective cell where there is no transition for the next succeeding cell, and (c) no transition for the respective cell where there was no relatively late transition for the next preceding cell, and by indicating all other cells as being in the first bit state.
Claim 6. In a self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states of a sequence of data bit states are normally transmitted by signal transitions relatively early in respective bit cells and logical second bit states of said sequence of data bit states are normally transmitted as signal transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, said method including generating a first indicating signal when the number of first bit states in the sequence of data bit states is of a predetermined parity, detecting the onset of a sequence of second bit states following a first bit state productive of said predetermined parity that might introduce a DC component into the transmitted signal with normal transmission, and in response to said first indicating signal, the state of a current bit and the state of an adjacent bit modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, the improvement comprising in response to said first indicating signal examining a limited number greater than two of bits next succeeding a current bit to determine at the onset of any such sequence if the sequence terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and inhibiting said modifying of the transmission of signal transitions corresponding to any of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 7. A method according to Claim 6 wherein transmission of signal transitions is modified to produce a single transition corresponding to each pair of second bit states of such sequence when the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 8. In a self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states of a sequence of data bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states of said sequence of data bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively late in the next preceding bit cell is normally suppressed, said method including generating a first indicating signal when the number of first bit states in the sequence of data bit states is of a predetermined parity, detecting the onset of a sequence of second bit states following a first bit state productive of said predetermined parity that might introduce a DC component into the transmitted signal with normal transmission, generating a second indicating signal indicative of whether the number of second bit states in such sequence prior to a current bit is odd or even, and in response to said first and second indicating signals modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component, the improvement comprising in response to said first indicating signal examining a limited number greater than two of bits next succeeding a current bit to determine at the onset of any such sequence if the sequence terminates within said limited number of next succeeding bits and would not introduce such DC component with normal transmission, and inhibiting said modifying of the transmission of signal transitions corresponding to any of the second bit states of such sequence that would not introduce such DC component with normal transmission.
Claim 9. A method according to Claim 8 wherein transmission of signal transitions is modified to produce a single transition corresponding to each pair of second bit states of such sequence when the first of the pair is an odd second bit state, which single transition is transmitted relatively early in the respective bit cell for the first of the pair.
Claim 10. A method according to claim 6 or claim 8 wherein the transmitted signal is decoded by deriving timing signals from the transmitted data signal transitions for identifying bit cell intervals, producing transition identifying signals identifying received signal transitions as relatively early or relatively late in respective bit cells, and from said transition identifying signals indicating a bit cell as in the second bit state under any of the conditions of (a) a relatively late transition for the respective cell, (b) a relatively early transition for the respective cell where there is no transition for the next succeeding cell, and (c) no transition for the respective cell where there was no relatively late transition for the next preceding cell, all other cells being indicated as in the first bit state.