NL7907383A - DEVICE AND METHOD FOR ELIMINATING DC COMPONENTS IN TRANSMISSION OF BINARY DATA. - Google Patents

Description

'Λέ' * * .; - ι - y * £ r

VO 839T

Apparatus and method for eliminating DC components in the transfer of binary data.

| The invention generally relates to facilities for the transmission of binary data in serial form via an information channel. More particularly, the invention relates to a system and method for transmitting signals with inherent clock information, and more particularly | particularly to a system and method in which the transfer i; ; occurs over an information channel without response being obtained at a frequency with the * zero value. The invention in this regard relates to the encoding and decoding IQ of certain binary codes. The invention is particularly applicable in those cases where the information channel is given as a magnetic tape device.

Data or information in binary form are composed of data bits with information present in each bit 15. by one or the other of two states. - Such states are often referred to as a logic "1" and a logic "0". When working with information in binary form, it is necessary to recognize the respective logical state for each bit. Regardless of whether such bits are recorded in a band or otherwise recorded or broadcast, each information bit is contained in a bit cell defining a time interval or a space element in which the respective information bit is contained. The logical states can be characterized in various ways, such as "yes" or "no"; "+" or "up" or "down"} "true" or "false" and the like. When the information is recorded on a tape recorder, the states may be characterized by opposite magnetic polarizations.

790 73 83 - 2 - w

Also, it is common to characterize one state by a reference level and characterize the other state by a deviating level, in which case the second state may be indicated by a recognizable sig-5 sew while the first state is indicated: when such a signal is absent. There is positive and negative logic. For the present invention, it makes no further difference which of the two states is designated "1" and which is designated "0".

As already noted, the present invention is particularly applicable to information channels, such as magnetic recording channels. no response being produced when a frequency has the zero value, i.e. these channels do not transmit direct current. Generally, it is desirable to record the 15 data bits as close together as possible, keeping the number of times an error is introduced within acceptable limits. Various recording formats or binary data codes have been developed for recording binary data. With some codes it is desirable that a 20 'internal clock signaling is possible, i.e. the bit cell intervals can be identified in the recorded data bits without the need for separate time signal pulses. ·

For information channels that do not. direct current passes, for example, binary waveforms distortions with respect to the value of the maximum amplitude and the location of the zero crossings, which distortions cannot be eliminated by means of compensation networks with a linear response characteristic, unless the relevant channel gives a pronounced response at frequencies at least as large as the bit frequency. Such distortions are generally referred to as base level fluctuations, as a result of which the effective signal-to-noise ratio is reduced and hence the reliable 790 7 3 83 - 3.-. * deterioration of the registered signals is deteriorated.

A transmission format or data code used in a recording and reproducing system is described in U.S. Patent 3,108,261. According to a code known therefrom, logical ones are represented by signal transitions occurring at particular locations in the respective bit cells, more particularly at the center of a cell, while logical zeros are represented by signal transitions at other locations. 10 s occur in the respective cells, more particularly at the beginning or at the leading edge of each bit cell. In this known format, every transition occurs at. suppresses the beginning of a bit interval following an interval where a transition occurs at its center. Verbandη connection with the asymmetry of a waveform induced under this discipline creates a difficulty as it introduces a DC component into the information channel.

However, a code based on this known code in which the DC component has been eliminated is known from an art "Zero-Modulation Encoding in Magnetic Recording" by A.M. Patel and published in IBM J. Res. Oevelop., Vol. 19, No.4, July 1975. Such a format commonly denoted by ZM is based on the above format according to the above-mentioned US patent for most input series; sequences of the 25 form 0111 ... 110 with an even number of ones, however, are encoded with special rules. Although this code eliminates a DC component in the encoded waveform, it does at the expense of requiring that each string to be coded in a special manner be recognized prior to coding any portion of the string. Such a prerequisite in scanning the sequences involves a code delay Calsook encoding memories approximately the same length as the longest possible 790 7 3 83. ί .¾ • '- 4 - series of the indicated species. In order to avoid that an "infinite" memory is required, provisions in the above Patel * system have been made to allow the input sequences to run periodically. are distributed while appropriately selected additional 5 parity bits are inserted. In practice this means that in order to accommodate these bits to be inserted, a frequency change is required. In addition, the bits necessarily take up some space available for the recording.

Another code based on the code from the above-mentioned US patent, in which a DC component has been eliminated, is known from US patent 4-027,335, this format which is sometimes referred to as 2nd Miller. Miller or Miller format, for most input-15 arrays is also based on the original Miller format of the above-cited U.S. patent, and arrays that would introduce DC components are encoded under special rules. However, with the Miller format, it is not necessary to look ahead beyond one bit interval, and therefore a 20 "long" memory and additional parity bits are not required. 2. With the Miller format, at the beginning of a series of 1s marked whether or not the series could be of the type producing a DC component, where if upon reaching the end of such a series it appears that the series is indeed of the type, where under the regular Miller format a DC component will be obtained, the encoding is changed to eliminate the transition that would have caused DC unbalance.

The format used in the present invention is also based on the original Miller code 2 and is an alternative to the Miller format in that it also eliminates any DC component without a long memory or extra parity bits are 790 7 3 83 ë. Λ - 5 - required. In the context of the present invention, it is also noted at the beginning of a series of ones whether or not the series could be of the kind producing a DC component; however, instead of waiting 5 to see what the sequence will turn out to be, the encoding ... is changed at the beginning of the sequence of ones to correct any possible imbalance. After this, the encoding at the end of the sequence of ones is changed as necessary to obtain the regular Miller format without introducing DC-10 current.

According to the invention, a stream of binary data received at a frequency of 1 / T bits per second is encoded to form a binary waveform with a minimum interval between transitions of T seconds, a maximum between 15 transitions of 2.5 T seconds, an absence of direct current. , components, and a maximum value for the running integral of the waveform of 1.5 T seconds but half the magnitude of the transition. The encoding procedure does not require a frequency change, while an encoding delay of only 2 T seconds is required. Decoding requires inspection of no more than 2.5 consecutive bit intervals; all this means that the occurrence of errors is limited. The format used in the context of the present invention is an alternative to the Miller format, where, as with the latter format, the Miller code requirements for pronounced response at high frequencies and with the characteristic inherent in the ZM code with regard to freedom of DC components, and without the need for frequency switching and the application of redundancy, as well as without the need to use a long memory. The format 2 used in the context of the invention represents an improvement over the Miller format, since no more than 2.5 T seconds are needed between transitions 790 7 3 83 -6-, p. Miller - measure between transitions up to 3 T seconds. Existence. A further improvement of. the proposed format shows that in many instances any accumulated DC charge is "undone" rather than at the Miller format. is and in no case later. Such

Means that the content at low frequencies. this size • 2 is smaller than that of the Miller size.

. Although Bij 'is a simple embodiment of. the present invention does not require any long memory, falls within the scope of the invention is a format with Restricted Forward Requirements, which may be used to reduce the Bandwidth Requirements of the Associated Transmission System .

More specifically, In the Basic Format of the present invention At the Termination of Certain Sequences, time intervals T5 are introduced between 2.5 T transitions; In the Miller format, on the other hand, the maximum time interval between transitions is only 2 T. Since the 2.5 1 time intervals between transitions occur only in series, if no net direct current component would be present in them using the standard Miller format. , 20 results from the present format, a problem which would not exist when using the Miller format. The Need for additional Bandwidth will be less if the present format were to be applied only if otherwise a parallel current component were present, since then the maximum time interval between transitions is 2 T (Miller produces a time interval 3 T between transitions When encoding Bit strings, which would otherwise introduce a parallel stream component. However, this would require an infinite look-ahead capability to see whether or not a problem would exist before the start of encoding a string. It will be clear that such an infinite look-ahead capacity is not feasible, since this would require an infinite delay in encoding. As a Compromise In one embodiment of the invention, a Limited Forward Capacity is used, such as 5 Bits forward. The simple format according to the present invention is then used exclusively for encoding those, relatively rare arrays, exceeding this look-ahead capacity.

2

Like the Miller format, the format of the present invention can be characterized as a format 5 which is DC-free, which has an internal clocking effect, and which has no retrograde to zero, which format may be briefly denoted by DCF-SC-NRZ CDC-free, self-clocking-non-return-to-zero]. This format is also referred to as the Xerxes format. It is therefore the object of the present invention in the first instance to provide a system and method for. serial transfer of binary data on: an information channel that does not pass direct current, although the system and. the method can of course be used in combination with information channels that allow direct current · 15 to pass through. Another object of the invention is to provide a system and method in which the data is transferred in an internal clock mode. It is also an object of the invention to provide a system and method of the type described above, in which it is not necessary to use a frequency change or a large memory. The object of the invention is also to make such a system and such a method available without a maximum time interval between transitions that is the same length as is permitted in the 2

Miller format. According to another object of the invention, it is contemplated to provide such a system and method in which any accumulated charge is nullified in many cases earlier and in no case later than in the Miller format.

The invention will be explained in more detail below with reference to the drawing. In the drawing is:

Fig. 1 a number of binary signal waveforms including those corresponding to the format of the present invention, as well as various formats known in the art; Fig. 2 shows a set of waveforms using x Miller format and a format according to the present invention, as well as diagrams illustrating the integrals of the transmitted signals;

Fig. 3. a block diagram of a system according to the invention;

Fig. 4- is a diagram of an embodiment of an encoder that is. to be used in the system according to fig. 3;

Fig. 5 waveform diagrams illustrating the operation of the encoder shown in FIG. 4; Fig. 8 is a diagram illustrating an embodiment of a decoding device, an embodiment of a transition detector and a 2F clock, to be used in the system according to Fig. 3;

Fig. 7 is a set of waveform diagrams illustrating the operation of the device shown in FIG. 6;

Fig. 8 is a diagram illustrating a "look ahead" chain device for another embodiment of an encoder to be used in the system of Fig. 3;

Fig. 9 is a schematic illustration of an encoding chain device to be used in the circuit device of Fig. 8; and

Fig. 10 waveforms illustrating the operation of the circuit devices shown in Figs. 8 and 9.

In order to gain an understanding of the present invention and the resulting advantages, a first consideration will be given to various binary data formats as applied according to known techniques. Fig. 1 illustrates a number of binary signal waveforms that can be used to transmit information in series and in binary form 790 7 3 83 4 *-registrerenατ. For the waveform IX, use is made of the format of a form of the present invention. The waveforms of Figure 1 are divided into bit cells, each cell containing a data bit in binary form; in other words, the 5 binary information contained in each cell is given either as a state 1 or as a state 0. By *. For example, FIG. 1A shows the binary state of the information contained in a number of consecutive bit cells. The same information resides in the different IQ forms of the indicated waveforms.

Fig. IB is illustrative of a waveform according to an RZ format Cwaves returning to zero level] and where ones are indicated by parent or positive levels and zeros are indicated by child or negative levels 15 with the signal returning to a central or zero level between the cells.

A more common format is the NRZ data code C not returning to zero for which the waveforms of FIG. 1C

\ and 1D are illustrative. The waveform (NRZ-20 L] shown in FIG. 1C corresponds to the waveform of FIG. 1B CRZ] without going back to the zero level between the bit cells. With this code, the signal remains at 1 level for the full duration of a cell containing a 1-bit and the signal changes to the Q level when a Q-bit is in the respective bit-25 cell, so this code only contains transitions when successive bit cells are in different states. * -n fig-1D illustrated waveform NRZ-M, is illustrative of an NRZ code marked * where each logic 1 is indicated by a transition between the two levels, while a logic 0 is represented by the absence of such With both of these NRZ codes, there is the difficulty that there is a high risk of timing errors, since the signal during one relatively long period in the one 790 73 83 .9 -9-.

the other state can remain. It is therefore sensible to use codes with an internal clocking effect.

The waveforms shown in Figures 1E and 1F are illustrative of the so-called Manchester codes which are also known as bi-phase level (BI-0-LJ and bi-phase mark (ΒΙ-0-ΙΊ). In the code illustrated in FIG. 1E, the state of the bit in question is indicated by the direction of the transition located in the center of a particular bit cell. As shown in FIG. 1E, an upward transition 10 in the center of the cell is indicative of a logic 1, while a downward transition in the center of a cell is indicative of a logic 0. The code shown in FIG. 1F shows a center of a cell standing transition directed either upwards or downwards illustrative of a logic 1, while a logic 0 is indicated by the absence of any transition from the center of a cell Internal clocking at this bi-phase level signal is obtained by using to make the relevant zi ch transitions located in the center of a cell. Internal clocking at the bi-phase 20 marker signal code is achieved by introducing a transition at the beginning of each bit cell. Although these Manchester codes do not require DC transfer, the addition of the numerous additional transitions causes the required bandwidth to be significantly increased. A waveform illustrative of the format as known from US patent 3308,261 is shown in FIG. As with the code of FIG. 1F ', the logic ones are indicated by transitions in the center of a cell, while logic zeros are indicated by the absence of such transitions. However, in the Miller format, no time signaling transitions at the beginning of the bit cell containing a logic one are present, and transitions are suppressed if they otherwise occur at the beginning of the respective bit cells following a corresponding occurrence. transition located in the center of a cell. At the base 790 7 3 83 - 10 -s

Miller code means that for every logic-1 there is a transition in the middle of the cell in question, while for every logic Q there is a transition at the beginning of the cell in question, except for the case where a 5 logic O follows a logical 1. The suppressed transitions -r are indicated in the wave form according to fig. 1G by an X. Although for the Miller code only the smaller bandwidth of the NRZ code is required * and also the internal clocking of the Manchester codes, where there exists, this code is not entirely free of DC content. When applying this Miller code, certain series of logical ones and zeros can give an unbalance in the waveform. In the waveform shown in FIG. 1G, for example, due to the suppression of the transition between cells 11 and 12, a DC component can become introduced 15 which is subsequently not compensated for by suppressing an oppositely directed transition. If similar arrays occur repeatedly, the DC component will grow, as will be discussed in further detail below in connection with FIG. 2.

20 For a waveform using a

Miller format has eliminated the DC component by suppressing another, however oppositely directed transition. According to the Miller format, this is a transition that can be identified as a transition suppressed under the regime of certain rules that define the format. At 2 a particular form of the Miller format, the immediately preceding transition is suppressed, which is indicated by an X in the waveform of FIG. 1H, which is tantamount to being the transition located in the middle of the bit cell 11.

A waveform illustrative of the Xerxes format is illustrated in Fig. 11. In the Xerxes format, a DC component is eliminated by restoring those transitions suppressed in the Miller format, in series where they would otherwise give rise to a DC component, which is shown in FIG. denoted by the transition marked by R. Rather, this code eliminates a signal imbalance by encoding certain pairs of ones as a single-flank represented cell transition at the beginning of the cell corresponding to the first 1 of the cell. : respective pair, all this as indicated in fig. 11 by the transitions indicated by A, the transition in the cell corresponding to the second 1 of the pair concerned being suppressed, which is indicated in fig. 11: by a X.

With reference to Fig. 2, it will be further explained how the use of a Miller code results in a DC problem and how such a problem can be solved by applying the present invention. In a Miller code 15, the bits are indicated by the phase transition level. With one exception, the zero bits are indicated by transitions occurring in a relatively early portion of a bit, while single bits are indicated by transitions occurring in a relatively late portion of a bit. More specifically, in the illustrated waveforms, the zero bits are indicated by transitions at the beginning of a cell while the one bits are indicated by transitions located in the center of a cell. One exception is that those transitions that would occur within one bit of any previous transition are suppressed. As a result, transitions indicative of a zero bit following a one bit are suppressed.

In fig. 2A b, v. the binary states of consecutive bit cells in a data stream. Fig. 2B gives an indication of the kind of the different series indicated below. waveform shown in FIG. 2C is illustrative of a signal in which the bits of such a data stream are identified according to the Miller format. Fig.

2D illustrates the integral of the waveform according to FIG. 2C with respect to the level applicable to the center of a transition. The transitions are about one unit above and one unit below this middle level. The length of each bit portion is given by the time interval T. It should be noted that the integral returns to zero after each cycle of the Miller signal through the bit cell 7. After this, the integral remains negative and then progressively becomes negative. This results in the aforementioned direct current component, which gives rise to errors when the relevant information channel does not have the possibility to transfer direct current, as is the case with magnetic recording.

From the consideration of the waveform shown in FIG. 2C will. For the relevant example of data stream. show why this. so is. For each bit cell containing a one bit, the signal is balanced above and below the mid level, which gives no net change in the integral. When the levels for successive zero bits are opposite, the signal is also balanced which does not give a net change in the integral. When consecutive bits are separated by an odd number of one bits, the signal levels in the respective zero-containing bit cells are opposite and the signal is also balanced. A problem arises only when zero bits are separated by an even number of one bits. In that case, the signal levels in the respective zero-bit cells have the same polarity, resulting in a net area accumulation under the curve and a net displacement for the integral deviating from zero. Whenever a data sequence occurs in which two zero bits are separated from each other by an even number of one bits, a net displacement of the integral occurs. The displacement can of course go in one or the other direction and sometimes the displacement will return the integral to zero. However, it is also possible that the areas grow such as e.g. in Fig. 2D, 790 7383 • 13 - is illustrated.

It will be appreciated that a problem arises from suppressing the transition at the beginning of a zero state following a succession of an even number of one states, making the signal asymmetrical. The solution proposed for this problem according to the invention boils down to this.

2 that such a transition ,. not as is the case with the Miller format, it is suppressed, but rather certain pairs of ones are encoded as a single transition at the beginning of "10 each pair", the result of such discipline being illustrated by the waveform of FIG. 2E, wherein, each restored transition is indicated by an R, each cell flank transition before the flank, of the first cell of such a pair is indicated by an A, and each traditionally suppressed transition is denoted by an X. As can be seen from the integral designation for this waveform shown in Fig. 2F, there is no net current component *. This is of course only possible if the suppressed and preceding transitions can be identified by a decoder. if this is not the case, the information will be lost. The present invention forms part of a system and method for identifying these suppressed and raging transitions.

In order to explain in more detail how such an identification is realized, it is assumed that the incoming data stream can be understood as a combination of strings of four kinds: Cal a string of ones Cb1 a string of ones with a zero at each end, and where the number of ones is even i Cc) a. series of ones with a zero at each end and wherein the number of ones is odd; and C 001 a pair of zeros. In this embodiment, the number of zeros from the start of a broadcast is counted. If the number of zeros is even at the beginning of a sequence of 1s, the sequence 790 is 7 83 - 14 - of the type Ca] with no DC problem; encoding and decoding may be accomplished using the format proposed in U.S. Patent 3,108,261, cited above. It should also be noted that two consecutive zeros are not part of a series of the type Ca], Cb], or Cc] are part of the series CQ0] and also balance the signal. It is in the case where the count of the number of zeros prior to a series of ones is odd that the zero is part of a series Cb] or Cc] and may give rise to a problem if it turns out that the number of ones of the series is even, as is the case with the series Cb). At the beginning of. a series therefore indicates whether the series of ones may or may not give rise to a problem. The encoder includes provisions that allow one 16 bit cell to be viewed forward. If it is indicated that the sequence starts with a zero and can therefore give rise to a problem, and when the first one is encoded it appears that looking ahead that the next bit is a one, the encoder immediately acts to detect a possible 20 to correct the imbalance, in that the transition present in the center of a cell, which could occur for the first one of the series and which produces a transition CA] at the leading edge of the first, is shifted forward. The 1st transition CX] is suppressed for the second of the two 1-25 bits. When the code performs a search to encode the third bit, it looks for the next fourth bit, again determining whether or not a pair of one bits is present. If so, the encoder, as previously indicated, continues to form a transition at the beginning of the first of the two one bits, suppressing each transition for the second of the one bits. Whenever the sequence reaches zero, and if the number of one bits is even, indicating that the sequence is of type Cb), the next bit is encoded by an edge transition at the beginning of the bit . M-a-w. the transition CRO is not suppressed since it does not follow an in. center of a cell present transition. Examples 5 of such coding for the series of the type Cb) are given in FIG. 1I, in particular bit cells 9-12 and in FIG. 2E, more in. in particular bit cells Θ - 11 and 18 - 21.

In such coding, it holds that any even number of one bits bounded by zero bits. which are part of the series, - does not introduce a galling current component. On the other hand, when a series of one bits occurring in a series of the type starting with zero is encoded according to this format and the encoder reaches the phase where a last one is encoded which is not part of a pair of ones, but rather is followed by the zero ending the sequence, indicating that the sequence is of the type Cc), the corresponding one being encoded by a transition present in the center of a cell, the transition for the next zero is suppressed as well as 2G with the regular Miller format, so that in this case also no net power component remains in the signal. Examples of such coding for series of the type Cc) are shown in FIG. II, in particular bit cells 2-6, and FIG. 2F, in particular bit cells 5-7.

As set forth above, the integral of the resulting waveform for the Ca), Cc), or C00) series always reaches zero at the end of the series when the Miller format is applied to these four series Ca ), Cb), Cc) or C00). This does not apply only to the integral 30 of the waveform of the series of the type (b).

Rather, it integrally reaches a value of + 2T, the sign depending on the direction of the last transition prior to the sequence. Furthermore, if a series of the type Cb) is followed after certain combinations of other series types by another series of the type (b), then the integral of the series joined together into one whole can grow-.

For certain types of these merged arrays, the running integral grows without limitation and this is the situation where the waveform gets equal current inhash as illustrated by the waveform of FIG. 2D.

For the purposes of the present invention, a sequence of type tb) is recognized and coded such that any form of DC component is eliminated. According to the present invention, sequences of types (a) and (GQ) are coded according to the Millei Farmate, and series of types Cb) and Cc) are encoded according to the special Xerxes rules. Between series of types Ca) and C00) on the one hand and series 15 of types Cb) and Cc) on the other hand, a distinction can be made by maintaining a modulo two count of logical zeros from the start of a coding operation. This distinction is based on the fact that all the series contain an even number of zeros. Series of the type Ca) do not have 20 zeros. Series C00) consists of two zeros. Series of types Cb) and Cc) and consisting of ones with a zero at each end, have two zeros. Therefore, if an even number of zeros is counted when a one appears to be encoded, the sequence is of the type Ca). On the other hand, if the number of zeros counted is odd when a one appears to be encoded, the sequence is of type Cb) or Cc).

Obviously, at the beginning of a series, no distinction can be made between a series of the type Cb) and a series of the type Cc), since the difference between the 30 series can only become apparent when the end of the series is determined, or the count is odd or even. Therefore, in such arrays the special Xerxes coding is applied from the beginning of the ones and the coding at the termination 790 73 83-17 V. s of ds series concerned is different and depends on the result of the count. To this end, a modulo-2 count of logical ones is maintained from the last odd zero. The ones are encoded in pairs by a single over-5 gang CA) at the beginning of each pair, until a πμΐ is reached, indicating the end of the sequence. When an odd number of ones is counted at that time, the last one and the. to the. end of the sequence occurring zero encoded using the. usual Miller code .. When the count of 10 ones is even, the zero is encoded by a cell flank junction CR) * which restores a junction which is at. application of the Miller code would have been suppressed, which can be said to fit the Miller code as no mid-cell junction was present as a marker for the previous one.

The sequence of the type Cc) as given by the bit cells 5, 6 and 7 (Fig. 2) contains only a single one bit and is encoded by applying the Xerxes rules since looking forward over one bit cell has shown that. the zero bit is in cal 7. In the Xerxes format, therefore, a forward look over one bit takes place.

With the Xerxes code, a transmitted signal is obtained from which the original data can be derived by decoding. Each transition occurring in the center of a cell is decoded as a one. A cell flank transition in a bit cell followed by a cell with no transition is decoded as a 1 for each cell. Any other cell flank transition is decoded as a 0. Any other cell in which no transition exists is decoded as a D. Except where signal is lost, no two consecutive cells without transitions can occur. This is not to say that longer intervals between transitions cannot occur, since the termination of a series of type (c) may result in a time interval of 2.5 T between 790 7 3 83 -18- between transitions. exists as shown in FIG. 1, in particular bit cells 3-5, where cell 3 has a cell flank transition, cell 4 has no transition, and cell 5 has a transition in the middle. Considering signal loss outside-5, this is the longest interval seen with the Xerxes. format is permissible.

A system and method according to the present invention therefore make it possible to transfer data in binary form over an information channel that does not transmit direct current, and wherein information is transmitted with an internal clocking action.

As stated in the foregoing, it makes no difference which "yy" the "binary" states ~ as the first logs ~ which "" binary "" states are considered a logical 0. HIn In the foregoing and in the following description it has been assumed that this state as indicated by the transition occurring in the center of a cell is the one state, while the state as indicated by the cell flank transitions is considered to be the zero state. cell center junction ”used to identify a relatively late bit cell junction that is not necessarily centrally located, while the term“ cell flank junction ”is used to identify a relatively early bit cell junction - the junction not necessarily exactly exists at the beginning.

Fig. 3 shows a general block diagram of a system for coding a data stream in series form and as binary bits, all this according to the format described above, in which this information is transferred over an information channel and the received signals for final use 30 are decoded. A data source 10 outputs binary data in series form to a pad 12 having a rhythm determined by clock pulses supplied from a clock signal source IS over a pad 14. The data provided by data source 10 may have originated from any number of 790 73 83-19 sources. Leaving aside how this data came into existence, this data is converted into binary form by known means, and arranged to be serialized by clocking under the control of the clock pulses present on the path 14.

The clock signal source 16 produces periodic clock pulses with a frequency 1F. The clock 16 may include a J-K flip-flop driven by double clock pulses supplied over a pad 17. from a clock 18 that is double; IQ - produces clock pulses with a frequency of 2F. The clock 18 can be composed of any number of oscillators known per se. Deza clock pulses and double clock pulses should have short rise times; to have. Since the transitions serving to indicate logical ones and logical zeros are resp.

15 located in the center of a cell and at a cell flank or more generally at a later phase and an earlier phase, the clock delivers 16 clock pulses with two phases, namely phase 1 (01) and phase 2 (62). The clock pulses can be crenellated with the phase 2 pulses being an inverted version of the phase 1 pulses. Phase 1 (01) clock pulses are applied through path 14 to rhythmically drive data source 10. The phase 2 (02) clock pulses are present on the pad 20.

An encoder 22 receives serial data from the data source 10 via the path 12, as well as 01 clock pulses 25 from the path 14 and via a path 24, and 02 clock pulses via the path 20. Double clock pulses are sent from the path 17 and via a receive path 25. The encoder 22 updates the received data according to the previously described Xerxes format according to the invention. The encoded data is fed via a path 26 to an information channel 28 which may consist of a magnetic tape recorder, whereby the information is recorded and subsequently read. The output of the information channel appears on a pad 30. The transitions in 79073 83 - 20 - the signal is detected by a transition detector 32 which produces a signal representative of the transitions on a pad 34.

These signals representative of the transitions are received by a decoder 36 whereby the information is restored to its original form or a related form, the information thus decoded about a pact 38 being fed to a data consumption circuit 40. previously noted, a signal format according to the present invention has an internal clocking effect. I.e. the coder 36 must time-correspond to the original 01 and 025 signalerv to be able to determine when a transition has occurred in each bit cell. Such a synchronization is achieved by using a clock 42 which emits clock pulses: with the double frequency 2F. In order to synchronize the clock, signals from the decoder can be applied over a path 44 or signals from the transition detector 32 can be applied over a path 46 will be constructed. In each of these cases, appropriate time signals are applied to the data consumption circuit 40> these signals may be applied either directly from the clock 42 over a pad 50 or indirectly through the decoder 36 and over a pad 51. It should be noted that a pad can contain multiple conductors.

Although several other circuits could be used, a preferred embodiment of an encoder 22 is shown in FIG. IF with the associated waveforms as shown in FIG. 5. The symbols placed in fig. 5 at the beginning of the different waveforms indicate the 30 places where the waveform in question arises in the chain arrangement according to fig. 5. The input signals for the encoder 22 are the phase 1 C01] and phase 2 C02] clock pulses applied from clock 16 over paths 24 and 20, the double clock pulses from clock 18 over clock 18. pad 25 are supplied, and the input data is supplied via the pad 12. Also, a reset pulse T is applied across a pad 52 from a diode pulse source 54. An input terminal 56 is coupled to the emitter of a tri-polar transistor Q10, the base of which is connected to ground. The collector of this transistor 010 is coupled through a node 57 to the input terminals of an AND gate 55. The AND gate 55 operates to convert the voltage levels located at its input terminals irr TTL levels idxeè at the output of which exist. The cathode terminal of the terminal diode D10 is coupled to the node 57 err the anode terminal of this diode is connected to ground. A resistor R10 is connected between the node 57 and a positive voltage supply source so that an auxiliary voltage circuit is formed between the transistor 010 and the AND gate 55 in combination with the diode D10. The start pulse source 54 is arranged to produce a reset pulse I when a start signal is applied to its input terminal 56.

This reset pulse I is supplied to the encoder 22 to bring the various parts thereof into an initial state.

As shown in Fig. 5A, the 01 clock pulses are equal pulses that periodically appear with a period equal to the length of one bit cell, which pulses have short rise and fall times, as well as a pulse duration corresponding to half of one bit cell. . The 02 clock pulses are identical in shape to the 01 clock pulses, and are delayed by a distance corresponding to half a bit cell interval. It has thus been achieved that the 01 clock pulses have a rising edge at the beginning of each bit cell and the 02 clock pulses ± i have a rising edge in the middle of each bit cell. The 01 and 02 clock pulses can be produced by the clock signal circuit 16, double pulses coming from the clock 18 and with a frequency 2F (Fig.

790 7 3 83 - 22 - 5G) are fed via the path 17 to the clock input CLK of a JJC flip-flop 59. The 01 clock pulses appear with a frequency 1F at the Q-connection of this flip-flop and the 02 clock pulses. appear on the Q jack. In a particular embodiment of. the invention, the 2F clock signal has a frequency of 2MHz, and the 1F clock signal has a frequency of 1MHz. The data bit rate is therefore equal to X mega-1 bit per second.

Ds input data (Fig. SBJ are applied in the form designated by NRZ-L to the input terminal D of a D-flip-flop SCT. The 01 clock pulses * are applied to the clock signal terminal of the D-flip-flop 60, whereby each positive-directed transition of the 01 clock pulses (shown in Fig. 5A) results in the signal at the D input being transferred to the 15 Q output terminal. D-flip-flop 60 appears is shown in fig. SC as X ^ + ^

This is the signal for the bit to be encoded immediately following the bit Ck] currently being encoded. At the same time, the inverted signal Χ ^ + ^ · appears at the Q output terminal of the D-20 flip-flop 60. The signal Xj ^ is applied to the input terminal 0 of a D-flip-flop 62 which appears when the immediately following E1 pulse applied to its clock terminal transmits the signal to the output terminal Q of the D flip-flop 62.

Therefore, the signal shown at the terminal Q of the D-flip-flop 62 shown in Fig.5D is X. ie, the signal for the bit being encoded, the inverted signal X ^ appearing at the output terminal Q. Starting from these signals X ^ + 1, \ and \ worc ^ and the transitions for the coded signals determined.

0 parity is determined by a JK flip-flop 64. To this end, the X ^ signal is applied to the J and K input terminals. When rhythmically driven by the 01 clock pulses, the Q- 7907383 '- 23 - 35. * * output terminal obtained a modulo 2 count of the number of zero bits counted from the start (reset signal) to the bit to be encoded, i.e. the count of the zero bits encoded. When equals 0, the 5 state of the JK flip-flop changes. when the next 01 clock-p pulse is applied thereto ,. in order to count a zero bit ,. When "X ^ equals 1, the state of the JK flip-flop remains unchanged. The output signal PCO developed at the terminal Q shown in FIG. 5E is therefore a parity count * which is signal 1. or 0 is when the number of passed: zero bits has been odd or even. * The inverted signal P (0) appears at the output terminal 0.1 parity is determined by a JK flip-flop 66. X ^ signal applied to the J input terminal while no signal is applied to the k terminal When a U is applied to the J terminal, the JIC is flip-flop.

66 operates in the same manner as JK flip-flop 64 and counts modulo 2's when 01 clock pulses are applied thereto. When a 1 is applied to the J terminal, the count value is reset to 0. The output PCD as developed at the output terminal Q and shown in: Fig. 5F is therefore a parity theorem which is 1 and 1, respectively. 0 is when it. number of ones that have passed since the last previous zero bit odd resp. has been a while. The inverse signal PCI) appears at the Q output.

The input data is encoded by applying the signals developed by the D flip-flops 60 and 82 and by applying the JK flip-flops 64 and 66 to the NOR gates 72, 74, 76 and 78 in different ways. are prepared by the 01 and 02 clock pulses. An insight into the operation of these gates can be obtained by checking when an output transition pulse is not caused and by thinking that a transition pulse occurs under other conditions. It also makes sense to assume that the transition pulses appear in one of two parts of the bit cell, with a relative one. early appearing or cell flank junction is referred to as an a junction and a relatively late appearing or cell mid junction is referred to as a b junction. When an a-y transition is considered in the first instance, the primary signal is generated by the NOR gate 72 which has three inputs. One of these input signals is the signal from the Q terminal of the 0-f lip-flop 62. Another input signal is the 02 clock-10 signal. When the third input signal is 0, the output signal of the NOR gate is 1 when X ^ is 0 and the 02 clock signal is 0. The 02 clock pulse which is the inverse of the 01 clock signal shown in Fig. 5A is during the first or a half of each bit period or bit cell 0. A signal a, ie the inverted 15 "value of a, is the signal sail the first half, will therefore be 1 whenever X ^ is 0 and therefore when X ^, the signal being encoded is 1. This means that a cell flank a junction will appear differently, ie when X ^ is 0, ie the normal encoding of a zero bit.

The normal Miller format requires those transitions CX in Fig. 1g] that appear at a time interval less than that of a bit cell after a previous transition, ie for zero bits following a one bit in the normal Miller code. , to suppress. This is achieved by a D flip-flop 80, the Éj output terminal of which is connected to its own D input terminal and which flip-flop is supplied with clock pulses in the form of the 2F claw pulses (Fig. 5G3. The output of the NOR gate 72 is also connected to the D input terminal to form a so-called wired OR gate at the node 81. The gates 72, 74, 78 and 78 as well as the flip-flop 80 are preferably of the emitter coupled logic indicated type However, other logic types can be used for this when instead of the so-called wired OR gate in node 81 79073 83 - 25 -.

* * * an OR gate is used.

Since the D flip-flop receives 80 clock signals with the double frequency 2F, this flip-flop is driven in synchronism with each half of the 01 and 02 clock pulses. The signal 5 fed back from the Q output is therefore the greased one; .yy. reverberated from the signal previously passed in the immediately preceding half bit by clock signal operation. As will be explained further below. is explained when the NQF gate 72. is prepared by the 02 clock pulse, the Q output signal; From the D flip-flop 80, sew the signal encoded in the last half of the previous bit b ^ _ ^, i.e. a 1 is returned when a cell center transition was present in the previous bit cell. When this signal is added to the output of NOR gate 72, this signal makes a ^ 15 a 1 when in the previous bit cell a cell mid junction was present, and therefore a 0 suppressing a cell flank junction becomes when a cell mid junction was present in the immediately preceding bit cell. This is in accordance with the standard Miller format. This also makes it possible to insert a transition (R in fig. 11 and 2EJ.

whenever the Cell center transition of the previous one bit has been suppressed according to the Xerxes format.

This Xerxes format also makes it necessary to insert a cell flank junction (A in Figures 11 and 2E] for the series of 25 odd ones or two ones, ie the series of types (b) or Cc]. This is realized by the NOR gate 74. An input signal is the signal X ^ from the Q output of the D flip-flop 60. The signal X ^ + 1 is 0 when the inverse X is equal to 1 , indicating that the bit after that coded K + 1; 30 is a 1. A second input signal is PCQ] from the Q output of the JK flip-flop 64. The signal PC0] is 0 when the inverse P (0] is a 1, indicating that there has been an odd number of zeros from the start, indicating 790 73 83 - 2B - which is not a series of the type 'Cb) or Cc). A third input signal is PCD from the Q output of the JK flip-flop 66. The signal PCD is 0 when the bit encoded since the last Q does not represent an even number of ones.

As a consequence, the output of the NOR gate 74 is only 1 when an odd 1 of a pair of ones in a sequence of type Cb) or Cc) is encoded. This output signal is applied to the third input of the NOF-. gate 72 so as to exit this gate 72 below. introducing an additional transition.

; The signal a. 'Cfig.SH), which is applied to the D input of the 0-flip-flop 80 during the first half of a bit cell, is therefore given by:

a. = -t * pCo Ptu) CD

-K -k-1 -k k + 1 J

The term b, is the Q output of the flip-flop 80, which K-i output makes both a ^ _ ^ and b ^ ^ available in successive double frequency time slots. For the above equation, however, only b ^ _ ^ is made available and in the encoding operation, a,. no 20 used.

As for the b transition, the primary signal is generated by the NOR gate 76. An input signal comes from the Q output of the D flip-flop 62. The other input signal is the 01 clock signal. When the signal being encoded is X X equal to 0, the NOR gate 76 is prepared by the 01 clock pulse during the second or b-half of each bit cell. Therefore, in the absence of any other input signal, a signal b, or the inverse of b, will be 1 whenever X ^ equals 0. Otherwise, a cell center transition b will appear otherwise 30, ie when X ^ equals 1, ie the normal encoding of a 1-bit.

The Xerxes format makes it necessary to use that transition CX in Figs. 11 and 2E) that would otherwise normally be produced when encoding the 'second Cof parity!). of ones in a sequence of the type Cb) or Cc). Such suppression is realized by the NOR gate 78. An output signal is P (0) from the 5 Q output of the 3K flip-flop 64. The signal PCQ) is 0 when the inverse i.e. PCQ) equals 1 * indicating that an odd number of zeros has passed from the start, indicating that it is a series of type Cb) or Cc) A second input signal is PCI) from the Q-: 10. output of the 3K flip-flop 66. The signal PCD equals 0 when its inverse PCD equals 1, indicating that the previously encoded bit was a 1. A third input signal is the 01 clock signal which causes the NOR gate 78 to become during the b-half of the bit cell. b, derhal-15 is also equal to 1 and b is equal to 0 when an even parity one is encoded for series of the species. Cb) and Cc).

Furthermore, with the Xerxes format it is necessary to: in certain situations transition from the cell center to the. cell flank CA in Figs. 11 and 2E). This advance is accomplished by the NOR gate 74 as described above. In order to complete the shift, it is necessary to suppress the cell center transition that would otherwise occur with the normal encoding of a 1. This is accomplished by the D flip-flop 80. In this case, it is the α 1 signal that is fed back to the D input during the time interval that the NOR gates 76 and 78 are prepared. As a result, the signal b ^ becomes 1 every time the signal a ^ is 1; therefore, the signal b ^ becomes 0 every time the signal is 1, suppressing the cell center transition in the same bit cell.

The signal b (Fig. 51) is applied to the D input of the 0 flip-flop 80 during the second half of a bit cell and this signal is therefore given by: 790 7 3 83 -28- bK = aR + XR + PCO ') PCI)' t23

The signals b and a are mutually exclusive in time as the former signal is 0 during the first half of a bit cell and the latter signal is 0 during the last half of a bit cell. This is so because the respective preparation pulses 02 and 01 are mutually exclusive. The signals a ^ and b ^ are therefore applied without interference to the D input of the D flip-flop 80 / where these signals are sequentially transferred to the Q-IC output by the operation of the clock 18 2F clock pulses, at which the inverse signals and are generated at the Q output. The combined signal developed at the Q output, as shown in FIG. 5J, is therefore delayed by half a bit from the input signals 15 present at the terminal. D. As described above, the delayed signal is fed back to the D input terminal.

The inverted signal ZQ as developed at the Q output of the D flip-flop 80 is in the NRZ-L form. The 20 is applied to the J and K terminals of a JK flip-flop 82 driven by the 2F clock pulses (FIG. 5G) from the clock 18. The flip-flop 82 causes, that in response to the level values of the NRZ-L shape of the data present at the Q output of the flip-flop 80 transitions occur. The clock pulses cause a state change at the Q output of the flip-flop 82 every time the input level is 1, while this state remains unchanged every time the input level is 0. This achieves the result that a change in state occurs, in other words, a transition, each time when the signal a ^, ^ b b ^ _ ^ is a 1 when a 2F clock pulse appears. This produces an output signal at the Q output in accordance with the Xerxes format as shown in Fig. 5K.

790 73 83 - 29 -

The special tasks of the encoder shown in FIG. 4 can be summarized as follows. It becomes through this encoder. beginning of any sequence of ones that may be of type (b). This is achieved in the encoder shown in Figure 4 by means of the D flip-flop 64 which switches every time a zero is encoded. A parity count is given at the v Q output PCD) thereof. . . if the number of zeros is odd or even at the beginning of a sequence of 1s. If the count is odd, this gives an IQ. indication that the series is of type tb) or of type Cc) ».

. . The encoder. recognizes at the end of such series whether it is of the type: Cb) or of the type Cc). This is accomplished in the encoder of FIG. 4 by means of the flip-flop 66 which switches each time a 1 is encoded and is released each time a Q is encoded. The Q output CPC1)) thereof indicates a count whether the number of ones is odd even. If when a Q is reached this number is odd, then the series is of type Cc) i if this count is even this series is of type Cb). 20 Series of ones and of the kind. Cb) or of the type Cc) are encoded by a transition at the flank of the first Coneven. parity) one of a pair of ones, the last 1 of a sequence consisting of an odd number of ones of the type Cc) encoded according to the standard Miller code of U.S. Patent 3,108,261. All other codings are in accordance with the requirements of this U.S. Pat. 3,108,261, with the standard Miller code the 0 at the end of a sequence of type Cb) would be coded with a cell flank transition, as with the Xerxes format for 30 the previous 1 no cell center transition exists.

As indicated in FIG. 3, the coded information present on the lane 25 is passed through the information channel 28 and then supplied through the lane 30 to the transition detector 790 7 3 83 - 30 - 32. The output signal of this averaging detector is applied to the 2F-Clock 42 via the lane 46 and this signal is applied to the decoder 36 over the lane 34. The output of the clock 42 is applied to the decoder 36 via the lane 48. Examples of the clock 42 , the decoding device 36 and the transition detector 32 are shown - in Fig. 6. The time diagrams valid for the circuit shown in Fig. 6 are represented by the waveforms according to Fig. 7, in which letters surrounded by circles in Fig. 6 correspond to the corresponding wave forms in Fig. 7.

In the arrangement shown in Figure 6, a received signal having a waveform as shown in Figure 7A is applied through the path 30 to the transition detector 32. This transition detector 32 includes a limiter circuit 132 and a differentiator circuit 134 The limiter circuit 132 gives a large gain of the input signal and cuts off the tops thereof, so that a correspondingly limited output signal is output on the path 34 with sharp transitions corresponding to the zero crossings of the input signal and as represented by the waveform 20. according to fig. 7B. The inverted output from the limiter 132 is applied to the differential circuit 134 which generates opposite phase signals in amplifier 136. The two outputs of this amplifier 136 are applied to both NOR gates 138 and 140 with the inverted signal when applied to the N0F gate 138 is slightly delayed by a delay line 142, while the non-inverted signal when fed to the NOR gate 140 is slightly delayed by a delay line 144. The differential circuit 134 thus indicates the path 46 a transition signal, the waveform of which is shown in FIG. 7C, wherein a pulse exists for each transition occurring in the input signal of FIG. 7A.

In this embodiment, the clock 42 includes an impulse 790 7 3 83 s * - 31 - oscillator which produces a signal having a shape shape as shown in Figure 7D and which signal, after amplified and limited, becomes a crenellated signal as shown in fig, 7E and which is present on the track 4Θ. The integrated circuit A3, which forms the clock 42 in the treated embodiment, is of a commercially available version, in which the pins \ 1 and 16 are grounded and the pin 0% connected to -5.2 V. The phase of the pulses present on the track 46 with respect to the vibrations in the tank chain of the oscillator determines the acceleration or deceleration of these vibrations, in order to synchronize the clock output signal present on the track 48 with the transitions occurring in the input information as present on lane 30. The phase of the clock output signal can be set. by a variable coil 146, so as to bring the clock pulses as shown in Figure 7E into an appropriate time relationship to the transitions such as appear in the limiter output signals as shown in Figure 7B.

The second output signal, as shown in Figure 7B of the limiter 132, is coupled via the path 34 to the decoder 36, more particularly to the D input of a D flip-flop 148 forming part thereof. The clock pulses from the clock circuit 42 shown in FIG. 7E are applied via the path 48 to the clock input terminal of this D-flip-flop 148. This transfers the data from the D input terminal to the Q The output terminal of the D-flip-flop 148 produces a signal of the form shown in FIG. 7F corresponding to the input data of FIG. 7A with a delay corresponding to a half cycle of the 2F clock pulses. The signal present at the Q output terminal of the D flip-flop 148 is applied to the D input terminal of a D flip flop 154. The 2F clock pulses are applied to the clock signal terminal of the D flip flop. flop 154. The D flip-flop 154 is therefore operative to transmit the 790 73 83 - 32 - Q output from ds D-flip flop 148, that output being at the Q output terminal of D-flip flop 154 Fig. 7G) is effected with a delay corresponding to one 2F clock pulse, in other words a shift corresponding to half a bit cell. The 2F clock pulses are also applied to the clock signal terminal of a JK flip-flop ISO, the J terminal of which is maintained at a positive potential and the J terminal at ground potential. This makes the flip-flop ISO. switched to produce an output signal of the form shown in FIG. 7H at its Q terminal. These are clock pulses with the frequency 1F, which correspond to the bit cell frequency of the data. These clock pulses are applied to path 51 as the output clock pulses supplied to the data consumption circuit 40.

The signals as present at the D input and the Q output of the D flip-flops 148 and 154 are applied to an Exclusive OR gate 172 which detects a difference between the clawed data signal (Fig. 7F) and the clocked and delayed data signal Cfig.7G3. The output of this gate 172 therefore indicates that every transition in the input data occurring since a previous 2F clock pulse on the clock signal terminal of the D-flip-flop 154. An output 1 of the gate 172 therefore indicates an data transition as shown in Figure 7I.

The data transition signals as shown in Fig. 7I

are applied to the S input terminal of a 5-bit shift register 174. In the discussed embodiment, this shift register 174 of a commercially available version CTI 7496] is indicated with the numbering of the connecting pins.

The shift register 174 is driven by the 2F clock pulses Fig. 7E]. The shift register is operative to clock the transition data from gate 172 in serial form during each clock pulse, shifting the data along the 5 output terminals behind 790 73 83 * i * - 33 - Since the shift register is driven by 2F clock pulses advance the register at each half bit cell. The bit cells occur sequentially at a frequency 1F, each bit cell containing two consecutive halves a and b. These halves therefore appear with the double frequency 2F, which is the clock frequency for the 5-bit shift register. The data are from the; decoder 36 clocked out via track 38 at the bit frequency 1F and as shown below. yet; will be explained in more detail. When the '10 decoded bit is thus clocked out, the output signals include EYa, Qgj. Oc ,. Qp and 0p of the 5-bit shift register 174 the transition data with respect to the half bit cells b ^ + ^, a ^ i »b ^, a ^ and b ^ _ ^. What the output signals contain in the next 2F clock operation is of no importance since the output signal is out. the decoder is only clocked out once per bit cell. The output signals are therefore indicated in FIG. 6 such that the state is indicated when the decoded signal is clocked out via the output path 38.

The five output signals from the shift register 174 are combined to form the decoded signal. The signals are combined to identify ones, decoding any bit that is not a one as a zero. In the above-discussed Xerxes encoding format, there are three possibilities according to which one is encoded.

Normally, ones are encoded by a cell middle junction, ie a ^ is a 0, b ^ is a 1, When ones occur in a sequence of type (b) or Cc], pairs of ones are encoded by a cell flank junction for the first (odd parity) 1 of the two 30s for the first (odd parity) 1 of these two ones is a ^ a 1 and b ^ is 0, while a ^ + ^ is 0 and b ^ + ^ is also 0, while for the second or even parity either of these two ones holds that 0, b ^ are 0 and b ^ are 0.

790 7 3 83 - 34 -

The normal state Cd-.i. ones are encoded as cell mid-transitions) is recognized by an AND gate 176 to which is applied the inverse of the Qg output signal a ^ (inverted by a reverse stage 178 into a ^) and the Dj output sig-5 sew as shown in fig. 7J. AND gate 176 therefore gives an output signal 1 when a ^ is 0 Cd.i. is a 1) and b. a 1 is. This signal is applied to an NOR gate

K

1SQ which produces output signal 0 in this situation.

A 1 which is odd 1 of a pair of ones encoded 10 according to the special Xerxes code, is recognized by OR gate 182 and an NOR gate 184. The Q ^ output signal b ^ + 1 and the Qg output signal a ^ are applied to the OR gate 182. This gate 182 only outputs 0 when both signals b,. and a are 0. This signal, together with the Qp output signal b ^ and the inverted O ^ output signal a. Is applied to the NOR gate 184. This gate 184 produces an output signal 1 only if b ^ + ^ and a ^ + ^ 0. b, is 0 and a is Q (dia 1 is 1. This corresponds to a cell flank transition in a bit cell followed by a bit cell in which there is no transition. This signal is also applied to the NOR gate 180 which in this situation output signal 0.

A 1 which is the second of a pair of ones encoded according to the special Xerxes code is recognized by a N0F-25 port 186 to which are applied GJ ^ output signal b ^, the Qg output signal a ^ and the O ^ output signal b ^ · The output of this port 186 is only 1 if all the signals a ^, b ^ and b ^ _1 are 0, which only occurs when the even 1 of a pair of ones is encoded according to the Xerxes -code. The output of the NOR gate 186 is also applied to the NOR gate 180, which produces a 0 in this situation.

The NOR gate 180 therefore produces an output signal 790 7 3 83 - 35 - O whenever one of the three situations denoting a 1 exists. Otherwise, the output is a 1. The output from the NOR gate 180 is applied to the D input of a D flip-flop 188 which is clocked by the 1F clock pulses 5F * 7HJ. Each clock pulse transports the output from the> NOF gate 180 to the Q output terminal of the D flip-flop '188, inverse appears at the Q output terminal. The Q output is therefore a 1 in those situations where the 0 output signal from NOR gate 180 indicates a 1 ia co-10. , while the Q output signal is otherwise 0. The Q output signal is applied to track 38 in the form of NHZ-L as shown in Fig. 7K,

This is briefly summarized in Table A below, in which X represents both a 1 and a 0,

Table A

bk-l ak bk ak + l bk + l Xk X 0 1 XX 1 through AND gate 176 X 11 0 0 0 1 through gates 182 and 184 20 0 1 0 1 0 0 0 10 0 10 0 0 0 XX 1 through NOR gate 186 1 0 0 XX 0 25 X 1 1 XX transmission error 1 11 XXX transmission error Q 0 0 0 0 transmission error X 0 0 00 synchronization error

The foregoing description of the circuit shown in FIG. 6 assumes that the clock 42 is in proper synchronism with the cell flank transition. However, since the clock 42 has a base frequency twice as large as the bit cell frequency, it is possible that in 79073 the clock is in phase with the cell center transitions instead of the cell flank transitions. In that case, the data as output to the output terminal 5 of the O-flip-flop 188 would be in the form shown in FIG. 7L. This absence of synchronization can be detected by a synchronization detector 190 which can detect certain impermissible output situations. In the Xerxes format, the longest allowable interval between transitions can occur at the end of a sequence of the type Cc] with the last three ones encoded by a cell flank-10 averaging the first of the three ones »for the second of the three ones no transitions exist, for the last of the three ones a cell middle transition exists. In the notation of Figure 6, this situation exists when both and b are ^ + ^ 1, and all the signals b ^. ^ A ^, b ^ and a ^ + 1 are 0. The situation is decoded by the NDF gate 186 when the D flip-flop 188 is clocked out by the IF clock pulse for an interval at which the signal appears at the Qg output terminal of the 5-bit shift register 174. When between if the IF clock pulse and the 2F clock pulse would not exist a proper phase relationship, the 20 D flip-flop 188 will be clocked out half a cycle too early. With the transitions given above, the output signals Q ^, Qg,

Qc and all half a cycle earlier than 0. For the decoder this will mean whether two consecutive bit cells would be present in each half without a transition. However, this is not a possible condition with the Xerxes format. The only situation where 2.5 T occurs between transitions, i.e. four half cells in a row have no transition, is that at the termination of a series of the type Cc3. In that case, only the middle 1 of the last three ones is encoded without a transition in each half. Thus, a situation where terminals Q1, Qg, Qg and Qg are all 0 at the time of clocking means an indication that the decoder is out of synchronism.

790 73 83 V * - 37 -

The synchronization detector 190 detects the absence of synchronisms by recognizing the occurrence of the situation where all terminals QA> Qg, GJC and Qq at the time. of the clock operation are 0. For this purpose, these terminals are connected to an NOR gate 192 which only produces an output signal ^ 1 when all the input signals are 0. The output of the NOR gate 192 is applied to the D input terminal of a D flip-flop 194 which is clocked by the 1F clock pulses (FIG. 7H). This converts an output 1 to 10. the: Q output terminal of the D flip-flop 194- triggered. the next clock pulse and when all the connections Q ^,

Qg, Dc and Qq are simultaneously 0 * The output signal can be used in a number of ways to activate an indicator or means by which the decoder is synchronized. The lF clock can be synchronized in several ways, such as by suppressing one at a time. JK flip-flop 160 designated 2F pulse in a manner similar to that applicable to the synchronization circuit of U.S. Patent 4,027,335. In order to ensure synchronisms 20, a special lead-in signal containing at least one sequence of the type Cc] may be transmitted, enabling synchronization detector 190 to detect absence of synchronisms and allow recovery upon initiation. This prevents data from being lost before the data bits themselves provide transitions that indicate that synchronization error exists.

It is noted that a signal indicating that synchronisms are absent will also be present at the output of synchronization detector 190 when signal loss exists on track 30. This situation can be distinguished from the situation where there is no synchronism, by analyzing the output signals from the 5-bit shift register 174. If there is a signal loss, 79073 83 A. * 1 - 38 - these output signals will simultaneously become 0 at the normal Xerxes encoding, on the other hand, can never be more than four half cells in a row without a transition, and therefore one of the output signals should be a 1 regardless of whether or not the decoder works synchronously as long as a signal is received in the Xerxes format.

At the beginning of the decoding operation, the various parts of the decoding device can be reset by a reset pulse I from an initial pulse source 196, the operation of which is similar to that of the similar circuit 54 of the coding device *

As noted above, the longest interval between transitions, under the regime of a Xerxes format, occurs at the end of a sequence of the type Cc] yet 15 this may be a sequence under the regime of the standard

Miller code without introducing a DC component may be encoded. Since the long intervals without transitions require a larger bandwidth, the bandwidth requirements are reduced when the standard Miller format is used to encode series of the type Cc]. However, there is a drawback here that series of types Cb) and Cc] cannot be distinguished at the beginning. Only upon termination of the sequence can it be determined whether the number of ones is odd 25 or even. In order to series of the type Cc] in the standard

To encode Miller format it is therefore necessary to look ahead to the end of the sequence. Since a series can have a particularly large length, this is impractical since then. ' an almost infinitely long "look ahead" must exist. Accordingly, in one embodiment of the present invention, provision has been made to limit such a look-ahead capability, requiring that an acceptable number of bits be looked forward when encoding strings that can be identified as the type Cc] 790 7383 h / - 39 - in the standard Miller format. Since the end of the sequence cannot be seen, the sequence is coded under the regime of the Xerxes rules discussed above. Figures 8 and 9 show an encoder with a 5-bit look-ahead capacity. The forward looking circuit arrangement and parity counters are shown in FIG. 8. The cadence chain is shown in Figure 9. Corresponding wave vests are shown in Figure 10. The 10 in. 8 and 9 circled letters drawn with the corresponding waveforms shown in fig. 10.

The in fig. 8. the forward circuit shown receives the same input signals as the encoder 22 shown in Fig. 4, namely the 01 clock pulses (Fig. 10A) on the track 24. The input 15 data in the form NRZ-L on the track 12. Fig. 10C] , and the reset pulses on the track 52. The other encoder inputs. 22 are applied to the circuit arrangement shown in FIG. 9, namely the 02 clock pulses on the track 20 and the 2F clock pulses (FIG. 10D) on the. lane 25 .. The 01 clock pulses and the reset pulses T are also applied to the circuit arrangement shown in FIG.

In the circuit arrangement shown in FIG. 8, the input data (FIG. 10OC) are applied in series form to the A and B input terminals of an 8-bit shift register 196 (serial form input / parallel form output.) Which is preferably of a commercially available version is (TI 74164) connected as shown. The 8-bit shift register 196 introduces a 7-bit delay in order to be able to look ahead with respect to the output data from the shift register. More specifically, if the output data is given to the Q ^ output terminal (Fig. 10E) as the signal to be encoded at that time, the signal to the Q ^ output terminal is given as Χ ^ + · ^> Etc. up to the D ^ output 790 7 3 83 - 40 connection through which the Z. bits of the signal became available after * X ^, namely X ^. If a string were present which could be determined to be of the Co1 type at the time the first 1 of the string reaches the Qg output, the entire string is encoded according to the standard Miller code. With the circuit arrangement shown in FIG. 8, such a determination is possible in which a flag signal G is introduced in order to modify the Xerxes frame Cfig * 9] for a series recognized as a series Cc].

The introduction of the flag signal G starts with the signal Cfig.lQD). The signal X ^ + 7 is applied to the K input terminal of a JK flip-flop 198, the signal X, i.e., the inverted version thereof obtained by an inverter 200, is applied to the J input terminal. The JK flip-flop is therefore operative to count zeros from the beginning of a coding and on a 7-bit time response before the signal X ^ is available at the coding terminal. When driven by the 01 clock pulses, the Jk flip-flop 198 is operative to give the Q output terminal a parity of zeros Cfig.lOFJ. The GJ output of the JK flip-flop 198 is applied to the D terminal of a D flip-flop 202 driven by the 01 clock pulses. The Q outputs of the JK flip-flop 198 and the D flip-flop 202 are applied to a NAND gate 204 which produces a 1 at its output (Fig. 10H] each time the parity of zeros at the connection is 0, ie when an even number of zeros has been present since the beginning.

Such an 1 indicative output signal is applied to terminal CLR of a counter 206 which may be of a commercially available embodiment CU 74161] and connected as shown with a count of ones Cfig at the output terminal. 101], at the output terminal Qg a count of two (Fig. 10J) and at the output 790 73 83 -41 terminal Qc a count of four (Fig. 1 OK) is obtained. When a 1 is applied to the preparation terminal EN of this counter (FIG. 10G), this counter 206 operates every 01 clock pulses applied to the terminal CLK there-5. to count. The preparation signal is triggered. through an AND gate 208 when all three input signals applied thereto are 1, in other words, when C1) X ^ + 7 (Fig. IOD) at the output terminal of the shift register 196 is 1, whereby a 1 in a series 1, the zero-10 parity theorem (Fig. 10OF) is indicated at one of the output terminals O of the. JK flip-flop 196. 1, indicating that the sequence of ones started with an O and is therefore of the type (b) or of the type Cc); and (3) the output of a NAND gate 210 is 1, indicating that the counter 206 has not reached a count of 6. A count of 6 would make the outputs Qg and the counter 206 both 1 so that the two inputs of the NAND gate 210 would be 1. As a result, counter 206 is operative to count the 01 clock pulses (up to a maximum value of 6) whenever a sequence of ones exists with 0 at odd parity, ie counts-20 when the ones are part of a series of type Cb) or of type (c). If the counter 206 does not reach a count of 6 before a 0 is reached in the data stream, the counting operation of this counter will be stopped when the first 0 25 appears at the output terminal of the shift register 196 (Fig. IOD), since this causes a 0 is applied to the input of the preparatory AND gate 208, whereby its output (FIG. 10G) becomes 0 and the counter 206 is turned off. The JK flip-flop 198 acting as parity counter also produces a 0 at the Q output terminal (FIG. 10F), indicating an even number of zeros, applying a 0 to AND gate 208 so that the counter is disabled remains when subsequent ones appear in the input data. Due to the even parity, the counter is also reset by means of 790 7 3 83 - 42 - of the D-flip-flop 202 and the NEN-part 204 (Fig. 10H), as already described above. At a count of 6 by the counter 20S, the cell operation is also stopped by producing an output signal 0 from the NAND gate 210 which is applied to the preparatory AND gate 208. The AND gate 212 determines whether a flag signal G may or may not be produced. The signals from the one indicating output Qa Cfig. 1011 of the counter 206 and the inverted signal from the inverter 200 (FIG. 1QD inverted) are applied to the AND gate 212. The one containing output signal is at the end of a sequence of ones is only 1 if the number of ones in the sequence is odd and less than 6. If the count is even and less than 6, a 0 is obtained at this output. number of ones in the sequence sc. 6 or more than 6, the counter stops at 6, thus keeping the ones output 0. The AND gate 212 will therefore only produce a 1 only when the counting of ones as performed by the counter 206, 1, 3 or 5 is at the time when the following 0 appears at the terminal 0A Cfig.lODJ 20 of the shift register 196. This output Cfig.10U is 1 whenever the flag signal G is to be produced.

The output of AND gate 212 is applied to the preparation terminal EN of a demultiplexer circuit 214, which may be of a conventionally available embodiment. TI

74S138] and connected as shown. When this circuit 214 is prepared by a 1 from AND gate 212, this demultiplex circuit 214 operates to transfer the count value applied at its input from counter 206 to a six 30 lines. containing output, wherein a 0 is produced on the line corresponding to the final count value. The other output lines are at 1. With a count of 1 the 0 appears on the output bj, for a count of 3 the 0 appears on the output 790 7 3 83 Τ '' * - 43 - d d Cfig.lOM) ; and for a counting of the variable 0 on the output (Fig. lON). There cannot be even counts since the AND gate 212- prepares the demultiplex chain only at count values of 1, 3 or 5, as previously indicated 5 * ^ The outputs of the demultiplex chain 214 are applied to the appropriate AND -Ports 216, 218, 220, 222, 224 and 226 * The output signals of these AND-gates are applied to the input terminals of parallel access sliding callers 1CL 228 and 230 of a commercially available version, eg TI74195 and Dia are connected as shown - When applying each of the 01 clock pulses (Fig. 10A), the 0 as applied from the demultiplex chain is shifted through the shift register until it is output as an output at terminal Qc 15 of the register 230 appears. This output 0 is coupled to the input of a latch circuit 232 which may be a commonly available flip-flop, such as "e.g. TI 7476.

When a 0 is applied to the input terminal of the latch circuit 232, the Q output terminal 20 thereof produces the flag signal G (FIG. 10Q) at the moment when the first 1 of the sequence reaches the output terminal 0H of the shift register 196. The inverse thereof G is triggered at the Q output terminal of this latch circuit 232. The flag signal G then continues to exist until the end of the sequence, this signal being reset by the Q output signal P (0 ') Cfig.lOP] of an Ö parity detector 234 which may be a commonly available JK flip-flop, e.g.

TI 74109. The zero parity detector 234 operates in a similar manner to the parity detector of the JK flip-flop 198 to determine whether the number of zeros counted from the beginning of the coding is odd or even, ie, or a series of the type Cb] or of the type CcO is about to start or is about to end. When at the end of a sequence 790 7 3 83 - 44'- of the type (b) or of the type Cc) ends with a 0 appearing at the output terminal of the shift register 196 (Fig. 10E), X. is a 0 This signal is converted to a 1 by a reversal circuit 236 to form the signal. In this situation, the zero parity detector 234 is operative to count a 0 for every 01 clock pulse. When the count is even, PCQ) is a 0. When this takes place at the conclusion of a sequence of ones at the output, the latch 23Z is released, resulting from the special situation where, according to the re-10 regular Miller code, strings of the type Cc) with a number of ones smaller than 6 are encoded, the encoding is returned with the regular Xerxes code. Except for releasing the latch circuit 232, the zero parity signal PCO) (FIG. 10P) and its inverse PCQ), as triggered at 15. Q output terminal of the zero parity detector 234 used in coding performed by the circuit arrangement of FIG.

A 1 parity detector 238 which may also be a commonly available JK flip-flop, e.g. TI 74109, similarly operates as the parity detector of the JK flip-flop 66 to provide a 1-parity signal PCI) Cfig at the Q output terminal. 10R) and its inverse PCI) to produce the Q output signal. This inverse PCD is used in the encoding as performed by the circuit arrangement of Figure 9. A reverse circuit 240 is used to invert the signal to obtain the inverse used in the encoding as performed by the circuit arrangement of FIG. 9.

The encoder shown in FIG. 9 processes the signals developed by the circuit arrangement of FIG. 8 substantially in the same manner as the encoder of FIG. 4. In the circuit arrangement of FIG. 9, the preparative AND gates 242 and 244 are prepared by the respective 01 and 02 clock pulses at the respective mutually exclusive a and b portions of 790 7 3 83 • ï ¥ - 45 - of a bit cell, to be pushed together

a. and b signals applied to KK via an OR gate 246

the D input of a D flip-flop 248 where these signals are clocked out in sequence, by 2F clock pulses (Fig. 1GB), so that the output signal at the Q terminal of the D flip-flop 248 lags by half a bit distance at the input signal "at the time of clock operation. The Q output signal is at the time at which aR is encoded, therefore bR_ ^.

As is the case with the encoding circuit of Figure 4,: 10 - ones are normally encoded according to the standard Miller code by a cell center junction, ie bR is a 1. Normal encoding is performed by the AND gate 244 which is a 1 when this gate is prepared by a 02 clock pulse and XR is a 1, provided that a third input is also present at the third input- The third input signal is received from an OR gate 250. This gate has two inputs of which one is connected to ”one. OR gate 252 and the other is connected to an AND gate 254. The OR gate 252, in response to F C0] or G, gives a 1 which prepares gate 244 through OR gate 250.

When P (0) is 1, the sequence of ones is of the type Ca) to be encoded according to the normal Miller format. When G is 1, the sequence of ones is of the type Cc); however, since the string is less than 6, it must be encoded according to the standard Miller code. The only other situation in which a 1 must be encoded by a cell center junction exists when this 1 is the last of a series of ones of the type Cc). This can be detected by AND gate 254. This happens when t1) PCO) is 1, indicating that the sequence is of type tb) or of type Cc), · C2) PCI) a 1 30 , indicating that an odd 1 is encoded, · and (3) is XR + ^ 1, indicating that the next bit is 0.

As is the case with the encoder of FIG. 4, zeros are normally encoded according to the standard Miller 790 7 3 83 - 48 code through a cell flank transition, ie a ^ is a lv. Normal encoding is performed through the AND gate 242. which generates a 1 when it is prepared by a 01 clock pulse and the output of a QF gate 256 is 1. OR gate 256 5 produces such an output signal 1 when the output signal of an NOR gate 258 is 1. The input signals of the NOR gate 258 are the bit signal and the Q output signal of the D-flip-flop 248, which is the Q output signal at the time of encoding a ^, b ^ _ ^. The output of the NOR gate IQ 258 therefore operates through the OR gate 256 to encode the AND gate 242 to achieve that a cell edge transition a ^ encodes a 0 when a is 0 except when it is 0. follows a cell center junction encoding the immediately preceding 1.

15 According to the Xerxes format, a cell flank transition is also effected at the onset of odd parity of ones from pairs of ones of one-member series of the type Cb) or of the type Cc], except for the situation where the look-ahead capacity is not exceeded and at the beginning it can be determined that the series is of the type Cc]. This encoding is performed by the AND gates 260 and 262. The AND gate 260 is prepared by the signal P11 which is 1 when the 1 being encoded is the odd 1 of a pair. AND gate 262 only produces a 1 at the output when C1] is PCO] 1, indicating that it is a series of type Cb] or of type Cc], * C2] X ^ and C3] X ^ both are 1, indicating that the pair of consecutive ones exists and C4] G is 1, indicating that it is not a series of the type Cc] within the look-ahead capacity. Under these conditions, the output 1 of AND gate 262 therefore produces an output 1 of AND gate 260 for the odd ones. This acts through the AND gate 260, the OR gate 256 and the AND gate 242 to cause a ^ 1 to result in a cell flank transition.

790 7 3 83 - 47 -

The transitions in the output signal are "caused by a JK flip-flop 264 which may be of a commercially available embodiment b * v · TI 74109. The transitions appear with every 2F clock pulse and when the GJ output signal of the D -flip-5 flop 248 is 1 obtaining an output signal of the form shown in Fig. IOS. Fig. 10T illustrates how this same signal would be encoded according to the * Xerxes format if the · look ahead capacity is only 1. .

This is the case with the encoder of FIG. 4, and it will be the case if the latch circuit 232 of the chain device. according to fig.8, would have been disabled with GO [suppressed.] .. It should be noted that when the look ahead capacity is exceeded Cfig.lOT] between transitions an interval 2.5T occurs * while the transitions otherwise Cfig.lOS) more than over 15 2 T stand apart from each other * which- illuminates the bandwidth requirements,

As is the case with the encoder of FIG. 4, the various flip-flops and shift registers of the circuit devices of FIGS. 8 and 9 can be released at the beginning of the coding operation by a reset pulse T.

Although two specific encoding chains have been described in the foregoing and a specific decoding chain, operating on: the same code, has been discussed * it will be understood that other chaining arrangements may be used for the same purposes. Furthermore, other code formats can be used within the scope of the present invention. Regarding zero parity, it makes little difference whether the controlling parity is even or odd, an imbalance cannot expand as long as a predetermined parity state is used for checking. the coding in order to distinguish between series of the type Ca] and series of the type Cb) and the type Cc] on the other hand. If an odd parity would use an odd parity instead of 79073 83 - 48 - "* · to identify the series of type Cb] and type Cc], other series would be identified and coded using the special Xerxes regime, but the same decoding scheme will provide accurate decoding to obtain the original data * p. Briefly summarized, the invention is directed to a system and a method which considers binary data stream in series form as a combination of multiple types of strings, some of which can cause a similar current imbalance if the code format of U.S. Pat. No. 3 * 103,261 were used. According to the invention, at the beginning of any sequence of ones, such sequence is indicated is not of the kind that could introduce DC balance In dependence on such an indication, at the beginning v took the appropriate series of rebuild actions to eliminate any DC component. Preferably, this is accomplished by encoding arrays of type Cb] or of type Cc) by creating a single cell flank junction for the first of each pair of ones while no transition exists for the second 1. In one embodiment of the invention, looking ahead over a limited number of states can determine at the outset whether or not a particular series of ones ends within that limit and is of the type that will not introduce a DC component into the transmission signal under applying the normal Miller code, in which case the entire string is normally encoded.

790 73 83

Claims (5)

Transmission system with internal time signaling and arranged for sequentially transferring binary data bits in successive clocked bit cells of a transmission channel, wherein logic first bit states are normally transmitted as signal-over-gates occurring relatively early in the respective bit cells * and logic second bit states are normally transmitted as signal transitions that occur relatively late in the respective bit cells, each one relatively early in one. bit cell occurring transition following an in. the immediately preceding bit-cell and relatively late-occurring transition is normally suppressed, comprising equipment for modifying the transmitted signal such that. any net direct current component is eliminated, characterized in that said equipment comprises first indicating means which, in response to first bit states, count the number of these first bit states, as well as at the beginning of a sequence from second bit states following a first bit state, produce a first clue signal when the number corresponds to a predetermined parity ter. designation of such a sequence which could introduce a DC component into the transmitted signal in normal transmission; transition changing means, in response to said first pointer signal, a running bit of such a sequence, and an adjacent bit, changing the transmission of signal transitions from the beginning of such a sequence so as to eliminate any DC component; limited capacity pre-viewing means which, in response to said first pointing signal, a running bit and a limited number of immediately following bits, produce a blocking signal at the beginning of each such a sequence that is within said limited number of immediately following bits and which would not introduce a DC component in normal transmission; and means responsive to said blocking signal disabling said transition change means for the transmission 790 7 3 83 - 50 - I A of signal transitions corresponding to all the second bit states of. such a series that will not introduce a DC component in normal transmission. 2. Apparatus according to claim 1, characterized in that said transition change means is adapted to change the transmission of signal transitions such that a single transition corresponds to each. pair of second bit states of such a sequence, the first of the pair having an odd second bit. is the state, and which single transition is relatively early in the respective bit cell for the first of the pair. is transferred 3. System according to claim 1, characterized in that said equipment further comprises second indication means which produce a second indication signal in response to bit states. indicating whether the number of second bit states occurring in one. such series appear, prior to a running bit, odd or even, said transition change means in response to said first and second pointer signals, as well as to the running bit and a neighboring bit, the transmission of signal transitions from the beginning of a modify such array so that any DC current component is eliminated. 4. Apparatus according to claim 3, characterized in that said transition modifying means changes the transmission of signal transitions such that a single transition corresponding to each pair of second bit states of such sequence is formed when the first of the pair has an odd second bit state which single transition is transferred relatively early in the respective bit cell for the first of the pair. 5. Apparatus according to any one of the preceding claims 1 to 4, characterized by decoders, which, in response to transmitted signal transitions, indicate the bit states of the transmitted binary data, of which decoders are part synchronizing means, which respond to transmitted signal transitions, time signals, which identify bit cell intervals; detecting means, in response to said transmitted signal transitions and said time signals, generating transition identifying signals 7907383-51 which identify received signal transitions as occurring relatively early or relatively late in the respective bit cells; and bit state recognition means, which may indicate in response to the transition identifying signals for a bit cell whether it is in the second bit state under any of the following situations. (a) a relatively late transition for the cell in question, (b) a relatively early transition for the cell in question, while for. the immediately following cell does not have a transition, and <c> no transition, for the oops in question, while for the immediately preceding cell there was no relatively late transition, as well as for all the other cells, which may indicate that they are in the first bite condition *. '790 7 3 83