JPH06125340A - Frame synchronization circuit for multi-frame data communication - Google Patents

Abstract

PURPOSE:To prevent circuit and device from being large in size and cost from being high by using RAMs of a few number to form the circuit even when it is required to store bit data by plural frames. CONSTITUTION:A RAM 1 stores data by one multi-frame, and a frame counter 2 counts bit number by one frame to generate a low-order address with respect to the RAM 1. A high-order address control circuit 9 selectively outputs a high-order address of the RAM 1 in response to a selection signal. A register 4 stores individually data read from the RAM 1 by a selection signal and sets synchronization pattern data by plural frames to a shift register 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit for frame synchronization in data communication having a multi-frame structure.

[0002]

2. Description of the Related Art FIG. 14 and FIG. 15 show a general structure of a multi-frame in which data communication is performed by the multi-frame method and an example of the data. As shown in FIG. 14, each frame is provided with a control field such as a synchronization pattern, and a plurality of frames are treated as one unit. The number M of bits per frame, the number m of synchronization pattern bits in one frame, and the number N of multiframes are all arbitrarily determined, and the position of the synchronization pattern in the frame is also arbitrarily determined. Furthermore, the number of synchronization protection stages (when the number of multi-frames is one unit, how many units of the multi-frame synchronization patterns are to be compared, the number of stages) L is also arbitrary. Here, the number of bits per frame M = 12
When it is set to 3, the frames shown in FIG. 14 are sequentially and continuously transmitted as shown in FIG. In FIG. 15, F _1-1 is the first bit of the first frame, F _1-2 is the second bit thereof, F _1-123 is the 123rd bit of the first frame, or F _2-1 is the first bit of the second frame. Bit, F _2-2
Indicates the second bit of the second frame, and F _2-123 indicates the 123 bit of the second frame.

Conventionally, a circuit applying a RAM to a shift register has been known as a frame synchronization circuit in a communication device of a multi-frame system. The structure is shown in FIG. 16 as a block diagram.

In FIG. 16, the RAM 1 stores all multi-frame data, and the frame counter 2 counts the number of bits of one frame to generate an address signal for the RAM 1. The buffer 3 is composed of a three-state buffer circuit and outputs write data to the RAM 1. The register 4 latches the data read from the RAM 1. The shift register 5 inputs the frame data for comparing the synchronization patterns. The synchronization pattern comparison / protection circuit 6 compares the data from the shift register 5 with the synchronization pattern for the number of protection stages to protect the synchronization detection. The synchronization counter 7 counts the frames and multi-frames synchronized with the synchronization pattern by the synchronization detection signal from the synchronization pattern comparison protection circuit 6. The control circuit 8 is RAM1
And a control signal for the register 4 are generated.

FIG. 17 is a specific circuit diagram of the frame synchronization circuit, FIG. 18 is a timing chart of each part thereof, and FIGS.
FIG. 25 is a diagram showing an example of changes in the contents of the RAM 1, the register 4, and the shift register 5 in each step.

In FIG. 17, the frame counter 2 counts the clock signal CLK and outputs an address signal to the RAMs 1a and 1b. Input data Din is buffer 3
A signal D0 by the control signal D-OT through a
And written to the I / O 0th bit of RAM. Since data is input continuously, RAM1
It is always written to the I / O0th bit of the address whose count is incremented a and 1b. Register 4 is a control signal CT
The data read from the RAM is latched by. The input data Din and the output of the register 4 are input to the corresponding shift register 5. Further, the output of the register 4 enters the buffer 3b, and according to the control signal D-OT, D1 to D10
Is written in the RAMs 1a and 1b. In this example, there are twelve shift registers 5 each having a 3-bit configuration, and the input data Din and the outputs DL0 to DL10 of the register 4 are provided.
Are sequentially shifted in synchronization with the clock signal CLK. Each bit data of each shift register 5 enters the sync pattern comparison circuit 6-1 and is compared with the sync pattern. The comparison result enters the protection circuit 6-2, performs a general set / reset type protection operation, and outputs a synchronization detection signal. The synchronization counter 7 sets the synchronization count value of the frame and the multi-frame according to the synchronization detection signal.

The operation of each part in FIG. 17 is shown in FIGS.
As shown in FIG. 25, if the value of the address counter is 1, the RAM data at address 1 is read and set in the register 4. Subsequently, the RAM address does not change, and the value of the register 4 and the input data (for example, the first bit F _1-1 of the first frame) are written in the RAM. Specifically, the input frame data F _1-1 is at the 0th bit of the RAM, and the 0th bit (LSB) of the register 4 is at the 1st bit of the RAM.
The 1st bit of the register 4 is written with being shifted by 1 bit such that the 1st bit of the register 4 is the 2nd bit of the RAM. After that, each value in the register 4 is loaded into the corresponding shift register 5. After that, the frame counter 2 is counted up and the RAM address becomes 2. The above operation is repeated, the frame counter 2 counts 123, and the output of the counter returns to 1. At this time, the 0th bit of the data read from the RAM is F _1-1 one frame before.
become. Also, the first bit F _2-1 of the second frame is RA
It is written in the 0th bit of M. By repeating the above process, the synchronous bit data for 3 consecutive bits for 12 frames is accumulated in the shift register 5, and the synchronous pattern comparison circuit 6
-1 compares with a predetermined sync pattern at the timing when the frame sync pattern is prepared in the shift register 5.

[0008]

In the frame synchronizing circuit in which the RAM is applied to the shift register as described above,
As is apparent from the configuration shown in FIG. 17, the RAMs 1a, 1
The number of data bits of b is determined by the frame data structure. In the case of the conventional example shown in FIG.
= 4 and the number of protection stages L = 3, the number of data bits in the RAM was N × L-1 = 11. But general R
The data width of the AM device is in units of 1/4/8 bits. When 11 bits are required as in the conventional example shown in FIG. 17, it is necessary to provide two RAMs having a data width of 8 bits, for example. . As described above, using a plurality of RAMs has been a cause of increasing the size of the circuit and the device and increasing the cost.

An object of the present invention is to provide a data width of 8 even if the number of data bits required for the RAM, which is determined by the frame data structure, exceeds 8 bits, for example.
There is no need to install multiple bit RAMs and a single R
An object of the present invention is to solve the above-mentioned problem by making it possible to configure a frame synchronization circuit using AM.

[0010]

A frame synchronization circuit in multi-frame data communication according to the present invention counts the number of bits for one frame by inputting a RAM for storing at least one multi-frame data and a clock signal. A frame counter for generating an address signal for the RAM, an upper address signal control circuit for switching and outputting one or more upper bits of the address for the RAM according to a selection signal, and the data read from the RAM for the selection signal A plurality of registers which are temporarily stored individually according to the switching by, and each of which has a number of bits corresponding to the number of synchronization pattern bits in one frame, at least as many as the number of multi-frames, in synchronization with the clock signal, The contents of the register and A shift register for storing the newly entered data, composed of a sync pattern comparing circuit for comparing the contents of the shift register to the synchronization pattern.

[0011]

In the frame synchronization circuit for multi-frame data communication of the present invention, the RAM stores at least one multi-frame data, the frame counter inputs the clock signal to count the number of bits for one frame, and the Generate an address signal. The high-order address signal control circuit switches and outputs the high-order 1 bit or a plurality of bits of the address to the RAM according to the selection signal. Each register temporarily stores the data read from the RAM individually according to the switching by the selection signal. Each of the shift registers has a number of bits corresponding to the number of synchronization pattern bits in one frame, is provided with at least the number of multi-frames, shifts the stored contents in synchronization with the clock signal, and the contents of the registers and new registers. The data input to is sequentially stored. Then, the sync pattern comparison circuit compares the predetermined sync pattern with the contents of the shift register.

As described above, by providing a plurality of registers for switching the upper 1 bit or a plurality of bits of the address to the RAM and temporarily storing the data read from the RAM individually according to the switching of the upper bits. , A single R with a data width of 8 bits
Using AM, (the number of multiframes N × the number of protection stages L−
Even if the value of 1) exceeds 8, it becomes possible to deal with it.

[0013]

FIG. 1 is a block diagram showing the structure of a frame synchronization circuit in multi-frame data communication which is an embodiment of the present invention. In FIG. 1, the RAM 1 stores all multi-frame data, and the frame counter 2 receives the clock signal 102 and counts the number of bits of one frame to generate the address signal 104 for the RAM 1.
The buffer 3 is composed of a three-state buffer circuit, receives input data 101, and writes data 1 to the RAM 1.
06 is output. The register 4 latches the data 103 read from the RAM 1. The shift register 5 inputs the frame data for comparing the synchronization patterns. The synchronization pattern comparison / protection circuit 6 compares the data 107 from the shift register 5 with the synchronization pattern by the number of protection stages to protect the synchronization detection. The synchronization counter 7 counts the frames and multi-frames synchronized with the synchronization pattern according to the synchronization detection signal 108 from the synchronization pattern comparison protection circuit 6. The upper address control circuit 9 is composed of a counter for outputting the MSB 105 of the address signal to the RAM 1 and a circuit for inverting its logic level by a signal from the outside. The control circuit 8 generates various control signals 109 such as a control signal for the RAM 1, a control signal for the register 4 and a control signal for the upper address control circuit 9.

Next, FIG. 2 shows a concrete circuit configuration, FIG. 3 shows a timing chart of each part thereof, and FIG. 4 shows changes in the contents of the RAM 1, the registers 4a and 4b and the shift register 5 shown in FIG. ~ Shown in FIG.

In FIG. 2, the input data Din is input in synchronization with the clock signal CLK.

In this embodiment, since the number of bits per frame M = 123, the frame counter 2 is set to 1
The carry signal RC is output every 23 counts, the T-type flip-flop 9-1 divides the carry signal by two, and E
The X-OR circuit 9-2 inverts the output of the T-type flip-flop 9-1 in accordance with the control signal (selection signal) SEL and RA
It is given to the most significant bit MSB (A7) of the address of M1. The registers 4a and 4b have control signals A-C and B-, respectively.
The read data from the RAM 1 is latched by C. Input data Din and outputs D of registers 4a and 4b
L0 to DL10 and DL1 to DL9 are input to the corresponding shift registers of the shift register 5. The output of the register 4a enters the buffer 3b and is written in the RAM 1 through D1 to D5 according to the control signal D-OT. In this embodiment, the number of protection stages L = 3 and the number of multiframes N = 4.
Therefore, in the state where the data of the synchronization pattern for L × N = 12 frames is set in the shift register (when the value of the synchronization counter 7 becomes 123), the synchronization pattern comparison circuit 6-shown in FIG. 1 determines whether or not a predetermined synchronization pattern and each bit of the shift register 5 match.

The protection circuit 6-2 is a synchronization pattern comparison circuit 6
When the result of the comparison by -1 indicates a mismatch for several frames in a row, the clock signal to the synchronous counter 7 is prohibited once to shift the value of the synchronous counter 7 by one bit and start the synchronous detection again. . Further, after synchronizing once, the protection circuit 6-2 operates as a synchronization pattern comparison circuit 6-
The counting operation of the synchronous counter 7 is not shifted until the comparison result of 1 is disagreement for several frames continuously.

In FIG. 3, when the value of the frame counter 2 shown in FIG. 2 is 1 and the selection signal SEL is at "L" level, the address A7 input of the RAM1 becomes "H" level, so that the RAM address. Becomes (81) H. In this state, when the control signal BC for the register 4b rises, the read data of the RAM is latched in the register 4b. After that, the selection signal SEL goes to "H" level, the address A7 of the RAM goes to "L" level, the RAM data of the address (01) H is read out, and the control signal AC for the register 4a is read. At the rising edge, the data is latched in 4a. After that, the control signal D
The -OT becomes "H" level, the input data Din and the contents of the register 4a are output to D0 to D5, and are written in the address (01) H of the RAM1 at the rising edge of the write enable signal WE. After that, the frame counter 2 is counted up, and the selection signal SEL becomes “L” level, so that the RAM of the address (82) H is
Data is read and the contents of the registers 4a and 4b are input to the shift register 5 at the rising edge of the clock signal CLK. After that, the selection signal SEL becomes the “H” level, the RAM data of the address (02) H is read, and this is latched in the register 4a. The same processing is repeated thereafter.

As shown in FIG. 4, in step 1, the output of the address counter is 1, and the RAM address MSB (A
When 7) is set to 1, the RAM data at the address (81) H is read out and set in the register 4b. In step 2, the value of the address counter is the same, the MSB of the RAM address becomes 0, and the RA of the address (01) H
The M data is read and set in the register 4a.
The input frame data F _1-1 in bit 0 of the RAM, bit 0 of the register 4a (LSB) in the first bit of the RAM, the first bit of the register 4a say ... the second bit of RAM Thus, the data is written with a shift of 1 bit.
In step 4, each value in registers 4a and 4b is loaded into the corresponding shift register. (In the figure, only a part of the shift register is shown.) As shown in FIG. 5, in step 5, the address counter is counted up, the output becomes 2, and the MSB of the RAM address becomes 1 again. Otherwise, the same operation as steps 1 to 4 is repeated. As shown in FIG. 7, the address counter becomes 123 at the (4 × 123) −third step, and (4 × 1)
23) At the 23rd step, the shift register 5 is set with the data F _1-121 , F _1-122 , and F _1-123 of the synchronization pattern of the 121st to 123rd bits of the first frame. As shown in FIG. 8, at the (4 × 123) +1 step, the address counter returns to 1, and (4 × 123) +
First frame data F of the second frame in the third step
_2-1 is written in the 0th bit of RAM. After this, the same operations as steps 1 to 4 are repeated. As shown in FIG. 10, at the (4 × 123) × 2 step, the shift register stores data F _2-121 , F _2-122 , and F _2-123 of the synchronization patterns of the 121st to 123rd bits of the second frame. Will be set. After that, similarly, as shown in FIG. 13, at the (4 × 123) × 4th step, the shift register has data F _1-121 to F of synchronization patterns for four frames.
_1-123, it becomes _{F 2-121 ~F 2- 123, F 3-121} ~F 3-123 and F _4-121 data to F _4-123 align it.

In the embodiment, the number of multiframes N =
4, using a RAM having a protection stage number L = 3 and a data width of 8 bits, a frame counter that counts the number of bits of one frame, and a T-type flip-flop 9 that divides a carry signal from the frame counter by 2 Although the example using 1 is shown, a binary counter for a plurality of bits for counting the carry signal of the address counter is used, and RA
By switching the higher-order bits of M, it is possible to deal with a case where data communication of a larger number of multi-frames is performed using a single RAM.

[0021]

According to the present invention, when the synchronization detection is performed by comparing the synchronization pattern data for a number of consecutive frames with a predetermined synchronization pattern, a RAM having a small number of multi-frames is used, but a RAM having a small number is used. 1
Data for multiple frames can be stored, and it is possible to cope with the circuit and the device without increasing the size and without increasing the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a frame synchronization circuit in multi-frame data communication which is an embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit configuration example of the same circuit.

FIG. 3 is a diagram showing a timing relationship of each unit in FIG. 2;

FIG. 4 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 5 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 6 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 7 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 8 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 9 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 10 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 11 is a diagram showing a state change of each part in FIG. 2 for each step.

FIG. 12 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 13 is a diagram showing a state change of each part of FIG. 2 step by step.

FIG. 14 is a diagram showing a structure of a multi-frame.

FIG. 15 is a diagram showing an example of a multi-frame data string.

FIG. 16 is a block diagram showing a configuration of a conventional frame synchronization circuit.

FIG. 17 is a diagram showing a specific circuit example of a conventional frame synchronization circuit.

FIG. 18 is a diagram showing a timing relationship of each part in FIG. 17;

FIG. 19 is a diagram showing a state change of each part in FIG. 17 for each step.

FIG. 20 is a diagram showing a state change of each part of FIG. 17 for each step.

FIG. 21 is a diagram showing a state change of each part in FIG. 17 for each step.

FIG. 22 is a diagram showing a state change of each part in FIG. 17 for each step.

FIG. 23 is a diagram showing a state change of each part in FIG. 17 for each step.

FIG. 24 is a diagram showing a state change of each part in FIG. 17 for each step.

FIG. 25 is a diagram showing a state change of each part in FIG. 17 for each step.

[Explanation of symbols]

 3a, 3b-buffer 4a, 4b-register 9-1 -T type flip-flop 9-2- -EX-OR circuit

Claims (1)

[Claims] 1. A RAM for storing at least one multi-frame data, a frame counter for inputting a clock signal to count the number of bits for one frame, and generating an address signal for the RAM, and an address for the RAM. A high-order address signal control circuit that switches and outputs the high-order 1 bit or a plurality of bits by a selection signal; and a plurality of registers that individually temporarily store the data read from the RAM in response to the switching by the selection signal. The number of bits corresponding to the number of synchronization pattern bits in one frame is at least as many as the number of multi-frames, the storage content is shifted in synchronization with the clock signal, and the content of the register and newly input data are also provided. And a shift register for storing the contents of the shift register Frame synchronization circuit in the multi-frame data communications composed of a sync pattern comparing circuit for comparing the sync pattern.