SU1448413A1 - Device for encoding cyclic codes - Google Patents

Abstract

The invention relates to telecommunications technology and can be used to transmit data subject to interference. The aim of the invention is to increase the speed of the device. The device contains elements 1.1-1.d of memory, where g is the degree of the forming polynomial, the first logical blocks 2.1-2 (d-1), the second logical block 3, trigger 4, the element NOT 5, the elements OR 6 and 7, the key element 8. 2 z. P. f-ly, Z il.

Description

4 4

The invention relates to telecommunications and can be used to transmit data subject to interference.

The aim of the invention is to improve the speed of the device.

Figure 1 shows the structural electrical circuit of the device proposed; FIG. 2 is a diagram of a logic unit of the first type; fig.Z - the same, the second type.

The device (Fig. 1) contains elements 1.1-1.d of memory, the first logical blocks 2.1-2 (d-1), the second logical block 3, trigger 4, the elements NOT 5, the elements OR 6 and 7, the key element 8, made on the element OR 9, the elements AND 1D.1, 10.2. Each of the first logical blocks (figure 2), contains elements 11-14. The second logical block (fig.Z), contains elements AND 15-24, elements OR 25 and 26.

The device works as follows

at once.

To encode cyclic codes with generating polynomials of the form X + X 1, the first logical blocks implement the excitation functions

- VR; XiX, 4i (or,);

Vs; X, X; ,, (U, V and).

the second logic block implements the excitation functions

Vft (xD,) and, v (x, x.; Vx, xi) 35

(UiU VUiUi) XKi

Vsr C (XiXiVX, X2) U V (X, XDR, (2)

where v | ;. and Vg. - excitation functions, 40, respectively, of the R and S inputs of the i-th memory element;

X., X. - respectively, the state of the direct and inverse output of the i-th memory element; and t, Ij are, respectively, the direct and inverse values of the informational input device; and, and-2 are, respectively, the values of the direct and inverse trigger output .55 The memory elements serve as the dp of storing intermediate and final results of dividing information into a polynomial. The number of memory elements, as well as logical blocks 2 and 3, is equal to r — the maximum exponent of the generating polynomial.

Logical blocks 2 and 3 serve to implement the excitation functions (I and 2) of the outputs of the blocks excite the inputs R and S of memory elements 1.

The element OR 7 serves to implement the exit function.

Y X ,, X, i,

(3)

15 20

25

thirty

35

40 45 SP 55 by means of which the verification elements of the code combination are formed.

Elements NOT 5 and OR 6 serve to implement the function

f (u, vuj),

who is involved; in the formation of the excitation function (1).

In the initial state, the first outputs of the memory elements 1 and the outputs of blocks 2 and 3 are in the zero state. In the first cycle of operation of the device, a pulse is applied to the first input of the distributor 4 from the first output of the distributor, which translates it into a state in which a single signal is supplied from the second output of the distributor trigger 4 to the third input of the key element 8 and the eighth input of unit 3. From the first output of the trigger 4 of the distributor, a zero signal is applied to the second input of the key element 8 and the seventh input of the block 3.

Information signals are transmitted to the tenth input of block 3 and simultaneously to the fourth input of the key element 8 successively to clock cycles, the passage of which through the key element 8 is allowed from the second output of the distributor trigger 4 by a signal. The passage of the test signals from the output of the element OR 7 is prohibited by the zero signal from the first output of the distributor.

The inverse value of the input information signal is fed from the output of the element HE 5 to the nine input of block 3 and the second input of the element of RSHI 6, the output of which forms the function (,), which participates in the formation of the excitation functions (1) of all r-1 elements 1 memory Therefore, the output of the element OR 6 is connected with the fifth) inputs of all r-1 logical blocks 2.

Since, in the initial state of the device, zero signals are removed from the outputs of blocks 2, on the first cycle of operation the r-1st elements of memory 1 do not change their state.

Depending on the type of information supplied from the input of the cyclic code coding device to the ninth input of block 3, the first K cycles, all elements of AND and OR of block 3 participate in the formation of the excitation function (2) of the gth memory element 1, except for Both 18 and 20, the passage of signals through which is prohibited by the zero signal from the seventh input of block 3.

In the event that a single signal is applied to the device input, it goes through the elements of AND 22 and OR 26 to the second output of block 3. Formed. the bath of single signals at the outputs of the remaining elements And is forbidden by the zero signal from the first input of block 3 for elements 15-20 and the zero signal from the ninth input of block 3 elements And 23 and 24 and the zero signal from the third input of block 3 for the element 21 Therefore, a zero signal is generated at the first output of block 3. A single signal from the second output of block 3 converts the first output of the nth item 1 of the memory into a single state. In the second cycle of operation of the device, this single signal from the first output of the gth element 1 of the memory goes to the third input (rl) -ro of the block 2 in which it participates in the formation of the excitation functions (1) of the (rl) -th element 1 of the memory . At the same time, since the second and fifth inputs of (r -) - second block 2 are also supplied with single signals taken from the second (inverse) output (rl) -ro of memory element 1 and the output of element OR 6, respectively, the single signal through elements 13 and 11 are fed to the second output of the (r-1) th block 2 and, due to the connection between it and the second input of the (r-1) th memory element 1, the latter changes its state to the opposite: at the first exit (rl) -ro memory element 1 appears unit, In turn, due to the connection between the first output (rl) -ro memory element 1 and the first input (rl) -ro Lok 2 on the next cycle of operation of the device (z-1) th block 2 is allowed proholzdenie signal from the fourth input through AND gates 13 and 11 .On its first output and

This is simultaneously prohibited by the zero signal from the second output (d-1) of memory element 1 to the second input (d-1) of unit 2, passing the signal from the third input (rl) -ro of block 2 through elements 14 and 12 to his second exit.

Later on (K + 1) -th cycle, the operation of the device occurs in a similar way; in the JM cycle of operation, the signals generated at the outputs of the i-ro and (i + l) -ro of the memory elements 1 participate in the formation of the state of the i-ro memory element 1 in the (j + l) -M cycle using the excitation functions (1) and (2), formed in the i-th block on the JM cycle of the device.

In that case, if the first cycle of operation of the device is not the tenth input of unit 3, a zero signal is applied, it does not change the state of its outputs, and therefore does not excite the inputs of the nth memory element 1. Therefore, the device will retain its previous, original state.

At the (K + 1) th cycle of operation of the device, a single signal from the (K + 1) th output of the distributor is fed to the second input of the trigger 4 of the distributor and converts its first input to a single, and the second output to the zero state. - signals during r cycles at the output of the device from the element OR 7 and the passage of signals from the input of the device to which the last r cycles at zero signals are given is prohibited.

The output signals at the output of the element OR 7 are formed in accordance with the function of the output (3). In this case, the disjunction of the second output of the first memory element 1 and the first output of the second memory element 1 is formed by the element 14; the first logic unit 2 and is fed to its fourth output, and the disjunction of the second output of the first memory element 1 is formed by the element And 13 of the first logical unit 2 and is fed to its third output.

Logic unit 3 last r clock forms the excitation functions (2 using elements 15, 16, 18 and 20 on its first output. Operation of elements 17, 19, 21-24 is prohibited by the zero signal from the second output of the distributor trigger 4, removed from the eighth input block 3 on the fifth

five

the inputs of these elements. Therefore, during the last r cycles, a single signal can be formed only at the first output of block 3, a zero signal will be removed from its second output. However, the first output of block 3 is connected to the first input of the g-th memory element 1, which means that at the first output of the g-th memory element 1, a zero signal appears, the value of which is the last r cycles does not change, because it can change only in the case of the appearance of a single signal at the second input of this; memory element 1.

Thus, the information cyclically from the first output of the i-ro element is rewritten to the code of the i-1 th memory element, the first two of which are involved in the formation of the verification elements of the code combination obtained at the output of the OR 7 element. K (K + g) - After the clock cycle from the output of the cyclic code coding device, the last check element will be released, and the device itself will be reset to the initial state, in which the first outputs of all memory elements 1 will be set to the zero state. Due to the communication structure between blocks 2 and 3 and memory elements 1, the K information symbols are divided into a generating polynomial. When dividing, the effect of the shift is not due to a special shift operation in the memory elements 1, but due to the structure of the connections between blocks 2 and 3 and the memory elements 1, as well as due to the internal connections of the logical blocks 2 and 3. this does not require time expenditure for the shift, and the elements of the Memory 1 work as an automaton, or this explains the increase in the speed of the cyclic code encoding device.

Claims (3)

1. A device for encoding cyclic codes containing r memory elements, where r is the degree of the generating polynomial, the trigger, the first and second inputs of which are the clock inputs of the device, first and second. The device according to claim 1, differing in that the first logic block contains AND elements, the inputs of the first and second elements are respectively the first, fourth, second and third inputs of the first logic block, the outputs of the first and second AND elements are connected to The first inputs of the third and fourth elements, And and respectively, are in the third and fourth outputs. the pins are connected to the combined 55 of the first logic unit, the second inputs of the key element, the output of which is the output of the device, the third input of the key element is the inputs of the third and fourth elements And are combined and are the fifth input, the outputs are respectively 0 five n 5 five 0 0 five E. With the information input of the device, characterized in that, in order to improve the speed of the device, the elements OR are entered, the element NOT, g-1 first logic blocks and the second logic block, the first and second outputs of the first and second logic blocks are connected to the first and second inputs of the same-named memory elements first and second outputs i-ro (L 3, d) of the memory element are connected respectively to the first and second inputs of the i-th logical block and to the third and fourth inputs (il) -ro of the logical block first and the second exits of the first ale The memory is connected to the first and second inputs of the first logical block of the same name and the third and fourth inputs of the second logical block, the first and second outputs of the second memory element are connected to the first and second inputs of the same logical logic block of the third and fourth inputs of the previous first logical block and with the fifth and sixth inputs of the second logic unit, the third and fourth outputs of the first logic unit are connected to the inputs of the first OR element, the output of which is connected to the input of the key element, The eighth and eighth inputs of the second logic unit are connected to the corresponding trigger outputs, the element output is NOT connected to the ninth input of the second logic unit and to the first input of the second OR element, the second input of which is connected to the second output of the trigger, output to the fifth inputs of the first logical blocks The tenth input of the second logic unit and the input of the element are NOT combined and connected to the third input of the device. 2. The device according to claim 1, characterized in that the first logic block contains the elements AND, the inputs of the first and second elements AND are respectively the first, fourth, second and third inputs of the first logic block, the outputs of the first and second elements AND are connected to the first inputs the third and fourth elements And and respectively are the third and fourth outputs first logical block, second the inputs of the third and fourth elements of AND are combined and are the fifth input, the outputs are the first and second outputs of the first logic unit, respectively. 3. The device according to p., Characterized in that the second logical block contains two groups of elements AND and elements OR, outputs of elements AND of the first and second groups are connected to the same inputs of the first and second elements OR, respectively, whose outputs are the outputs of the second logical block, the first inputs of the elements of the first group are combined and are the first input of the second logical block, the first inputs of the elements of the second group are combined and are the second input of the second logical block, the second inputs of the first, five torus The elements of the first group and the first and fourth elements of the second group, the second, third, fourth elements and the first group and the second and third elements and the second group are combined and are respectively the third and fourth inputs of the second logic unit, the third inputs of the first, third and fourth the elements of the first group and the first, third elements of the second group, the second, fifth, sixth elements of the first group and the second, fourth elements of the second group are combined and are respectively the fifth and sixth in The signals of the second logical block, the fourth inputs of the fourth and sixth elements of the first group are combined and are the seventh input of the second logical block, the fourth inputs of the third and fifth elements of the first group and all elements of the second group are combined and are the eighth input of the second logical block, the fourth inputs of the first, second elements And the fifth entrances of the fourth and sixth elements And the first group and the third and fourth elements And the second group, the third, fifth elements And the first group and the first, second el The elements of the second group are combined and are respectively the ninth and tenth inputs of the second logic unit. Vytody F.y.y. vddy 1 i BA / JfOffT you are one FIG.