SU1162052A1 - Converter of code with sign digit to two's complement form - Google Patents

Description

The invention relates to digital computing, in particular to devices for processing data with an impact when calculating over numbers with bases other than 5

from traditional, and can be used in those industries that use control, modeling and computing machines and devices operating in a sign-based numeral system with bases 1,0,1, in the transition to the representation of numbers in the binary additional code.

The purpose of the invention is to increase 15

performance.

Figure 1 shows a block diagram of the Proposed Converter, 'figure 2 is a block diagram of a group of blocks of controlled inversion. 20

The converter of the digit-by-bit code to the additional binary code contains delay element 1, element NOT 2, element FROM, first group 4 blocks of controlled inversion 25, triggers 5 and 6, element NOT 7, block 8 of memory, second group 9 blocks of controlled inversion. Memory block 8 has four outputs: output of 10 high-order rows; exit 11 zero reset sign; output 12 low order; output 13 inverse transducer. The group of controllable inversion units has the first and second information inputs, the reset input 14, the control input 15, the first clock input 16 connected via the HE 2 element to the clock input 17 of the converter and the second clock input 18. .40

element And 21, element UNEQUAL 22, output trigger 23. The outputs of the triggers 23 and 20 are respectively the first and second outputs 24 and 25 of the controlled inversion unit.

The design and operation of blocks 19 are described in detail in [2].

The proposed device implements the conversion of the digit-significant representation of a number into an additional binary code as the number arrives, starting with the most significant digit, in the case when two digits of the number being converted are received in each clock cycle.

If there is a digit-significant representation of the number (the most significant digits of the number are on the left), to obtain an additional binary code, it is enough to add a zero to the left in the additional digit in the source code, and then on the bits to the nearest any unit to the nearest any unit inclusively, inversely, and inverse - direct conversion according to Table 1.

Table!

Digit abundance _

exact code 1

Inverse

conversion 0

Direct conversion 1 0 1

The group of blocks of controlled inversion (figure 2) consists of identical blocks 19, each of which contains a trigger mask 20, Example.

Initial number

Inverse Transform Areas

Getting the view and will be additional source code

45 numbers.

Extra bit

O 0 7 0 0 7 1 1 0 I 1—1-1 1__1

Additional code

110 1 1110 1

55

In order to form his incomes by two additional binary codes of the sign-,, series, it is necessary in each so-ί co-row number in the process of those. ’

3 1162052 4

convert two incoming in ^; Discharge device taking into account the described conversion rules?

develop the signs that determine the impact of incoming discharges on previous ones}

according to the developed characteristics, to transform the previously accepted bits in accordance with the described rule of the formation of the full binary code of the bit number.

The sequence of the lap device consists

job on the information entry. devices of a sequence of pairs of digits in a redundant sign-digit numeral system, setting a clock series £ _t at the clock input 17 and removing the result at the converter outputs after processing the last pair of digits.

Conversion in each clock cycle of two incoming bits in accordance with the rule for the formation of an additional binary code

doziakopredv

produced by the memory unit 8 (FIG. 1) at the outputs 10 and 12. Formation of the signs determining the influence of the two current digits

5 preceding, is performed by memory block 8 at output 13 and the second element is NOT 7. Conversion of previously accepted bits according to the described rule is performed

10 first 5 and second 6 triggers and the first 4 and second 9 groups of blocks of controlled inversion.

Table 2 is the truth table of memory block 8, made in the form of a ROM, in which 8 *, 8 ^, 8 /

| And 8 ^ - input address signals, '

) a 1.0, 11, 12, and 13 are weekends, with 8 being the positive part of the old of two (odd) digits;

£ 8 is the negative part of the highest of two (odd) digits, 8 \ is the positive part of the younger of two (even) digits, 8 ^ is the negative part of the younger of the two (even) digits.

table 2

entrance at; n Outputs g one 1 * + · one one one l 10 senior level 11 Sign of zeroing 12 Junior level 13 Sign of the inverse transform 0 0 , 0 0 0 0 0 0 0 0 0 one one one one one 0 0 one 0 0 one one 0 0 0 one one 0 0 0 0 0 one 0 0 one one 0 one about one 0 one 0 one one one 0 one one 0 one one one one 0 one one one one one 0 one one 0 0 0 one one 0 one one 0 0 one 0 one one 0 one 0 one 0 one one one 0 one 0 one one one' one 0 0

6

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Continuation of table 2

Inputs

Outputs

⁸ ' ί I I v I _: _ 10 senior level 11 Sign of zeroing 12 Junior level 13 Sign of the inverse transform one one 0 0 0 0 0 . 0 one one 0 one one one. ' one one one one one 0 0 one . one 0 one one one one one one 0 0

Discharges to the information input of the converter, and consequently, to the address input of the memory block 8, arrive at the negative differential of the synchronizing series at the clock input 17.

At the first output 10 of block 8., A transformed senior (odd) current discharge is formed / at the second output 11 - a zero signal indication / at the third output 12 - transformed low (even) current discharge and at the fourth output 13 - a sign of the inverse transformation. Even-numbered digits through the first trigger 5 are rewritten to the first group of 4 controlled inversion blocks, and odd digits through the second trigger 6 to the second group 9. The area of inverse transformation in each group of controlled inverting blocks is formed by the states of the corresponding set of trigger masks 20, while the second information input The first group 4 blocks of controlled inversion is supplied with the constant ”1”, and the second information input of the second group 9 is the inverse value of the even digit, which is necessary for correct the ability to set the inverse transform domain for even and odd digits.

Depending on the value of the signal at the control input 15 and the status of the trigger mask 20, information from the first information input of the block 19 is recorded in the output trigger 23 either in the direct or inverse code. Recording is carried out on the positive differential clock frequency £ _t received at the second clock input 18,

Information from the second information input of block 19 through

^{25, the} trigger mask 20 is supplied to the second output of block 19. Information is recorded on the positive differential of the inverse synchronization series £ _t , which arrives at the first clock input 16 of a group of blocks of controlled inverting.

Upon receipt of a positive im-. pulse to the zero input, the mask trigger is reset to the left state.

Element. 1 delay, the first element NOT 2 and the element 3 provide the sequence of control, clocking and zeroing pulses required for proper operation of the device, at which in each step a pair of digits is first received and the information corresponding to this pair is received from block 8

45 memory, then entering information into triggers 5 and 6 and on the first information input - on the output triggers 23 blocks 19 of the first 4 and second 9 groups of blocks of controlled inverting, and finally preparing the trigger masks 20 modules 19 of the first 4 and second 9 groups for the next measure, consisting of a preliminary zeroing (if

55 of the corresponding attribute) of all triggers — masks 20 of the first 4 and second 9 groups and the subsequent recording of information on the second information input of the first 4 and second 9 groups

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blocks of controlled inversion.

In order to form the result of the sign bit in the code, the first group 4 has one more block 19 than the second group 9. In this connection, the receipt of the digit-significant code of the number at the information input of the device begins with the combination 00.

Signed and even result bits will be formed at the first outputs of 24 blocks 19 controlled inversion of the first group of the 4th first trigger 5, and odd digits at the first outputs 24 of the second group 9 blocks of controlled inverting and second trigger 6 no later than admission to triggers 5 and 6 of the last pair bits formed by the memory block 8 according to the input information, taking into account the sign - on (n / 2 + 1) clock, where η is the digit capacity of the sign bit number being converted.

Table 3 contains data on the hardware costs of conversion, for example, -16-bit number in the device prototype and in the proposed device.

Table3 Item type Device prototype The proposed device 16x4 rom - one Element BAN one Item NOT one 2 Element And 17 sixteen- Element NOT- \ EQUAL VALUE But 17 15 Trigger 33 32

25

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Claims (1)

CONVERSION CONVERSION CODE TO ADDITIONAL BINARY CODE containing the first group of serially connected blocks of controlled inversion, delay element, first element NOT, AND element and the first trigger, the output of which is connected to the first information inputs of the first block of controlled inverting of the first group, the second information inputs of which are the input of the logical unit of the converter, the clock input of which is connected to the first input of the element I, the output of which is connected to the inputs of the reset of blocks y of the first group, the first clock inputs of which are connected to the output of the first element, the delay element output is connected to the second input of the I element, and the clock input of the first trigger is connected to the second clock inputs of the controlled inverting blocks of the first group, the outputs of which are the first group of information outputs of the converter , characterized in that, in order to improve speed, a memory block, a second trigger, a second element NOT and a second group of series-connected blocks are entered into it controlled inversion, the first information inputs of the first block of which are connected to the output of the second trigger, the control input of which is connected to the high-level output of the memory block, the control output of which is connected to the third input of the element I, the output of which is connected to the reset inputs of the controlled inverting blocks of the second group , the second information input of the first block of which through the second element is NOT connected to the low-order output of the memory block and to the control input of the first trigger, the output of the inverse transducer Formation of the memory block is connected to the control inputs of the controlled inverting units of the first and second groups, the first clock inputs of the controlled inverting blocks of the second group are connected to the output of the first element NOT and the input of the delay element, the memory block input is the information input of the converter whose clock input is connected to the clock inputs the first and second triggers, the input of the first element NOT and the second clock inputs of the blocks of the controlled inverting of the second group, the outputs of which are The second group of information outputs of the converter. 1162052 2