SU1265975A1 - Device for generating time intervals - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to expand the range of formation of time intervals. The device contains a reference frequency generator 1, a frequency divider 3, a multiplexer 4, a shift register 6 and a counter 7. To achieve this goal, a synchronization and control unit 2, a number 5 reference intervals register 5 and a counter 8 are introduced into the device to form new connections between the elements of the device . 2 tab. 4 il.

Description

Yu

05 01

The invention relates to a pulse technique and is intended to form time intervals. The purpose of the invention is to expand the range of formation of time intervals. Fig. 1 shows a block diagram of an apparatus for forming time slots; 2 shows a synchronization and control unit; on fig.Z - register the number of reference intervals; figure 4 is a pulse counter. A device for forming time intervals contains a generator 1 of the reference frequency, a synchronization and control unit 2, a divider 3 frequencies, a multiplexer 4, a register 5 of the number of reference intervals, a shift register 6, the first 7 and second 8 counters, and the reference frequency generator 1 is serially connected to the divider 3 frequencies, the outputs of which are connected to the information inputs of the multiplexer 4, the output of which is connected to the subtraction input of the pulse counter 7, the output of the loan which is connected to the subtraction input of the counter 8, the output of the loan after the day is connected to the first input of the synchronization and control unit 2, the second input of which is connected to the generator output 1 of the reference frequency, and the third input is connected to the Start bus, the first output of the synchronization and control unit 2 is connected to the control input of the frequency divider 3, and the second output connected to the reset input in “About the splitter 3 frequency and counters 7 and 8, the outputs of register 6 are bitwise connected to the inputs of counter 8, the outputs of which are connected to the address inputs of the multiplexer 4 and to the first group of inputs of the register 5 the number of reference intervals The second group of inputs of which are connected to the data bus and to the inputs of the register 6, the outputs of the register 5 of the number of reference intervals are connected to the information inputs of the pulse counter 7, the borrowing output of the pulse counter 8 is the output bus. The synchronization and control unit 2 (FIG. 2) consists of the elements OR 9 and 10, inverters 11 and 12, and triggers 13-15, the output of the generator 1 through inverter 12 being connected to the counting input of the trigger 15, whose direct output is connected to the first input the element OR 9, the second input of which is connected to the Start bus, the output of the element OR 9 is connected to the reset inputs in “On the flip-flops 13 and 14, the output of the counter 8 is connected to the inverter 11 and the counting input of the trigger 14, the inverse output of which is connected to its D- input, and direct output is connected to the D-input of the trigger 13, the output of which is Connected to the trigger input of trigger 15, the input of the element OR 10 is connected to the D input of trigger 13 and reset to "On trigger 15. Register 5 (Fig. 3) consists of power supply units 16 and 17, multiplexer 18 and three delay elements 19-21 . Moreover, the inputs of the memory blocks 16 and 17 are connected to the data bus, and their outputs are connected to the inputs of the multiplexer 18, whose address inputs are connected through delay elements 19-21 to the outputs of counter 8. Each counter consists of a reversible counter 22 (FIG. 4), inverters 23 and element 24, and the information inputs of the reversible counter 22 are connected to the outputs of the register 5 of the number of reference intervals, the subtraction input to the output of the multiplexer 4, and the reset input to the output of the synchronization and control unit 2, the output of the loan is connected to the first input of the element Both 24 and through inverters 23 to the second input of the element AND 24, the output of which is connected with the input of the counter 22. The device operates in the following manner. An external device, such as a computer, is used to encode information and memorize registers 5 and 6. Recording is done via the data bus. The device is triggered by a pulse on the Start. At the moment of time corresponding to the pulse of the oscillator 1, the frequency divider 3 turns on and the reset of divider 3 frequency counters and counters 7 and 8 stops, because the number 8 is set at the outputs of counter 8, multiplexer 4 is turned on. divider 3 with oscillator frequency 1. The first of these pulses is inverted by multiplexer 4 and passes through counters 7 and 8 (since they contain the number 0000} on the output bus and on the third input of the synchronization and control unit 2. The pulse on the output bus is the beginning time interval, which is the time interval between two pulses on the output bus.At the end of the pulses at the output of the counter 8, the number corresponding to the number of pulses of the first intermediate interval is recorded in the counter 8, and the scale 8 in which this intermediate interval is counted The feature of the device operation is that instead of the interval, the value of which is set by a multi-digit number and which is formed at a scale value corresponding to one Itza youngest non-zero discharge of that number. A sequence of decreasing intervals is formed, each of which is given in a single digit and is counted in its respective scale, with the sum of intermediate intervals being equal to the interval given by the multiple digit. The choice of the direction of reference from a larger scale to a smaller one and the use of a special coding method, in which, formally, instead of "O junior bit, it is written" A: 10 designation in hexadecimal numbering system) with simultaneous

a reduction per unit value of the older bit allows you to always complete the formation of an interval specified by a multi-bit number, the formation of an intermediate interval at the minimum scale for a given device.

The number given, its time interval value, is recorded in the dimension defined by the smallest scale of the device, with zeros written in the lower bits if the number is specified in a larger dimension (for example, 1050.2 ms to be written as 1050200 μs). Then the zeros in the direction from the least significant bits to the most significant ones are replaced by "A 10 with a simultaneous decrease by one digit of the most significant digit, for example

1050200- (1-1) (A) (5-1) (A) (2-1) (A-1) (A) - A4A19A

The number of digits of the number obtained is reduced by one and the remainder is written to the scale register (6-1) 5 0101 in binary code.

The digits of the coded number alternately each, in addition to the units of the ISS, are reduced by one and written to register 5 in binary code at addresses distributed according to the table. 1. If the number of digits of the number obtained is equal to one, then the digit "unit μs is also reduced by one.

In the specific case, taken for example, the number 8 is counted in the counter 8, and the number 7 in the counter 7 - 9.

The address of the multiplexer 4, determined by the state of the outputs of the counter 8, includes the information input of the multiplexer 4 with the reference intervals corresponding to the most significant digit of the number (Table 2).

If the number 8 is written to counter 8, the loan pulse appears on the N + 1 pulse, therefore the numbers written to register 5 of the number of reference intervals and register 6 are reduced by one, since the output signal corresponding to the beginning of the time interval appears with a delay of one oscillator 1 of the reference frequency with respect to the end of the reset pulse in "About counters 7 and 8 divider 3 frequencies, the first reference period is reduced by one period of the reference frequency. This loss is compensated for by the fact that the number of reference intervals corresponding to the zero scale per unit does not decrease. The inputs of the counter 7 from the output of the register 5 receive information recorded at the read address that matches the scale value, namely the number of reference intervals following, in the direction of decreasing the scale of the intermediate interval.

When the counter 7 counted to the number 0000, a loan pulse is generated from the next input pulse. Counter 7 records information on the number of smaller in scale per unit reference intervals of the next intermediate interval. The number stored in the counter 8 is reduced by one, multiplexer 4 switches to receive reference pulses corresponding to a smaller scale by one. The outputs of the register 5 receives information about the size of the next intermediate interval.

When the counter 8 reaches up to the number 0000, the processing of the intermediate interval of the smallest scale begins. Pulse

5 of the loan, generated by the counter 7, is accompanied by a pulse of the loan of the counter 8, which arrives at the output port and is the end of the formed time interval, it also arrives at the input of the synchronization and control unit 2. As a result, the gating of the device over the bus is removed. The start-up divider of 3 frequencies is turned off, reset to divider 3 counters, and the counters 7 and 8 of the device return to the initial state.

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Claims (1)

Invention Formula A device for generating time intervals containing a serially connected reference frequency generator, frequency divider and multiplexer, as well as a shift register, the inputs of which are connected to a data bus, the first pulse counter whose output of the loan is connected to an output bus, characterized in that expanding the range of time intervals to be formed, a synchronization and control unit, a register of the number of reference intervals, and a second pulse counter, the input subtraction of which is connected to 0 by the multiplexer output, the loan output is connected to the subtraction input of the first pulse counter, the loan output of the first pulse counter is connected to the first input of the synchronization and control unit, to the second input of which the output of the reference frequency generator is connected, and the third input is connected to the Start bus, first output the synchronization and control unit is connected to the control input of the frequency divider, the reset inputs in the “About the frequency divider of the first and second pulse counters are connected to 0 to the second output of the synchronization and control unit, the shift register bits are connected to the inputs of the first pulse counter, the outputs of which are bitwise connected to the address inputs of the multiplexer and to the first group of register inputs 5 the number of reference intervals, another group of inputs of which are connected to the data bus, and the outputs are connected to the inputs of the second counter and pulses. Table 1 Inaorma Sr. unit, ten, cy ononulex, µs µs, the size of the dar 9A hundreds of ms Frequency generator f / 10 f / 102 torus 1 MHz 100 kHz 10 kHz 1 kHz 100 Hz units, dets, hundreds, units, ms, ms, U4 sections with Table 2 f / 1 () 3 f / lO f / 10 f / 10 f / ic 10 Hz 1 Hz 0.1 Hz From the reference frequency generator Bus Start Lienz Exit about from informational 8kodo8 first counter FIG. Fy