SU1076904A1 - Device for raising to some power - Google Patents

Abstract

A DEVICE FOR CONSTRUCTION TO A DEGREE, containing a base register, a matrix of multiplying two bits, a matrix for raising a decimal digit in a square, a decimal counter, a decimal number to pulse number converter, a pulse generator, and a control unit containing a clock generator, the counter and the first decoder, the output of the clock generator is connected to the counter input of the counter, the bit outputs of which are connected to the information inputs of the first decoder, the bit outputs of the base register are connected to the first bars The packs of the inputs of the matrices for multiplying two bits and squaring the decimal digit into squares, the bit outputs of the squaring digit digestion matrices are connected to the digit inputs of the decimal counter, the counting input of which is connected to the output of the decimal number to pulse number code, the bit inputs of which are connected to the bit outputs of the matrix of multiplying two bits, the clock input of the converter of the decimal number into the number-pulse code is connected to the output of the pulse generator, which is ct Expansion of functional possibilities by obtaining the possibility of extracting the square root of a local number, a subtractive counter, a group of elements AND, a comparison circuit, a unit for storing constants are entered into it, an element OR, first and second triggers, mode trigger, first, second and third elements AND, cycle counter, clock counter, second and third decoders, a group of elements OR, first, second, third, fourth and fifth outputs of the first torch decoder are connected to the first inputs of cooTBeTcjTByromHx elements the OR group, the first output: the second decoder is connected to the second inputs of the elements of the OR group, the outputs of the elements of the OR group from the first to the fifth are connected to the control inputs of the base register, the matrix of the construction of the decimal digit in the square, the ten counter, the multiplication matrix of two bits and a decimal number converter in a pulse code, the first group of information inputs of the comparison circuit is connected to the bit outputs of the base register, the second group of information inputs of the comparison circuit The dinene with the bit outputs of the decimal counter, the output of the comparison circuit is connected to the first input of the first electroscope of the group I and the installation input to the CD O 4 unit of the second trigger of the control unit, the output of the pulse generator is connected to the second input of the first element And whose output is connected to the counting the input of the subtracting counter, the bit outputs of which are connected to the second groups of bit inputs of the matrix of multiplying two bits and raising the decimal digit to a square, the information inputs of the base register are connected to input Device house The discharge outlets constants storage unit connected to .informatsionnymi. the inputs of the subtracting counter, in the control unit, the direct output of the first

Description

the trigger is connected to the first input of the first element AND, the output of which is connected to the counting input of the cycle counter, the bit outputs of which are connected to the information inputs of the second decoder, the second output of which is connected to the input of the second element OR, the output of the clock generator connected to the second input of the first element And the first input of the second element And, the second input of which is connected to the inverse output of the first trigger, the reset input of which is connected to the third output of the decoder, the installation process in the unit-first trigger is connected to the output of the second element OR, the second input of which is connected to the output of the third element AND and the reset input of the cycle counter, the first input of the third element AND is connected to the first output of the third decoder, informational inputs of which are connected to the bit outputs clock counter whose counting input is connected

with the output of the second element And the second input of the third element And is connected to the direct output of the second trigger, gating the inputs of the first and second decoders connected to the first output of the mode trigger, the second output of which is connected to the gate input of the third decoder, second, third., fourth, p The sixth, sixth and seventh outputs of the third deifferent are connected respectively to the control inputs of the base register, the matrix of raising the decimal digit in a square, the decimal counter, the matrix of multiplying two bits, the transforms the body of the decimal number in the pulse number code and the control input of the comparison circuit, the second output of the second decoder is connected to the INPUT setting the number of the subtracting counter and the input of the read resolution of the number of the storage unit consant, the seventh output of the third decryptor is connected to the third input of the AND element .

The invention is related to computing and can be applied in digital instruments for processing measurement results. A device is known that contains a pulse generator, a group of elements And, a result counter, a counter of a number and a group of decoders zero and allowing to erect decimal numbers represented by a binary-decimal code in square 1.. The closest in technical terms (the invention is a device containing a base register, a bit matrix, a two-bit product matrix, a number-to-code converter, a pulse generator, and a control circuit 2) The disadvantage of the known devices is the impossibility of extracting the square root from given number The purpose of the invention is the expansion of the functional capabilities of the device by obtaining the possibility of extracting a square root from a decimal number. An apparatus for raising to a power containing a base register, a matrix of multiplying two bits to a matrix for raising a decimal digit to a square, a decimal counter, a decimal number to pulse number converter, a pulse generator, and a control unit containing a clock generator, a counter and the first decoder, the output of the clock generator is connected to the counter input of the counter, the bit outputs of which are connected to the information inputs of the first decoder, the bit outputs of the base register are connected to the first groups of times the serial inputs of the matrix of multiplying two bits and the construction of the decimal digit in the square, the bit outputs of the matrix for the construction of the decimal digit in the square are connected to the bit inputs of the decimal counter, the counting input of which is connected to the output of the decimal converter, to the pulse number code, the bit inputs of which are connected to the bit outputs of the matrix of multiplying two bits, the clock input of the decimal number to pulse number converter is connected to the output of the pulse generator, a subtractive counter is entered, a group And, the comparison circuit, the storage unit of constants, the OR element, the first and second triggers, the mode trigger, the first, second and third AND elements, the cycle counter, the clock counter, the second and third decoders, the group of the OR elements, the first , the second, third, fourth and fifth outputs of the first decoder are connected to the first inputs of the corresponding elements of the OR group, the first output of the second decoder is connected to the second inputs of the elements of the OR group, the outputs of the elements of the OR group from the first to the fifth are connected The first group of information inputs of the comparison circuit is connected to the control inputs of the base register, the matrix for raising the decimal digit to the square, the decimal counter, the multiplication matrix of two bits and the decimal digitizer to the number-pulse code, the second group of information inputs of the comparison circuit is connected to the bit outputs of the decimal counter, the output of the comparison circuit is connected by the first input of the first element of group I and the installation input to the unit of the second trigger In the control unit, the output of the pulse generator is connected to the second input of the first element I, the output of which is connected to the counting input of the computing counter, the bit outputs of which are connected to the second groups of the bit inputs of the matrix of multiplying two bits and squaring the decimal digit in the square, information inputs the base register is connected to the device input; the bit outputs of the constant storage unit are connected to the information inputs of the detracting counter; in the control unit, the direct output of the first trigger is connected to By the first input of the first element I, the output of which is connected to the counting input of the cycle counter, the bit outputs of which are connected to the information inputs of the second decoder, the second output of which is connected to the input of the second trigger and the first input of the second element OR, the clock generator output is connected to the second the input of the first element And the first input of the second element And, the second input of which is connected to the inverse output of the first trigger, the reset input of which is connected to the third output of the second decoder, the input is ki in one of the first flip-flop connected to the output of the second OR gate, a second input coupled to an output of the third AND gate and the reset input of the loop counter, the first input of the third AND gate connected with the first output of the third deshifra-. torus, informational inputs of which are connected to the bit outputs of the clock counter, the counting input of which is connected to the output of the second element I, the second input of the third element I connected to the direct output of the second trigger, the gate inputs of the first and second decoders are connected

with the first output of the trigger modes, the second output of which with the gate input of the third decoder, the second, third, fourth, fifth, sixth and seventh outputs of the third decoder are connected respectively to the control inputs of the base register, the matrix of erecting the decimal digit in the square, de. from a partial counter, a matrix of multiplying two bits, a decimal number converter into a number-pulse code and a control input of the comparison circuit, the second output of the second decoder is connected to the input of setting the number of the detracting counter and the input of the resolution for reading the number of the storage unit for the constants, the seventh output of the third decoder is connected to the third input of the element I.

Fig, 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of a decimal number-to-pulse code converter; in fig. 3 is a block diagram of a control unit.

The device for exponentiation (Fig. 1) contains the base register 1, the decimal digit squaring matrix 2, the decimal counter 3, the decimal converter 4, the pulse number generator 5 pulses, the control unit 6, the multiplication matrix 7 two bits, the subtracting counter 8, the AND 9 element of the comparison circuit 10 and the constant storage unit 11.

The decimal number-to-pulse code converter (Fig. 2) contains a shift register 12, elements AND 13-17, an OR circuit 18, a trigger 19 and an AND 20 circuit.

The control unit (Fig. 3) contains a generator of 21 clocks, a counter 22, a first decoder 23, a first element I 24, a counter of 25 cycles, a second deimefrator 26, a first trigger 27, a counter 28 of clocks, a third decoder 29, a second trigger AOR, the second element And 31, the third element And 32, the element OR 33, group-, elements OR 34 and the trigger 35 modes.

In the device, the construction of a decimal number of 3 square is carried out using the J table.

With this method, the construction of a decimal number, for example, in a square, where a is the first digit of the number, b is the second bit, c is the third bit, the algorithm of the device operation is as follows. First, the first digit of a number is multiplied by all bits of the number A, starting with the first digit. Then the second bit is multiplied by all bits of the number A, and so on. The resulting partial products. are summed, with each subsequent partial product being shifted relative: but the previous one by one bit to the left. 4p Sp

5p

br

R

ba

ai

R

At the base of the number equal to ten, the product of one bit per DRUA (ab, la, sa) occupies two bits, and their

5p

4p

As follows from the reduced recording form, the summation of private products for raising a decimal number into a square is implemented using a decimal counter.

The private products equal to the square of each bit are written into certain bits of the counter: the square of the first bit (c) is written into the first and second bits of the counter, the square of the second bit (b) into the third and fourth bits of the counter, square third grade yes

g

in the fifth and sixth bits of the counter. Private works, equal to twice the works of two bits - 5

6

1076904

1P

2p

SA

military work - three bits.

We transform the form of the record into a form that is suitable for analysis.

Sp

2p

iP

The poles (2cb, 2c4, 2b3) are converted into a number-pulse code and arrive at certain counts of the counter, where they are added to the number located there.

The double pulse number code 2 c4 is fed to the counting input of the second digit of the counter (one) and to the counting input of the third digit of the counter (ten). The number-pulse code of doubled work 2cb arrives at the counting input of the third bit of the counter (one) and at the counting input of the fourth bit of the counter (ten). The number of the pulse code of the doubled product 2a is fed to the counting input of the fourth bit of the counter (one and to the counting input of the nth bit) along the counter (ten). In the device, the square root of the decimal number D is extracted by the method of successive tests. For several cycles. To do this, one consecutively squared the numbers of the natural series da, a, ..., a, differing one by one by grace, (unit), starting with the maximum number that can be extracted from the maximum number A o, and is compared with the number A. The sequence is as follows: the operations continue until the inequality a:, i. E. conditions are met. The operation of extracting the square root of the decimal number A ends at the moment when the inequality a / A is satisfied. The square root of the number A will be equal to the number a, when the difference a 2 is first negative or equal to zero, the difference The square-root and square-root action algorithms are implemented by control block 6. The squaring operation is as follows. When the first pulse arrives from the generator of 21 clocks in the counter 22, the decoder 23 outputs an enable signal to the base register 1, and the number A c1cc t is written to square on it. Upon admission to. the counter 22 of the second pulse from the generator of 21 cycles the decoder 23 carries the enabling signal, which through the group of elements OR 34 enters the matrix 2. By this signal, the square of each bit a b of the number A goes to the corresponding installation inputs of certain binary-decimal counters 3 drives. When a third pulse arrives in counter 22 from a clock generator of 21 clocks, a decoder. 23 outputs an enable signal to a multiplication matrix 7 and a converter to 4 numbers in a code. According to this signal, the doubled product 20b (units) from matrix 7 is fed to a 4 digit converter into a code. When a fourth pulse arrives at the counter 22 from the generator of 21 cycles, the decoder 23 outputs a permit signal for the multiplication matrix 7 and the converter 4 numbers into the code. By this signal, the double product 2cb (ten) from the matrix 7 goes to the converter 4 numbers into the code. Upon receipt of the fifth and sixth pulses of the generator of 21 clocks in the counter 22, the doubled product conversion 2 with | to the proportional number of pulses that goes to counter 3. Upon receipt of the seventh and eighth pulses from the generator of 21 cycles into the counter 22, the decoder 23 outputs a permit signal to the multiplication matrix 7 and the converter 4 numbers to the code that doubles the double conversion, 2a, located in the matrix 7, in a proportional number of pulses, which enters the counter 3. The operation of extracting the square root is performed as follows. When the first pulse arrives from the Generator of 21 clocks in the counter of 25 cycles, the decoder 26 outputs the initial setup signal, which sets all the units of the device, having the digital memory, to the initial state. When the second pulse from the generator of 21 cycles arrives in the counter 25 cycles, the decoder 26 outputs an enable signal to the constant storage unit 11 and the base register 1. By this signal, the number stored in block 11 is rewritten into subtractive counter 8, and the number in register 1 is written to the base register; military root. In addition, by the signal of the decoder 26, coming through the element OR 33, the trigger 27 is reset. At the same time, the output signal of the trigger 27 prohibits the passage of the generator signals of 21 clocks through the AND 24 element to the counter of 25 cycles and allows the passage of these signals through the And 32 element to the counter of 28 clocks. According to the first impulse received from the generator of 21 clocks to the counter of 28 clocks through the element AND 32, the decoder 29 outputs the resolving potential to the matrix 2. According to this signal, the square of each bit a, b from the number recorded in the subtracting counter 8 goes to the corresponding inputs certain binary decimal counters 3 storage. Upon receipt of 28 clocks of the second pulse from the generator of 21 clocks in the counter, the decoder 29 outputs a permit signal to the multiplication matrix 7 and the converter 4 numbers to a code. By this signal, the doubled product of 2cb (units) from the multiplication matrix 7 is fed to the transducer 4 numbers in the code. Upon receipt in the counter 28 cycles of the third pulse from the generator,

The pa of 21 clock decoder 29 provides the enable signal to the multiplication matrix 7 and the number 4 converter to the code. By this signal, the doubled product 2cb (ten) from the multiplication matrix 7 is fed to the transducer 4 numbers in the code.

Upon receipt of the fourth and fifth pulses from the generator of 21 strokes in 28 clock cycles, the double generation of 2 cd is formed into a proportional number of pulses that enters counter 3..

Upon receipt of the sixth and seventh pulses from the generator of 21 clocks, the counter of 28 clocks decoder 29 transmits the enable signal to the matrix 7 and the converter 4, which is used to transform the dual product 2Ba, which is located in the matrix 7, in proportion to. the number of pulses that enter counter 3.

When the eighth pulse arrives from the generator of 21 clocks into the counter of 28 clocks, the decoder 29 outputs a resolving potential to the comparison circuit 10, which compares the number L stored in accumulator 1, from which the square root is extracted from the number in counter 3. In addition, for this signal, the AND 9 element impulses to the subtractive counter 8 if D (abc) The eighth pulse of the clock generator 21 sets the counter to 28 cycles into the output state. The sequence of operation of the device when the following groups of eight pulses arrive at the counter of 28 cycles is similar to that described.

When condition A5; (abc) is fulfilled, the comparison circuit 10 will generate a control signal per element AND 9 and a single trigger input 30. With this signal, trigger 30 causes the potential per element AND 31 to be cleared.

Element 31 will receive a signal from the decoder 29. This signal will set the counter to 25 cycles to its original state and will also go to the zero input of trigger 27. Trigger 27 will issue an enable signal to the And 24 element and a inhibitory signal to the And 32 element. the square-root extraction process ends.

The proposed device as compared with the base object, in which a prototype is adopted, is characterized by a significantly shorter execution time of the square root operation, which can be carried out for several consecutive cycles of the device operation. In this case, when extracting the square root of the number A, the natural row numbers differing by one gradation are successively squared, starting with the maximum number that can be extracted from the number A, until the result-square number smaller than the number from which you want to extract the square root.

With a 2n-bit decimal number A, from which the square root is extracted, there will be 10 such squaring operations. If it is assumed that the execution time of the square root operation from the D number in the proposed device is equal to the squaring time, The new number, which is squared, and the time of reading the result in the prototype, then in the proposed device, the execution time of the square root operation will be reduced in 10

(T / + T2- T.) 10

 10 times.

20

nineteen

13

n

15

(Pue.2

Claims (1)

DEGREE DEVICE containing a register of base, matrix of multiplication of two digits, matrix of raising a decimal digit to a square, a decimal counter, a converter of a decimal number to a pulse-number code, a pulse generator, and also a control unit containing a clock generator, a counter and a first decoder , the output of the clock generator is connected to the counting input of the counter, the bit outputs of which are connected to the information inputs of the first decoder, the bit outputs of the base register are connected to the first groups moves of the matrices for multiplying two digits and squaring a decimal digit, the bit outputs of the decimal digit squaring matrices are connected to the bit inputs of the decimal counter, the counting input of which is connected to the output of the decimal number to pulse-number code converter, the bit inputs of which are connected to the bit outputs of the matrix multiplication of two digits, the clock input of the decimal number to pulse-number converter is connected to the output of the pulse generator, revealing that, in order to expand f functional capabilities by obtaining the ability to extract the square root from a decimal number, a subtracting counter, a group of AND elements, a comparison scheme, a constant storage unit are introduced into the control unit, an OR element, the first and second triggers, the mode trigger, the first, second and the third AND element, cycle counter, clock counter, second and third decoders, the group of OR elements, the first, second, third, fourth and fifth outputs of the first torus desyfrat connected to the first inputs of the corresponding elements of the OR group, the first the second output of the second decoder is connected to the second inputs of the elements of the OR group, the outputs of the elements of the OR group from the first to fifth are connected respectively to the control inputs of the base register, matrix, decimal squaring matrix, decimal counter, two-digit multiplication matrix and decimal number converter into a pulse code, the first group of information inputs of the comparison circuit is connected to the bit outputs of the base register, the second group of information inputs of the comparison circuit is connected to the bit the outputs of the decimal counter, the output of the comparison circuit is connected to the first input of the first element of the And group and the installation input to the unit of the second trigger of the control unit, the output of the pulse generator is connected to the second input of the first element And, the output of which is connected to the counting input of the subtracting counter, the bit outputs of which are connected to the second groups of bit inputs of the matrices of multiplication of two bits and squaring a decimal digit, the information inputs of the base register are connected to the device input, the bit outputs are The storage of constants is connected to the information inputs of the subtracting counter, in the control unit the direct output of the first trigger is connected to the first input of the first AND element, the output of which is connected to the counting input of the loop counter, the bit outputs of which are connected to the information inputs of the second decoder, the second output of which is connected to the zero input of the second trigger and the first input of the second OR element, the output of the clock generator is connected to the second input of the first AND element and the first input of the second AND element, the second the stroke of which is connected to the inverse output of the first trigger, the reset input of which is connected to the third output of the decoder, the unit input - the first trigger is connected to the output of the second OR element, the second input of which is connected to the output of the third AND element and the reset counter input, the first input of the third And element is connected to the first output of the third decoder, the information inputs of which are connected to the bit outputs of the clock counter, the counting input of which is connected. with the output of the second element And, the second input of the third element And is connected to the direct output of the second trigger, the gate inputs of the first and second decoders are connected to the first output of the mode trigger, the second output of which is connected to the gate input of the third decoder, second, third., fourth, fifth, the sixth and seventh outputs of the third decoder are connected respectively to the control inputs of the base register, the decimal digit construction matrix c. a square, a decimal counter, a matrix of multiplication of two digits, a decimal number to pulse converter and the control input of the comparison circuit, the second output of the second decoder is connected to the input · setting the number of the subtracting counter and the permission input to read the number of the constant storage unit, the seventh output is third—? 'its decoder is connected to the third input of the element AND.