SU1228095A1 - Digital frequency generator - Google Patents

Abstract

The invention relates to the field of computing and can be used to obtain a set of C-signals with various frequencies required for data processing, spectral analysis, measurements, etc. The purpose of the invention is to expand the functionality by generating arbitrary frequency signals. The generator contains a clock pulse generator, two counters, a switch, a block of permanent memory, two blocks of RAM, an adder, an And element, and two registers. F function generation; (t) is reduced to obtaining the products f; t (where t s, c is discrete in time, P 0, 1, 2, .., integer) and analyzing a certain bit of the resulting product. 1 il. § (L from to to 00 with SP

Description

" one

The invention relates to digital computing and can be used to obtain a set of signals with different Frequencies required for data processing, spectral analysis, measurements, etc.

The purpose of the invention is to extend the functionality by generating arbitrary frequency signals.

A multi-frequency signal is a set of functions. View sin 21Ti; -t, If we move from sinusoidal functions to rectangular functions, then we can describe them as Ff (t) 1, .yy 2k i 2 iti; (tH2k + t) lt- and

O, if (21s + 1) 2 Mi; (t) 2 (.

fi (t)

F; (t) H

KMii K

(one)

Fi (tl 0 +)

where k 0,1,2 ... is an integer. Before that, f; 4 is a binary number with an integer and fractional part, for example 1001101, 10011. Then the whole part of this number is k and the first digit is after the decimal (the weight of which is 1/2) gives the value of the functions F; (t). The task of generating the functions F; (t) in such a case is reduced to obtaining the products f; t (where i n g is discrete in time, n 0,1,2 ... is an integer) and analyzing a certain bit of the resulting work.

The following scheme can be used to produce works: Suppose that ij is expressed 8 times as a binary number, and t as a 16 bits word that is divided into two eight-bit blocks, denoted A and a:

i; (8 bits.) I A (8 times.) A (8 bits.)

II

f; a (16 bits)

(2)

i; I (16 bits) .8 bits. III i; (A4a1 (24 bits)

Numbers A and o Moryt take 256 values each: from 0000 0000 to 1111 1111. Therefore, for each {there are 256 values of products i; a or ij A (II stage of the calculation scheme). These 256 products280952

Research institutes can be recorded in the permanent storage device (ROM). The memory capacity at this is 256-16 4096 bits

5 The drawing shows a functional diagram of the proposed digital frequency generator.

The generator consists of 1 clock pulse generator, the first counter

10 2, the second counter 3, the switch 4, the block 5 of the permanent memory, the blocks 6 and 7 of the operational memory, the adder 8, the element I 9, the registers 10 and 11. The generator operates as follows 15 times.

Clock pulses from the generator 1 clock pulses arrive at the first counter 2, which divides the frequency by 2 pp times, where m is the number of frequency

20 components. The low bits of the first Counter 2 (in which the digital code takes m values) are used to address memory blocks 5-7. The first bit of the first counter 2 (the digital code on which takes two values O and 1) is used for organizations of two cycles p device works. In the first cycle, switch 4 connects the lower bits of the second

30 of the counter 3 (q) to the second group of address inputs of the block 5 of the permanent memory, the block of memory being included in the record. As in; counter 2 at the lower bits selects m code values, numbers i and i are removed from block 5 of the permanent memory; (i 0,1, ..., m-1) and stored in memory block 6. In the second cycle, the switch 4 connects the higher divisions (A) of the counter 3 to the second group of address inputs of the fixed memory unit 5, the storage unit 6 is switched on at the same time. As in counter 2 at the lower bits

45 enumerates the code values, the numbers are removed from the block 5 of the permanent memory

M - and from the memory block 6 - numbers

of; and summed with the shift (e.g., 8 bits, as shown in the example). One of the bits of the adder 8 (which one will be shown below) is connected to the information

the input of the first register 10. In the second cycle, the element And 9 opens, the clock pulses from the generator 1 clock pulses pass through the element And 9 and arrive at the clock input of the register 10. During the m clock pulses (the duration of each cycle in the register 10 The numbers (1 or O) are sequentially recorded on the selected bit of the adder 8 for the T. frequency signals. The trailing edge of the end of the second cycle is parallel rewriting from the first register 10 to the second register 11 and entered into the second counter 3.

Thus, on the m inputs of register 11 (denoted by 12) with the frequency fp ij (f / 2 rn, the data on the value m of the function P, (t) (O or 1) are updated. Each such function will consist of a sequence of units during C; cycles of frequency 1p and then a sequence of zeros also for 6, cycles. Suppose that 5 + 1th digit of the adder 8 is selected as an informative one. Then from conditions (I) the number change on this bit will occur in the case if a

i; WITH; will exceed 2

2%

numbers ijE; 2, If the period of the signal whose frequency is given by the digital code f; equals

those. shift condition from; ,

2e; -28 J1

frequency cycles

,five

R,

Those.

4Te; 4m2P clock frequency;

i l iroiKT ir.

4m2

Consider the restrictions imposed on the number 5, If 1; has r bits, then the number of clock cycles is 26, must also have at least r bits. The periods cj may differ from each other by one least significant bit of the number C; (discreteness error) This discreteness error does not have to exceed the discreteness when specifying the number i ;. From here 5 2р and expression (3) will take the following form:

; from here is real

(3)

y; -i; m2

2p42

() A digital frequency generator containing a clock pulse generator, two counters, a switch, a block

For example, if i; p 8 is set - the time of the permanent memory 50, an adder, and the output of the generator of clock pulses, is connected to the counting input of the

random number, f stroke m B, then 1; (Hz), i.e. the real frequency will correspond to the binary number f ;,

The second counter 3 counts the frequency pulses ip -ifc, i / 2m. Its volume should be 2p bits: p. lower order bits

the high-order counter, the output of the higher bit of which is connected to the counting 55 input of the second counter and the control input of the switch, characterized in that, in order to expand the functionality

air senior bits expressing

) BUT . I clock count

the number of a. Counter 3 is filled to 2

those. in time

)

G.

zap

tg

2p + |

 For top10

five

zo

tact - - of the given example (t 8, p 8

, kt 2 MHz T, „„ 0.5 s. during this time, all signals at outputs 12 go without phase discontinuities. But after filling, counter 3 should return to zero, all signals at outputs 12 should start again from zero phases, i.e. there will be phase jumps. To prevent this from occurring at the moment when the counter 3 overflows (when all its bits are logical 1), the values of the phase ijt from the outputs 5 of the lower bits of the adder 8 to the second memory block 7 are recorded. Once

the counter 3 returns to the zero state, the memory block 7 goes into a read mode and the residual values of the phases i; t will be added all the time to the number in the adder. Now, a jump in phase does not occur. At the end of each period T, the second memory unit 7 records the new boundary values of phase i; i and thus the generation of the frequency grid can be performed continuously. If necessary, in the beginning of the work, memory unit 7 can be recorded. Initial values of phase shifts for each of the ITI signals of the frequency grid can be written.

If we take as an informational not 5 + 1-D, but 6 + 2-th digit of the adder, then at outputs 12 it is possible to get a grid of frequencies Y; / 2, i.e. each frequency will be twice as low. In general, you can set up several groups of registers 10 and 11 and get a set of frequencies of frequencies C, Y; /. y, 74 ...

25

35

40

45

Claims (1)

Invention Formula the high-end counter, the high-end output of which is connected to the counting input of the second counter and the control input of the switch, characterized in that, in order to extend the functionality by generating signals of arbitrary frequencies, two RAM blocks, two registers and an I element are entered into it, with the low-order bits of the first counter connected to the low-order bits of the address input of the permanent memory block and the first and second RAM blocks to the high I’ll unload the address input of the fixed memory unit with the switch output, the first and second information inputs of which are connected to the output groups of the lower and higher bits of the second counter, the first input of the AND element, the clock input of the first p The registry and the recording resolution input of the first RAM block are combined and connected to the output of the higher time of the first counter, the second one. input element And is connected to the output of the clock pulse generator, the output element And - to the clock input Editor Yu. Sereda Compiled by S. Kurosh Tehred G.Gerber Proofreader A. Ferenc : 2303/49 Circulation 671 Subscription VNIZHI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing pregfine, Uzhgorod, st. Project, 4 the second register, the output of which is to the information input of the first register, the output of which is to the output generator, output, constant memory block - to the information input of the first RAM block and the first information input of the adder, the second information input of which is connected to the output of the second RAM block, information input of which is connected to the output of the adder, output of the k-th ( k 1, ..., D), where m is the size of the form representation of the signal), the bit of which is connected to the input of the sequential recording of the second register, the information output of the first RAM block is connected to the third the information input of the adder, the output of the overflow of the second counter to the input of the resolution of the recording of the second. memory block.