SU1363188A1 - Parallel adder - Google Patents

Abstract

The invention is intended to build highly reliable, ultra-high-speed, specialized microprocesses. The purpose of the invention is to simplify the device and increase speed. Single-ended adder contains one-digit adders 1, half-adder 5, element OR 6, and each one-digit adder 1 P IH (L with and SLE 00 00

Description

consists of the elements of OR and I. The basic algorithm for adding significant digits in a single-digit adder is given by the relation (j; (S) + ((S). V (S) + (f (S-2) + Ct (S-3), where (5) - the weights of the binary bits of the minimum number system

The invention relates to automation and computing and can be used in specialized computers for the parallel summation of multi-digit binary numbers.

The purpose of the invention is to simplify the device and increase speed.

FIG. G shows a parallel adder structural scheme where n is the operand size; in fig. 2 - a one-bit adder circuit is functional.

The parallel adder (Fig. 1) contains nine one-bit adders 1 (-1y, inputs 2 of the first term, inputs 3 of the second term and outputs 4 results, half-adder 5, the element OR 6.

The one-bit adder (Fig. 2) has information inputs 7 and 8, inputs 9, 10 of the transfer, output 11 of the sum, and output 12 of the transfer, the element 1, 13, and the element 14.

A parallel adder performs summation of the n-bit parallel numbers A arriving at its inputs, represented in the excess minimum number system as follows:

BUT

). (one)

where o, ij;

(+ (S)

with S O;

at, 1; (1a)

((S-2) + V (S-3) with S 1.

The value (n + 2). Determines the power of the minimum n-bit code.

laziness. Since at least four bits of zeros follow after each unit of discharge in the minimum images of the terms, the unit of transfer in the S-th bit is possible to be placed in the (h-2) -th and (5-3) -th digits of the sums without delay. 2 Il.

f

0

The recurrence relation (1a) implies an algorithm for adding significant digits in the minimum number system.

y (S) + ((S) 9 (S) + v (S-2) + V (S-3) (2)

Thus, the summation rule for the minimum number system is

 LTD

0 + 1 1 1 + 1 1011.

Based on the expression (2) and the reduced rule, each W-th one-bit adder (, p-1) of the minimum codes at the output of the sum generates a signal of the sum of the m-th bit as a function of the logical addition of the m-bits of the first and second terms and transfer signals from (t + 2) -th and (t + 3) -th bits П П + +

t 2

25

V.

(3)

and at the output of the transfer, the 1st one-digit adder generates the transfer signal Il.g ,,. (, n-1), entering in (1-2) -th and (1-3) -th bits directly, as a function of the logical multiplication A. and

b.V.Z.

AT

e

(four)

From expression (1) it follows that in the images of the minimum number system there are those in which c. In the general case, after each bit from left to right, there should be at least four digits of zeros (such images are

allowed and contain the minimum number of units).

Consequently, after summing up the significant 1 bits, the unit of transfer can be immediately placed in (1-2) -and (1-3) bits of the sum, since these bits of both terms are obviously zero. In addition, in the minimum images of the numbers (1), the second bit of the terms constantly contains the zero character. This means that the unit of transfer from the first or from the third digit can also be immediately placed into the second digit of the sum according to the ratios

V (o "- yd) (,

Q) (3) + t, (3) s,; (3) +

V (2),

which follow from the sequence (1a).

Thus, each one-digit adder in the proposed adder contains only two simplest logic elements, and the sum value is generated at the output after the summer values of the terms arrive at the inputs, since the transfer signals are transmitted without delay. The essence of the invention consists in the implementation of formulas (3) and (4),

Single-digit adders 1 are designed to generate a sum signal at the output 11 according to the relation (3) and generate a transfer signal at the output 12 according to the relation (4); The implementation of the basic addition algorithm (2) is carried out by corresponding connections between the outputs 12 and the inputs 9-10 of the single-row adders 1.

The half-adder 5 serves to generate a sum signal at the sum output of the transfer signal at the transfer output according to the relation (5). The OR 6 element is necessary for combining the output of the half-adder 5 and the output 12 of transferring the one-bit adder C. The implementation of the algorithm-addition in the three least significant bits of the minimum code described by relations (5), (6) is carried out by appropriate links between the transfer ports of the half-adder 5, the one-bit adder and the inputs 7 and 8 of the sum of the one-bit adder 1 ,.

Thus, the introduction of new one-digit adders 1, half-63638

Matrix 5, the element OR 6, and the relations between them determine the essential differences between the proposed and the known, and ensure that a positive effect is achieved.

Parallel adder works - as follows.

Suppose you need to add 10 minimum codes of numbers 19 and 20, represented as follows:

Bit, No. Weight bit yes Number 19 Number 20

1098765432 1

1612 97543221

1 about 00001000

1 O O O O O 10000

20

25

The codes of the first term and the second term are supplied to the inputs 2 and 3 of the single-ended adder, respectively. At the same time, at output 1 of the sum of one-bit adders C, 1 and 1, single signals appear. At the same time, from the output 12 of transferring a one-bit adder Ij, a single signal through the elements OR 13 of one-bit adders 15 and 1 is set at the outputs 11 of the sum. Consequently, after the arrival of the codes of the terms on the inputs 2 and 3 of the adder, at the output of the 4 sums, the code 1011010000 39 is formed. The addition is completed.

thirty

Claims (1)

Invention Formula A parallel adder containing, in each bit of de, except the first, one-bit adders whose sum outputs are connected to the outputs of the corresponding bits of the result of the adder, characterized in that, in order to simplify the adder and increase its speed, a half-adder and an OR element are introduced for the first time, each one-digit adder contains an AND element and an OR element , the first and second inputs of the OR element and the AND AND one-bit adders from the second to the nth digit, where n is the width of the operands, are connected respectively to the inputs from the second to the nth bits of the first and second operands of the adder, the inputs of the first and second operands of the first bit of the adder are connected respectively to the first and second inputs of the half adder the first bit, the output of the sum of which is connected to the first input of the element OR of the first bit of the adder, the output of which is connected to the output of the result of the first bit of the sum 13631 pa, the output of the one-bit lump cell of this bit is connected to the output of the sum of this one-bit adder; the first IQ inputs of the AND element and the OR element of the one-bit adder of the first bit, the second inputs of the AND element and the editor A, Dolynich Compiled by M, Esenina Tehred L.Oleynik Proofreader M. Pojo Order 6362/39 Circulation 671 Subscription VNIIII USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 88b or one-digit adder of the first digit is connected to the transfer output of a single-digit adder of the second digit, the transfer output of the 1-g single-digit adder. (, p-.1) is connected to the third and fourth inputs of the OR element (1-2) - first and (1-3) th one-bit adders; the transfer output of a one-bit third adder is connected to the second input of the first-order MI element.