SU1411733A1 - Multiplication device - Google Patents

Abstract

The invention relates to computing and can be used in the pipeline processing of digit-significant numbers, which allows operands to be represented and to receive the result of their processing by successive bits of a bit ahead. The aim of the invention is to increase speed. This goal is achieved by the fact that in a multiplying device containing two delay elements 1.2, a digit-significant adder 3, a group of operating modules 4 each containing six triggers 6-11, four AND-OR elements 12-15 and delay element 5 , four additional elements, HE 35-38, are additionally introduced, and in each operational module, four significant digesters 39-42 with corresponding links are inserted. I il., 2 tab. but

Description

vi

CA2 OE

The invention relates to computing technology and can be used in conveyor bitwise processing of operands represented in a redundant sign bit system (IZSS) with OD.

 The purpose of the invention is to improve speed.

The drawing shows a multiplication circuit.

The device contains the first 1 and second 2 delay elements, the signed bit adder 3, the operational modules 4, each of which contains the delay element 5, six triggers. 6-11, four elements AND-OR 12-15, - Moreover, the first 16 and second 17 inputs of the multiplicand device are connected respectively with the first 18 and second 19 inputs of modules 4, the first 20 and the second. 21 inputs - / device multipliers are connected respectively to the third 22 and fourth 23.-inputs of modules 4 and through elements i and 2 of the back; kki respectively to the fifth 2A and sixth 25 inputs of modules 4, input-.26-start of the device is connected . with the seventh INPUT 27 module 4 of the highest bit,.

. In each module 4, the seventh input 27 is connected through the delay element 5 by the modulating inputs of the third 8 and fourth 9 flip-flops of module 4 and with the first output 28 of module 4, the information inputs of the first 6 and second 7 triggers are connected respectively to the first 18 and second 19 inputs module 4. The direct output of the first trigger 6 is connected to the first inputs of the first groups of the first 12 and second 13 AND-OR elements, the first inputs of the second groups of which are connected to the direct output of the second trigger 7. The direct output of the third trigger 8 is connected to the first the inputs of the first groups the third 4th and fourth 15 elements AND-OR, the first inputs of the second groups of which are connected to the direct output - the fourth trigger 9.

The first input 18 of the module is connected to the second input of the first group of the third element AND-OR 14 and the second input of the second group of the fourth element AND-OR 15. The second input 19 of the module is connected to the second input of the second group of the third element AND-OR 14 and-with the second input of the first group of the fourth element AND-OR 15. The outputs of the p 10

and the sixth 11 flip-flops are connected respectively to the second 29 and third 30 outputs of module 4. The first output 28 of module 4 of each bit, starting with the highest one, is connected to the seventh, input 27 of module 4 of the lowest bit by one. The second 29 and third 30 outputs of module 4 of each bit,

Q except senior., Are connected accordingly. with the eighth 31 and ninth 32 inputs of the module, 4 bits, following in order of precedence. . . Second 29, third 30, fourth

The 5 33 and fifth 34 outputs of the high-order bit module 4 are connected respectively to the first, second, third and fourth inlets of the sign type adder 3, the outputs of which are high-end device outputs. The eighth 3 and ninth 32 inputs of the module 4 of the highest bit are connected. They are connected to the input of the zero potential of the device.

In addition, the device contains

5 .. four elements are NOT 35. - 38, and in each module 4 there are four digits 39 and 42, and the inputs of the first 35, second 36, and third. 37 and fourth tv elements tfe

0 are connected respectively with the first 18, second 19, third 22 and fourth 23 inputs of modules 4, and the outputs respectively with the tenth 43, eleventh 44, twelfth 45 and thirteenth 46 inputs of the modules 4. Sixth 4.7 and seventh 48 outputs of the module .4 senior bit connected respectively with, fifth and sixth, in-. There is a single digit adder 3.

d Fourth 33, fifth 34, sixth 47 and seventh 48 outputs of module 4 of each bit are connected respectively with - fourteenth, fifteenth, sixteenth and seventeenth inputs 49 - 52 module 4 of the next highest order. The fourteenth, nt, nadtsaty, sixteen and seventeenth - inputs 49 - 52, respectively, the module 4 lower digits are connected to the input of zero potential of the device 5

five

9

properties

Moreover, in the module, 4-clocking inputs of the first 6 and second 7 flip-flops are connected to the seventh input 27 of the module 4. The inverse output of the per-second flip-flop 6 is connected to the second inputs of the second groups of the first 12 and second 13 elements. I-INR, inverse output of the second trigger 7 - with the second inputs

, five

The first groups of the first 12 and second 13 AND-OR elements, the inverse output of the third trigger 8 - with the third inputs of the second groups of the third 14 fourth 15 AND-OR elements, the inertial output of the fourth trigger with the third inputs of the first groups of the third 14 and fourth 15 elements AND-OR. The third inputs of the first group of the first element AND-OR 12 and the second group of the second element AND-OR 13 are connected to the third input 22 of module 4, the fourth input 23 of which is connected to the third inputs of the second group of the first element I-INR 12 and the first group the second element AND-OR 13. The fourth inputs of the second group of the first element AND-OR 12 and the first group of the second element AND-OR 13 are connected to the twelfth input 45 of module 4, the thirteenth input 46 of which is connected to the non-twelve inputs of the first group of the first AND-OR element 12 and the second group of the second element AND-OR 13. De-25 with input 43 of module 4 is connected with the fourth inputs of the second group of the third element AND-OR 14 and the first, group of the fourth element AND-OR 15, the eleventh input 44 of module 4 with the fourth inputs of the first group of the third element AND-OR 14 and the second group of the fourth element AND-OR 15. The information inputs of the third 8 and fourth 9 flip-flops of module 4 are connected respectively to the fifth 24 and. the sixth 25 inputs of the module 4. The first, second and third inputs of the first signed bit half-summat. 39 are connected to the outputs of the first, second AND-third elements AND-OR 12, respectively, 14, and the first, second and third inputs of the second half-block number significant 40 - respectively

the output of the fourth element, AND-OR 15, the eighth, 31, and the ninth, 32 inputs of module 4. The first outputs of the first 30 and second 40 sign-discharge half-dispensers are connected respectively to the quarter and fifth 34 outputs of the module 4. The first, second and third inputs of the third sign-discharge half -matmator 41 are connected respectively to the second outputs of the first 39 and second 40 sign bit half-adders and the fourteenth input 49 of module 4. 55 The first output of the third sign-discharge half-adder 41 is connected to the sixth output 47 of the module 4, and the first.

40

45

five

th th go „go e-25,,„. and -

, but

55 40

45

second and third inputs of the fourth half-adder znakorazr-stand 42 - respectively to the second output of the third znakorazr-stand half-adder 41, 50 and fifteen sixteenth 51 inputs modulation 4. A first output of the fourth znakorazr-stand half-adder 42 is connected to the seventh output of unit 48, the second output of the fourth half-adder-stand znakorazr 42 - with the information input of the fifth trigger 10. The seventeenth input 52 of module 4 is connected to the information input of the sixth trigger 11.

Elements 1, 2, and 5 delay the delay by one cycle.

The device works as follows.

The first inputs of the multiplier 16 and multiplier 20 receive positive bit codes of significant operands, while the second inputs 17 and 2 receive negative codes (multiplier A and multiplier B codes), sequentially, bit by bit, starting with the oldest. The result at the outputs of the device is also obtained by a sequential sign-digit code, starting with the highest bit. The delay introduced by the device is three cycles. From the device input 26, a clock pulse arrives at the clock inputs of flip-flops 6 and 7 of module 4 of the highest (first) bit, and the current values of positive and negative bits go at the information inputs of flip-flops 6 and 7 Dov mnimogo. Further, the passage through the circuit consisting of series-connected elements 5 of the tactful delay of all modules, a single impulse permits alternate insertion of the multiplicable bits into the flip-flops 6 and 7 of the modules of the corresponding bits.

To the clock inputs of the flip-flops 8 and 9 modules 4 of the senior bit, the control signal is received in the second cycle (from the output of the module 5 delay unit). At the information inputs of the triggers 8 and 9 modules of all bits, the sequential code of the multiplier B is received by delay elements 1 and 2 delayed by one clock cycle. Thus, the first bit of the multiplicand is recorded in the triggers 6 and 7 of the module of the first bit on

the first cycle of the device operation, and the first bit of the multiplier is triggered by the 8 and 9 modules of the first bit on the second cycle, at the same time as the second bit of the multiplicand into the corresponding triggers of the second bit module, etc. Such an entry allows converting a serial code of operands into a parallel one and storing it in flip-flops 5–8 to form the values a and b |, respectively (these are the states of flip-flops 6–9 of the i-th bit modulus, the bottom of the incoming operands is reduced to bitwise summation in accordance with the expression:

(A-B) - where (A-B);

(A-B), - ,, -n,

(one)

value of the 1st digit of the product in the current cycle T |

 (A-B) j, is the value of the (i + 1) -th (minor) bit in the preceding measure T - 1;

a, b are the current values of the multiplier and multiplier bits (in T); a., b- - state triggers. multiplier and multiplier in the current cycle T. With a significant bit of coding in the binary system with the numbers 1, O, I, each digit of the number is represented by a combination of positive and negative parts in accordance with Table. one.

Table 1

X number

+ 1 -I

However, a different representation of X 0 (1)

X 0 (1)

I About About 1

At the bottom of the coding expression (I) takes the form:

(A, B) t + (A-B) -. (Ab) t,

20

+ (A-B) f4 + (atL ,.) + (at-b,) + + (a-b) + ().

(2)

However, a random representation of numbers characterized by a bounded

The transfer depth in the summation allows one-by-one processing in multiplication according to expression (2) to be performed on the same modules 4. At the same time, the terms (AB) t and (A-B)., arrive as the first and second term of expression (2 ) to the inputs 31 and 32 of the i-ro digit module from the outputs 29 and 30 of the 4 (i + 1) -th (junior per unit) discharge unit. The terms (a, b)% () -, (atb,) - and (,) are formed at the outputs of the first, second, third and fourth elements, AND-OR 12-15 module 4, respectively, according to the expressions

(a-b) a | -L; .a- (abт-) a b - a

() but-

 :

t r-h (a - C) - a; . B- but; | L | Va; bt -.

The boxes with a dash at the top are the inverse values of the corresponding signals obtained for the current values of a and be of the outputs of the HE elements 35 - 38, for the signals of a and b, from the inverse outputs of the corresponding triggers.

The summation of the three digits of the single numbers according to expression (2) is performed in parallel on the first 39 and second 40 sign half-adders of module 4, and the formation of the discharge, taking into account the incoming from mob; va, is in V a:

 but

l ;;

 Bt-varbt a

va, -k o-.

t g-h; | L | Va; bt -.

(3) (4) (5) (6)

4 junior bits of two significant discharge of Piex and R2.bh third 41 and fourth 42 significant half half-modulators of module 4 were blowing.

The half-adders 39 and 41 form the values of the positive transfer P and the negative sum Z with; Shuch positive x, and one negative x, and the significant half-summators 40 and 42 produce the negative transfer P and positive sum Z With two negative x, y and one positive x terms (see Table 2). t b „c 2

Mathematical signs of variables, corresponding to the input and output signals of semi-summator, shown in the drawing.

The signals of the output translations P, P of the sign bit half-adders 39-42 of module 4 are fed to the outputs of module 4 for use as input signals from P., the module of the next-most-significant bit. The positive and negative values of the i-ro bit formed at the second output of the fourth significant half-adder 42 and at the seventeenth input 52 of module 4 of. the expiration of the time required for operation of the half-modulators of module 4, in the current clock cycle, according to the sync pulse f, is triggered by triggers 10 and P. Signals from the -10 and 11 high-end trigger outputs, as well as the output signals of the high-order module 4 are received to the input of a three-input serial multi-accumulator adder 3, which forms a discharge-by-discharge result of the calculations. The delay introduced by a three-input sequential signed-bit adder is two clocks.

An additional positive effect of the invention is to expand the scope of application by

homogeneity of the device and the possibility of using a zero encoding value by a combination of single signals of positive and negative parts.

et e and

Form mlaisobbr

A device for multiplying, containing the first and second delay elements, the signed bit adder and n (n is the number of bits in the multiplied-, my operands) operating modules, each of which contains a delay element, six triggers and four AND-OR elements, the first and the second inputs of the multiplicand device are connected c-respectively to the information inputs of the first and second triggers of each operational module, the first and second inputs of the multiplier, the devices are connected respectively to the inputs of the first and second delay elements, you the strokes of which are connected respectively to the information inputs of the third and four triggers of each operational module, the input-launch of the device is connected to the input of the delay element of the operational module of the higher discharge, the outputs of the fifth and sixth triggers of which are connected respectively to the first and second inputs of the significant accumulator The output of which is the output of the device, the clock input of which is connected to the clock inputs of the fifth and sixth triggers of each operational module, the output of the delay element k-ro operation module

(k 1 ... n - 1) is connected to the input of the delay element (k + 1) -th op-module, and in the operating module the output of the delay element is connected to the clock inputs of the third and fourth triggers, the first output of the first trigger is connected with the first inputs of the first rpyrtn of the first and second elements AND-OR, the first inputs of the second group of which are connected

with the direct output of the second trigger, the direct output of the third trigger is connected to the first inputs of the first groups of the third and fourth AND-OR elements, the first inputs of the second groups of which are connected to the direct output of the fourth trigger, the information input of the first trigger is connected to the second input of the first the group of the third element is AND-OR and with the second input of the second group of the fourth element is AND-OR, the information input of the second trigger is connected to the second input of the second group of the third AND-OR element and the second input of the first group of the fourth AND element - OR, distinguished by the fact that, in order to improve speed, it contains four NOT elements, and each operational module contains four sign-half semi-summators, with the first and second inputs of the multiplicand first and second inputs of the multiplier of the device - 15 cops AND-OR connected respectively

through four, the first outputs of the significant digits of the semi-intelligence of the first to fourth operational module of the highest bit are connected respectively to the inputs of the third to the sixth signed discharge accumulator, the outputs of the fifth and sixth triggers, the first outputs of the significant discharge half-masters of the first on the fourth | (k + 1) -th operational module are respectively connected with the first and second inputs of the second sign of the second half-combinator, with the first input of the third sign-significant half-summator, with the first and second inputs of the fourth sign the aspire semi-adder and with the information input | iecToro the trigger of the k-ro operational 1 module, the first and second inputs of the second 1PO sign discharge semi-summator, the first input of the third sign-size discrete p-ootusmatmator, the first and second inputs of the fourth sign-size semi- sum (|: Ummator on the information input of the six trigger of the nth operational module DOOL1I is connected to the input of the zero quadrant of the device, the first and second multipliers of the device are connected to the second inputs of the first and second groups of the first Iodul, the outputs of the elements And from the first g (about a quarter are connected respectively to the third input of the second group of the second element AND-OR, with the third 1 move of the first group of the third element Composer A

editor V, Petrash

Tehred M. Khodanych

3655/44

Circulation 704Subscribe

. VIIIPI State Committee of the USSR

for inventions and discoveries 113035, Moscow, “{-35, Raushsk nab. 4/5

And-OR, with the third input of the second group of the first AND-OR element and the third input of the first group of the first AND-OR element of each operational module, and in the operational module the input of the delay element is connected to the clock inputs of the first and second triggers, the second and third inputs The first group of the first element AND-OR is connected respectively to the second and third inputs of the second group of the second element AND-OR, the second and third inputs of the second group of the first ele

0

With the second and third inputs of the first group of the second element AND-OR, the third inputs of the first and second groups of the third element AND-OR are connected respectively to the third inputs of the second and first groups of the fourth element AND-OR, the inverse output of the first trigger is connected to the fourth inputs of the second groups of the first and the second Ele.

5 cops AND-OR, the inverse output of the second trigger is connected to the fourth inputs of the first groups of the first and second. And-OR elements, the inverse output of the third trigger is connected to the fourth inputs of the third group - the third one. first and fourth elements AND-OR, the inverse output of the fourth trigger is connected to the fourth inputs of the first groups of the third and fourth elements I-IPI, the first, second and third inputs of the first sign-size half-adder are connected to the outputs of the first, second and third elements AND-OR, respectively the third input of the second signed bit half-adder is connected to the output of the fourth AND-OR element, the second and third inputs of the third signed bit half-adder are connected respectively to the second outputs of the first and second signed-bit half summators, the second output of the third sign bit half summator is connected to the third input of the fourth sign bit size half summator, the second output of which is connected to the information input of the fifth trigger.

lyuyev

five

0

0

Proofreader L. Pilipenko

Claims (1)

SUMMARY OF THE INVENTION A device for multiplication containing the first and second delay elements, a bitwise adder, and η (η is the number of bits in the multiplied operands) of the operating modules, each of which contains a delay element 15, six triggers, and four AND elements -OR, and the first and second inputs of the multiplier device are connected respectively to the information inputs of the first and second triggers of each operational module, the first and second inputs of the multiplier, the devices are connected respectively to the inputs of the first and second delay elements whose outputs are connected 25, respectively, with the information inputs of the third and fourth flip-flops of each operating module, the input –start of the device is connected to the input of the delay element of the operational module of the highest order, torus outputs, show! in the drawing. The signals of the output transfers P _{1t of the} symbol-bit half adders 39 42 of the module 4 are fed to the outputs of the module 4 for use as input signals P _{1g1 <} , P _26x in the next- _{highest-order} module. Positive and negative values of the i-ro discharge formed at the second output of the fourth half-bit half adder 42 and at the seventeenth input 52 of module 4 of. the expiration of the time required for the operation of the half-adders of module 4, in the current clock cycle, f _T are recorded in triggers 10 and 11. The signals from the outputs of the triggers .10 and 11 of module 4 of the highest order, as well as sig. The output transfer zones of the high-order module 4 are fed to the input of a three-input sequential sign-discharge adder 3, which forms the result of the calculations bit by bit. The delay introduced by the three-input sequential sign-discharge adder is two clock cycles. An additional positive effect of the invention is to expand the scope due to the fifth and sixth triggers of which are connected respectively to the first and second inputs of the digit-adder, the output of which is the output of the device, the clock input of which is connected to the clock inputs of the fifth and sixth triggers of each operating module, the output of the element the delay of the k-th operational module 40 (k = 1, ..., η - 1) is connected to the input of the delay element of the (k + 1) -th operational module, and in the operation module, the output delay element 'is connected to the clock inputs of the third and. fourth, triggers, the direct output of the first trigger is connected to the first inputs of the first groups of the first and second AND-OR elements, the first inputs of the second groups of which are connected 5Q with the direct output of the second trigger,. the direct output of the third trigger is connected to the first inputs of the first groups of the third and fourth AND-OR elements, the first inputs of the second groups of which are connected to the direct output of the fourth trigger, the information input of the first trigger is connected to the second input of the first group of the third AND-OR element and to the second input the second group of the fourth AND-OR element, “the information input of the second trigger is connected to the second input of the second group of the third AND-OR element and the second input of the first group of the fourth AND-IPI element, which means that, in order to improve performance, it contains four NOT elements, and each operating module contains four half-adders, the first and second inputs of the multiplier ^ first 'and the second inputs of the device multiplier are connected respectively to the inputs of NOT elements from the first to the fourth, the first outputs the half-adder half-adders from the first to fourth operational modules of the highest order are connected respectively to the inputs from the third to sixth digit adders, the outputs of the fifth and sixth triggers, the first outputs of from the first to the fourth (k + 1) -th operating modules, the half-admittance half-adders are connected with the first and second entrances of the second half-admitter half-admitter, with the first second of the third best-sized rumor, with the first and second Mi the fourth digit-bit half-adder and with the information input! the cleaned trigger of the k-th operational module, the first and second inputs of the second digit-half-adder, the first input of the third digit-half-adder, the first and second inputs of the fourth digit-half-adder and the information input of the sixth · trigger of the η-th operational module the input of the zero potential of the device, the first and second inputs of the device multiplier are connected respectively to the second inputs of the first and second groups of the first AND-OR element of the operating Module, the outputs of the AND elements from the first rjo the fourth are connected respectively | o to the third input of the second group of the Third element AND-OR, to the third input of the first group of the third ele