SU1287145A1 - Computing cell - Google Patents

Abstract

The invention relates to computing. The invention allows to extend the functionality of the cell by performing addition operations (viitani), which is achieved by introducing into the computational cell with random processing of numbers, containing the multiplier 14 register, adder 15 and delay elements 23-27, counter 1, multiplier 13 register, shift register 12, trigger 16 digits of the multiplier, elements AND 2-10, OR 11, I-ШШ 17-22. 2 ill., 1 tab. (L 00 "and ate sruzh. /

Description

(2) 3935578 / 24-24

(22) 06/14/85

(46) 01/30/87. Bul № 4

(71) Leningrad Scientific and Production Association Burevestnik

(72) Yu. M. Monashkin

(53) 681.325 (088.8)

(56) Japanese Patent No. 54-31939, class. G 06 F 7/39, 1979.

Japanese patent number 56-29306, cl. G 06 F 7/52, 1981.

(54) COMPUTING CELL

(57) The invention relates to computing. The invention allows to extend the functionality of the cell by performing addition operations (viitani), which is achieved by introducing into the computational cell with random processing of numbers, containing the multiplier 14 register, adder 15 and delay elements 23-27, counter 1, multiplier 13 register, shift register 12, trigger 16 digits of the multiplier, elements AND 2-10, OR 11, I-ШШ 17-22. 2 ill., 1 tab.

(L

00

"and

ate

srug./

fO

112871

The invention relates to computing technology and hydraulic data ((| | LOW time1) (: 1 performing operations 7 ,, R) .x over two-digit numbers supplied in a sequential complementary code with low-order bits

and, the purpose of the invention is to enhance the functionality by performing an add operation,

FIG. 1 is a diagram of a computational cell; Fig. 2 is an example of the connection of three computational cells;

The computational cell (Fig, 1) contains a counter, the first - the ninth elements AND 2-10, the element OR 11, the shift register 12, the register of the multiplicand 13, the multiplier register 14, the adder 15, the trigger 16, the first - the sixth elements And -OR 17-22, first delays delay elements 23-27, operation result input 28, multiplier sign input 29, multiplier inverse sign input 30, first and second inputs 31 and 32 of the resolution resolution for additional code, multiplicative input 33, input 34 multipliers, input 35 of the partial product, input 36 of the term, input 37 of the resolution resolution, output 38 of the partial product reference, the output storage inverse sign multiplier, the sign of the multiplier output 40, first and second outputs 41 and 42 of the resolution conversion to do20

452

knives into elements and 27 and registers- 13 both multiplicand and multiplier

Counters carry out three (code P) and turn on sequentially, sleep counter first time, etc.

Single bit delay delays are used to transmit the bits of the phones.

Binary bit storage registers of multiplicable and compressed for recording and stored multipliers.

The operation of the elements of the moat 13 and 14 describes the transitions:

25

about -Q

H 3

about 1 ° B

thirty

01 10

eleven

1-1 1

oh oh

h. And with

Note on trigger triggers

, 0-3s number cell;

Completion code, output 43

states of elements 13 and 14 of the i-th cell; delay elements 2 ki; Qg QJ - 40 hold 26 and 27 (1-1)

l, output 44 of the start signal of the correction, output 45 of the multiplicand, outputs 46–47 of the senior and minor bits of the result of the cell.

An example of construction (Fig. 2) for three computational cells 48, - 48; allows you to connect these cells. The identity of all cells allows you to change the size of the data being processed by connecting additional circuits.

The multiplier and counter registers are two-digit, which makes it possible to construct two-digit cells and organize a bitwise output of the result of the operation with a delay of one cycle in relation to the bitwise input of operands.

The cells perform simultaneous multiplication and ayuzheniya (subtraction) operations.

A two-bit counter 1 serves to control the input of one-bit sfO.

71

five

 -

0

452

scissors into delay elements 26 and 27; and registers 13 and 14 of storage multiplier and multiplier.

The counters count up to three (code P) and are put into operation sequentially, first the counter of the first cell works, then the second one, and so on.

Single-bit delay elements 26 and 27 serve to sequentially transfer the multiplicative and multiplier bits.

The two-bit storage registers 13 and 14 of the multiplier and multiplier are used to record and store two-digit factors.

The operation of elements 26 and 27 and registers 13 and 14 is described by the transition table:

about -Q

H 3

about 1 ° B

ABOUT ,

9;

01 10

eleven

1-1 1

oh oh

h. And with

Q; Q .; Q;

Note, QQ is the trigger state of the counter 1 of the i-th computational cell;

the state of the memory elements of the registers 13 and 14 of the i-th cell; , - states of delay elements 26 and 27 of the i-th cell; Qg QJ - states of delay elements 26 and 27 (1-1) -th cells.

The trigger 16 of the multiplier sign, the elements 17 and 18, 2 and 11, are used to convert the additional code of the multiplier into direct when correcting the result of the operation.

Correction is multiplication

the value of the sign bit multiplier to the value of the multiplicand in the forward code. If the state of the trigger is 16,

then the register register 13 of the multiplicand is removed from the outputs of the AND-OR elements 17 and 1B; for Q 3, the additional code of the multiplicable register 13 is removed at the outputs of the AND-OR elements I7 and 18 (i.e., the additional code from the additional register code 13). During the correction, the multiplier sign is multiplied by the triggers 16 of each cell in series.

one

- A combinational seven-input adder 15 serves to form a partial sum of the i-th cell, which is delayed by one clock cycle by delay elements 23-25.

The four-bit shift register 12 serves to store the result of the operation and allows you to implement expressions of the form, Since the registers 12 of each cell are connected to, in series, the registers of all the computational cells comprise one 2n-bit shift register. This register is used to enter and store the 2n-bit result of the operation in the current operand processing cycle. To do this, it is necessary to connect the first cell exit 47 to the first cell input 28,

All memory elements are built in a two-step scheme with S (D) reset inputs R and Shared sync input.

When processing n digit numbers with the sign, the device should consist

1 p g

FROM J L CARDS.

The device works as follows.

Previously, all the elements of the device memory are set to the zero state.

A signal 1 is fed to the inputs 30, 31 and 37 of the first cell, and a signal O is fed to the input 32. The input 35 of the first cell is connected to the output 47 of the second cell. During n-1 cycles of operation of the device, at the inputs 29 and 30 of the first cell, signals of O and I will be present. Starting from the n-th cycle of operation of the device, inputs corresponding to the sign bit of the multiplier will be present at inputs 29 and 30 of the first cell.

During the first steps of the device operation, the inputs to the inputs 33 and 34 of the first cell are successively starting from the lowest bits, factors are received, and during the second pixels to the input 36 of the first cell they also arrive sequentially starting from. younger bits, the term. If a term has a length of 2p bits, then it arrives within 2p cycles.

The multiplier sign at the input 29 of the first cell is applied after calculating the n bits of the result of the operation and the form 454

It is controlled by an AND 9 element of one of the device cells. The specific element AND 9, the output of which is the signal for the start of the correction of the result of the operation, is determined by the width of the operands. So, when element And 9 of the second cell is used.

With the synchronization signal (not indicated in the diagram), the formation of a one-bit result of the operation presented in the additional code and removed from the output 47 of the first cell is carried out.

When entering operands and changing the states of the memory elements of the device.

. When implementing multiply-accumulate operations, the input 28 of the first cell is connected to the output 47 of the first cell, and the security module 38 of the last cell is connected to the input 36 of the first cell.

To obtain the actual product of the factors presented in the additional codes, it is necessary to multiply the sign bit of the multiplier by each bit of the multiplicand presented in the direct code. This is the correction of the pseudo-production in the device, with the correction of the pseudo-production starts from the moment the trigger 16 is set to the first character. From this moment, the sign bit of the multiplier, which, like its previous bits, arrives at the delay element 27, is multiplied sequentially by the transformed direct code. multiplicand.

The sequential conversion of the multiplicand code, starting with the least significant bit, is due to the successive propagation of the multiplier sign (starting with the nth cycle of the device operation) using the 16 sign multiplier trigger of each two-bit multiplication cell.

The product sign is determined by the value of the (2-1) -th bit of the result of the operation. The result of the operation is removed along with the sign from the output A7 of the first computational cell.

The term is fed to the input 36 of the first cell, including the sign bit. Addition is carried out in additional codes for all bits, including sign bits. To obtain the correct result of the operation, z K y + g in the additional code,

The following two cases should be excluded:

X, their y + g, I;

X y O, g O and | x y + gj 1.

In these cases, an overflow of the discharge grid occurs and the result

turns out to be wrong. I

In all other cases, the result of the operation is correct.

The cases listed above are eliminated by appropriately scaling the operands.

Claims (1)

Invention Formula The computational cell containing the multiplier 5 register is two elements AND, five delay elements, an adder, the output of the high and low bits of the sum of the adder are connected to the inputs of the first and second delay elements, the outputs of which are the outputs of the high and low bits of the cell result, output transferring the adder is connected to the input of the third delay element, the output of which is connected to the transfer input of the adder, characterized in that, in order to extend the functionality by performing the addition operation, in There are seven AND elements, a trigger, a counter, a multiplicable register, a shift register, six AND-OR elements and an OR element, the shift register shift input is the result of a cell operation, the output of the shift register is a partial cell output, the multiplier sign input the cells are connected to the information input of the trigger and to the first and second inputs of the first AND-OR element, the third input of which is the inverse sign of the cell multiplier. The first input of the conversion resolution to the additional cell code is connected with the fourth input of the first element AND-OR, with the first inputs of the first element AND and the second element AND-OR, the second input of the conversion resolution into the additional cell code is connected to the first input of the OR element, with the fifth input of the first AND-OR element and the second input of the second element I-ШШ, the input of the multiplicable cell is connected to the first inputs of the second, third and fourth elements AND, to the first input of the third AND-OR element and the first and second five 0 the inputs of the fourth section of the I-NLI, the input entry of the cell count is the first input of the fifth I-NPI element and is connected to the second input of the fifth H-OR element, the output of which is connected to the counting input of the counter, the inverse output j lepBoro of which is connected to : the third input of the fifth ILEI element, with the second input of the third AND element, with the first input of the fifth AND element, and the second and third inputs of the third AND-OR element, the output of which is connected to the first information input of the atope, direct output of the first bit yes the counter is connected to the sec the inputs of the second and fourth elements AND, the first inputs of the sixth 5th, seventh, eighth and ninth elements AND, with the fourth input of the third AND-OR element, the third input of the fourth AND-1SH element and the first input of the sixth AND-OR element, the inverse output of the second bit Yes, the counter is connected to the fourth input of the fifth element AND-OR, to the third input of the second element AND, to the second input of the seventh element AND and the fifth input to the third element AND-OR, the direct output of the second discharge of the counter is connected to the third inputs of the third and fourth and second In addition, by moves of the second, eighth, and ninth element AND, with the second input of the sixth element AND-OR, with the fourth input 5 of the fourth element AND-OR, and with the sixth and seventh inputs of the third element AND-OR, the multiplier input of the cell is connected to the third inputs the fifth, sixth and seventh elements And, with the eighth input of the third element and the third and fourth inputs of the sixth element AND -1 ShI, the inverse output of the trigger is connected to the third input of the second element AND-OR and is inverse five 0 0 five The output of the multiplier cell sign, the output of the flip-flop is the direct output of the multiplier cell sign and is connected to the fourth and fifth inputs of the second I-ШШ, the outputs of the second and third And elements are connected to the information input of the first and second bits of the register of multiplicable the inverse output of the first bit of which is connected to the sixth inputs 55 of the first and second AND-OR elements and the second input of the first AND element, the output of which is the first output of the resolution and conversion to the additional cell code, direct output /one iiepFsoT o register of the multiplicable state with the seventh input of the second and seventh and eighth inputs of the first I-Sh1I element and the second input of the OR element, the output of which is the second output of the resolution for converting to the additional cell code, the inverse output of the second digit of the multiplicable register connected to the third input the first element AND the eighth and ninth inputs of the second element AND-OR, the output of which is connected to the fifth and sixth inputs of the sixth element AND-OR, the output of which is connected to the BTopbJM information input of the adder, the direct output of the second About the bit of the register of the multiplicand is connected to the tenth and eleventh inputs of the second AND-OR element and the third input of the OR element, the output of the first AND-OR element is connected to the ninth input of the third AND-OR element, the tenth input of which is connected to the output of the fourth delay element and is the output of the cell multiplier 58 This and the fourth AND elements are connected respectively to the inputs of the fourth and fifth delay elements, the output of the fifth delay element is connected to the third input of the ninth AND element and is the output of the multiplicand. cells, outputs of the fifth and seventh elements AND are connected to the information input of the first and second bits of the multiplier register, the output of the first bit of which is connected to the fourth input of the ninth AND element, whose output is connected to the third information input of the adder, the fourth information input of which is connected to the output of the fourth element AND-OR, the fifth and sixth inputs of which are connected to the output of the second bit of the multiplier register, the inputs of the summand and partial product of the cell are the fifth and sixth information the inputs of the adder, the output of the eighth element And is the output of the signal of the beginning of the correction of the cell. 2