SU690477A1 - Digital device for modulo limiting - Google Patents

Description

(54) DIGITAL DEVICE OF NUMBER LIMITATION BY MODULE

the bits of the limiter register and the operand register are connected to the first and second inputs of the first character analysis block and the correction block 2, respectively.

A disadvantage of the known device is low speed.

The aim of the invention is to increase the speed of the device.

The goal is achieved by introducing a second code converter and a second character analysis unit, the inputs of which are connected respectively to the sign bits of the operand register and the result register, and the output of the second character analysis unit is connected to the control input of the second code converter through the first character analysis unit. , information inputs. Which are connected to the outputs of the register of the operand, and its outputs - with the second inputs of the adder.

FIG. 1 shows the block diagram of the device for limiting the number of the module; in fig. 2 - block program of the device.

The device contains a register of 1 operand, a register 2 of a delimiter, a register 3 of the result adder 4, the first code converter 5 the first character analysis block 6, a correction block 7, a group of AND 8 direct transfer codes, a group of AND 9 transmission codes with a shift to the left, a group elements. OR 10, element II, the second code converter 12, the second block 13 of the analysis of characters.

The device works as follows.

The Number Limit is entered in re. gister 3, it can also be the result of a previous operation. The limiter module is entered in register 2.

Numbers are added positive if their significant digits are in the zero state, and negative if they are in the unity state.

When the first clock pulse is applied, the number to be limited is rewritten from register 3 to register 1. To determine the largest module from among those prepared in registers I and 2, the contents of register 2 are fed to the input of the first term of adder 4 via the AND 8 group of direct transmissions of code converter 5 The input of the second term of the adder 4 through the code converter 12 receives the contents of register 1 in the forward code if it is negative or in the reverse code if it is positive. The character analysis in the case is carried out by the first block 6, it also selects the corresponding signals controlling the operation of the converters 5 and 12.

In the case of submission to the first or second inputs of the adder, the inverse (inverse) code of one of the addends to the transfer chain is young, and its bit 4 is from the correction block 7 in the tact cycle

690477

numbers comes in one. The analysis of the sign content of the register 1 is carried out by the second character analysis unit 13, which is additional to the first, character analysis unit 6.

J Both character analysis blocks are a set of AND, OR elements that generate control signals to control the 5 and 12 code converters.

The result of the subtraction of the modules of the contents of register 2 and perHCTpjf 1 is written through a group of elements AND 8 direct transmission of codes and a group elemet-gS OR 10 into register 3.

The new value of register 3 is analyzed by the sign of the result by the second block 13. If. the sign of the result is positive, then the module of the contents of register 2 (limiter) during subtraction was greater; if the sign is negative, then less.

In the first case, if the sign of the register contents is positive, in the next ZO cycle, the input of the first term is received O, the input of the second term is transmitted through the direct transfer gate of the converter 12, the contents of register 1 are received, i.e. the register is zeroed out 1, or the census (limited number) in the register 3.

In the second case, if the sign of the contents, register 3 is negative (Fig. 2), the next register inputs register 2 to the input of adder 4 via the direct transfer codes of the converter code 5 if the sign of the limited number of the operand register is positive or inversion the limiter 2 register with the addition of one from the correction block 11 to the input of the lower digit of the adder if the sign of the limiter is negative.

The input of the second term of the adder 4 is entered 0. The result from the adder is rewritten through the groups of elements AND 8 and OR 10 to register 3.

Thus, on the register 3, as a result of the restriction operation, the value of the limited number is fixed if its module is less than the limiter module, or if the limiter module is less than its module.

The speed of the proposed device is determined by the maximum operation cycle (Fig. 2) and is equal to T 2ir,

so where is the time of the short addition operation in the digital computer.

Claims (2)

To carry out this operation of the known device by dividing the limited number by the limiter and analyzing the result li, and then choosing the smaller one with the logical processing of the rezul) 1tat requires 4p time (where n is the number of bits of the device. Thus, the speed of the proposed the device is 2n times better than the known .. The equipment of the proposed device is almost equal to the equipment of the known device, selected as a prototype, and the functionality is wide The digital modular limiting device contains an operand register, a limiter register, a result register, an adder, a first code converter, a first character analysis block, a correction block, two groups of AND elements, an OR group of elements, and an AND element, the control input of which is connected to the output of the correction unit and the control inputs of the first group of elements AND, the information inputs of the first and second groups of elements AND are connected to the outputs of the adder, and their outputs through the group of elements OR They are not connected to the information inputs of the result register, the outputs of which are connected to the information inputs of the register of the operand, and the control inputs of the register of the operand and the result register are connected to the clock bus, the outputs of the register of the operand are connected via the first converter of the codes to the first inputs of the adder, and the second inputs of the first converter of codes connected to the output of the first block of character analysis and the low-order bit of the result register, the sign bits of the limiter register and the operand register are connected respectively Initially, the first and second inputs of the first block of character analysis and the correction unit, characterized in that, in order to increase speed, a second code converter and a second character analysis unit are introduced, the inputs of which are connected respectively to the sign bits of the operand register and the result register, and the output of the second character analysis block is connected via the first character analysis block to the control input of the second code converter, the information inputs of which are connected to the outputs of the operand register, and the outputs to the second ones in the moves of the adder. Sources of information taken into account in the examination. 1. USSR author's certificate number 472347, cl. About F 7/12, 1973. 2. USSR author's certificate number 551642, cl. G 06 F 7/39, 1975.  / / i V V A- Vv- , 0