SU744559A2 - Device for computing m-power polynomial values - Google Patents

Description

one

The invention relates to the field of digital computing and can be used in digital computers.

The closest in technical essence to the proposed is a device 1 for calculating the value of a polynomial of degree t, containing three shift registers, three AND elements, a transfer counter, an adder, a control unit. In this case, the first and second shift registers contain transfer chains. The outputs of the first and second registers through the first element And is connected to the input of the transfer counter. The first input of the adder is connected to the output of the transfer counter, the second input of the adder is connected to the output of the third shift register, and the output of the adder via the second element I connected. not connected to the input of the first shift register, the output of which is connected to the first input of the third And element, the output of which is connected to the input of the first register, the control inputs of the registers, adder, transfer counter, the first and second And elements, as well as the second input of the third And element corresponding outputs of the control unit.

This device has a simple design and allows the calculation of the values of elementary functions approximated by

polynomials with nonnegative coefficients without using standard programs for calculating elementary functions. In this case, the functions are calculated faster and savings are achieved in the memory cells of the digital computer in comparison with the calculation of the functions by software.

However, the known device cannot calculate the value of a polynomial with arbitrary coefficients, which makes it impossible to calculate with it such important practical functions as Y cosX, Y aTcigX, y arcshJ, F arcchX, etc., which are approximated polynomials with arbitrary coefficients.

The purpose of the additional invention is to expand the class of tasks due to the possibility of calculating the value

20 polynomials with arbitrary coefficients.

The goal is achieved by the fact that the device according to ed. St. No. 575648 entered the fourth element I, the first, second and third inputs of which are connected respectively to the output of the control unit, to the control input of the transfer counter and to the output of the first bit of the first shift register, and the output to the input of the first register

30 shift. FIG. Figure 1 shows a block diagram of an apparatus for calculating a polynomial value of a nth power. It contains a control unit 1, registers 2, 3, 4 shifts, a transfer counter 5, an adder 6, elements AND 7-10, an output 11 of the adding characteristic of the control unit, an output 12 of the clock of the control unit, an output 13 of the indication of shifting the transfer counter of the control unit, the outputs 14, 15 of the sign of the shift (respectively) of the first and second registers of the control unit; the inversion output 16 of the indication of the addition of the control unit, the argument input bus 17, the coefficient input bus 18 at the powers of the argument. FIG. 2 shows a timing diagram of the operation of the control unit in each cycle. Here 19 is the output of the fourth element And, if the partial value of the polynomial 20 is the output of the fourth element And, if the partial value of the polynomial Sj, 0. FIG. 3 shows a diagram of the change of the contents of the registers, fJtfe a - the arrangement of numbers in the initial position; b - arrangement of numbers after the first cycle; c is the arrangement of numbers during the circulation in the first cycle of the second cycle; g is the arrangement of numbers during the circulation in the (n-1) th cycle of the second cycle; d is the arrangement of numbers during the circulation in the nth cycle of the second cycle; e is the arrangement of numbers during the circulation in the (2л-1) th cycle of the second cycle. In addition, in FIG. 3 denotes: x, -j- is the binary digit of the argument X; a / - / - the binary number of the coefficient with the degree of argument Aji, 1, 2, ..., p-1, / 0, 1, 2, ..., t; bi-g is a binary digit of a l-digit number. The first register 2 and the second register 3 are (2n-1) -digit, and the third register 4 is l-bit, where l is the digit size of binary numbers, including one sign bit received in the device. The proposed device calculates the value of a polynomial with arbitrary coefficients AjXJ + + + ... + A; g + 4 according to Horner’s algorithm (scheme) r {((... ((A + + A ,,) X + + ... +4) + 4), where Y is the value of the polynomial; X is the degree of the argument; AJ is the / -th coefficient with the degree of the argument; Xs is the / -I degree of the argument; AjXi is the / -th member of the polynomial; / is the number of the coefficient with degree argument, polynomial member number, exponent of the argument; t is the degree of the polynomial; (t + 1) is the number of members of the polynomial; ... l (., lx + An, + + ...) partial value of the polynomial. / b / ( ; (0,1} -digits of the number 2 f2-. Argument 1Х, 2-,,.,., Where, 1} -titra t-ro The argument number is an l-bit binary number whose code is fixed before the fractional part. In both the known device and the proposed device, the argument X is a non-negative number, i.e., -, 0, and the value is signed bit: The coefficient of the degree of the argument, where the a / e {0,1} digit of the i-th bit of the / -th coefficient of the degree of the argument, is an l-bit binary number, in which the code is fixed before the fractional part. In contrast to the known device, in the proposed device, the coefficient AJ is an arbitrary number. If the coefficient is L;, 0, then it is represented in the forward code and the value of the sign bit is a 0. If the coefficient is L; Oh, it is presented in an additional code, and the value of the sign bit. First, in the second register 3, the input argument X is supplied with the argument X in the upper bits ahead. At the same time, in the third register 4, the input ratio 18 is applied to the coefficient Am in the lower bits ahead. The device is set up to calculate the value of the polynomial. FIG. 3, and the arrangement of numbers in the initial position ... is shown. The device operates cyclically (see the timing diagram of the control unit in each cycle shown in Fig. 2). Each cycle consists of (2l-1) cycles. In each clock cycle, the control input of the second register 3 of the shift receives the sign of the shift of the second register from the control unit 1. The sign of the shift of the second register is a sequence of (2l-1) pulses. Under, the effect of the sign of the shift of the second register in the second register 3 is the circulation of the argument in each cycle. In each cycle, the control input of the first register 2 of the shift receives the sign of the shift of the first register from the control unit 1. The sign of the shift of the first register is a sequence of 2n pulses. Under the effect of the sign of the shift of the first register in each clock cycle, the number in the first register 2 circulates, and in addition, in each cycle the number in the first register is shifted by one bit relative to the argument in the second register 3. As a result of the circulation of the number in the first register 2, and the circulation of the argument in the second register 3, the output of the first element And 7 produces digits of the bit products of these numbers. Under the influence of the clock pulses on the first element And 7, in each clock cycle, the digits of the bit products are transferred to the transfer counter 5. At the end of each clock cycle, the control input of the transfer counter 5 will indicate the shift of the transfer counter from the control unit. Under the influence of the sign of the shift of the transfer counter in the transfer counter 5, a shift is made by one bit of the number in it towards the lower digits. As a result, the output of the low-order bit of the transfer counter 5 at the end of each clock cycle appears, starting with the low-order, the next digit of the product of the number in the first register 2 and the argument in the second register 3. Thus, at the output of the least significant bit the transfer counter 5 will form within the first cycle, starting with the youngest, all {2 / d-1) digits of the product of the initial number, which is in the first register 2, and the "-discharge argument, which is in the second register 3. When performing the second half of the cycle, i.e. in n, (“+) , ..., (2га-1) clock ticks, the control unit 1 generates also signs of the floor, under the influence of which addition occurs in the sequential adder b, starting with the lower digits, two numbers, of which the first number is the highest n digits ( ) - the bit size is produced, and the second number is the next n - bit size factor with the degree of argument. Under the action of each attribute of the transfer, starting from the youngest, each digit of the sum from the output of the sequential adder b through the second element I 8 to the input of the first register 2 occurs. In addition, under the influence of each characteristic of the addition applied to the control input of the third register 4, a shift in the direction of the lower bits by one bit of the coefficient when the degree of the argument is stored in the third register 4, and in the released major bit is placed, starting with the youngest, the digit of the next, starting with the highest, the coefficient the one with the degree of argument that comes to the 18 input groups. Simultaneously with the sign of addition, the control unit produces an inversion of the characteristic of addition. Under the effect of inversion of the attribute of the addition to the third element AND 9, standing in the cyclic transfer chain of the first register 2, the cyclic transfer chain is opened at the moment when the input of the first register 2 under the influence of the folding feature is fed through the second element And 8 from the output of the series adder 6 digit amount. Thus, the replacement of the digits that come through the cyclic transfer chain to the input of the first register 2 is carried out with the digits that come from the output of the sequential adder b, i.e. the first register accumulates the result of the calculated polynomial value. After (m-fl) -fold repetition of the specified cycle in the first register 2, the result will be the calculated value of the polynomial. It is advisable to follow the operation of the device according to the chart of changing the contents of the registers shown in FIG. 3. After performing the first cycle in the nerve register. 2, the coefficient Am appears, in the second register 3 - without changing argument X, in the third register 4 - coefficient LT-1 (see Fig. 3.6). In the first cycle of the second cycle, the argument L is circulated in the second register 3 and the coefficient L ,,, is circulated in the first register 2 (see Fig. 3, s). As a result, at the output of the lower bit of the transfer counter 5, the figure of the younger (2n-2) -th bit of the product X-A-t will be generated. This figure will be o j-an-i. In the second cycle of the second cycle, at the output of the lower bit of the transfer counter 5, a digit will be formed of the next (2L-3) -th bit of the product HL of the second cycle at the output of the lower bit of the transfer counter 5 a digit of the nth digit of the X-Am product will be generated (see Fig. 3, d). In the nth cycle of the second cycle, the output of the sequential one from the chmator b will form the digit of the younger (n-1) -th bit of the n-digit number X-Am-Am-i. This figure will be. It arrives at the input of the first register 2, replacing with itself the digit of the lowest bit of the coefficient Л „,. Simultaneously, under the influence of the attribute of addition, a shift by one bit in the direction of the lower bits of the coefficient At-1 in the third regg: thr 4 and the reception of the digits ajij of the lower digit of the coefficient Am-z through tires 18 (see Fig. 3, d ) etc.

After the (2n-1) th cycle of the second cycle in the first register 2 is executed,

the number of ATX + AT-1, WHICH & o, b

, ...,, in the second register 3 - without changing the argument X, in the third register 4 - the coefficient Lt-2 (see Fig. 3, e).

After the third cycle is executed, the number in the first register 2 will be (), in the second register 3 there will be no change in the argument X, in the third register 4 - the coefficient AT-3, etc.

After repeating the cycle () once in iRev register 2, the calculated value of the polynomial will appear

U (... {(A „, X: + ... + A,} X + A,):

t

 2

in the second register 3, without changing the argument X, the third register 4 is free.

Consider the work of the fourth element And 10.

Since the coefficient at the degree of the argument Aj (0, 1, ..., / n) can be both positive and negative, the partial value of the polynomial

... l (+ + +

+ ..

It can also be both positive and negative.

In the / -M cycle, using the fourth element AND 10 at the end of each of the first (n-1) cycles, the value of the sign bit of the partial value of the polynomial Bj from the output of the first, counting from the input, bit of the first shift register 2, is fed to the input of the first shift register , which corresponds to the shift of the number Bj in the direct code, if Bj ,, and corresponds to the shift of the number Bj in the additional code, if.

If 5, -, 0, then in this cycle, using the fourth element AND 10 at the end of each of the first (p-1) ticks, the value of the sign bit from the output of the first, counting from the input, the bit of the first shift register 2, is fed to the input of the first shift register, which corresponds to the shift of the number 5, -in the forward code (see. Fig. 2, position 20). In this case, the multiplication of the argument X by the partial value of the polynomial Bj occurs in the direct code in the same way as in the known device.

If Bj.G, then in this cycle, using the fourth element And 10 at the end of each of the first (n-1) ticks, it is the sign bit from the output of the first one.

counting from the input, the bit of the first shift register is fed to the input of the first shift register, which corresponds to the shift of the number: Bj in the additional code (see Fig. 2, position

nineteen). In this case, unlike the well-known Device, the multiplication of the argument X by the partial value of the polynomial Bj occurs in the additional code without any transformations to the direct code, and the result X-Bj-.G is presented in the additional code.

The organic property of the adder is to provide the addition of arbitrary numbers if the negative terms are represented in the additional code. Therefore, in this cycle, from the output of the adder 6, through the second element I 8 to the input of the first register 2 of the shift, the new partial value of the polynomial Bj + i XBj- -Am-j-i comes forward. In this case, the number Sj + i can be both positive and negative, since the terms X-Bj and Am-j-i can be arbitrary numbers.

In the first cycle, therefore, the digits 6, of the initial value of the polynomial B are indicated as a ™ -g in FIG. 3, b, d

The use of a new, compared to the prototype element — the fourth element of AND — and new connections favorably distinguishes the proposed device by expanding the functionality consisting in providing the calculation of the value of a polynomial with arbitrary coefficients, which makes it possible to calculate using the proposed device additionally with respect to the known device important practice functions such as 7, sin J,, Y aTcigX, 7 arcshJ,

y arcch J, etc., which are approximated by polynomials with arbitrary coefficients.

Claims (2)

1. USSR author's certificate No. 575648, cl. G 06F 7/38, 1975 (prototype). - „affias:;. 1-4 I I 1-1: | --- P1 1-H -1 I J - I 1 I gp-1 gp-1 in 2P 1st 2.-U tact eleven in-f gp-1 Zn-1 Tt .2w 2/7 2 / - If (in-l} -u (p-1) th .nth --.- -k FIG. 2 Puz.3a, f, e Ri.2.3 z, d, e