SU932484A1 - Number comparing device - Google Patents

Description

one

The invention relates to automation and computing technology and can be used in the implementation of discrete automation equipment and computers.

A device for comparing binary numbers, containing an H-bit comparison node, is known, including registers of compared numbers, AND, OR-NOT elements and corresponding connections between elements l.

The drawback of the device is constructive complexity and limited (the functional possibilities associated with the impossibility of algebraic comparison of numbers.

Closest to the proposed technical solution is a device containing an AND-bit circuit of arithmetic comparison with input buses of compared numbers and outputs Greater and Less, and output elements And tz.

The disadvantage of this device lies in the limited functional possibilities associated with the impossibility of an algebraic comparison of numbers.

The purpose of the invention is to expand the functionality by algebraic comparison of numbers.

The goal is achieved by the fact that in a device for comparing numbers, containing an arithmetic comparison circuit, there are two AND elements, and the output of the More arithmetic comparison scheme is connected to the first input of the first And element,

15 output A smaller arithmetic comparison circuit is connected to the first input of the second element AND, the elements AND, OR, OR-NOT are introduced, and the inputs of the direct and inverse values

30 sign bits of the first number are connected to the first inputs of the third and fourth elements AND, respectively, the inputs of the direct and inverse values of the sign bit of the second number are connected to the second inputs of the fourth and third elements AND, respectively, the outputs of the fourth and third elements And are connected to the first inputs the first and second elements OR, respectively, the output of the first element AND is connected to the second input of the first element. OR, the output of the second element AND is connected to the second by the input of the second element OR, the inputs of the direct values of the sign bits of the numbers being compared, and the device comparison mode bus are connected to the inputs of the fifth AND element whose output is connected to the first inputs of the sixth and seventh And elements and to the first the input of the OR-NR element, the output of which is connected to the second inputs /: | of the first and second AND elements, the outputs of the third and fourth AND elements are connected to the second and third inputs of the OR-NO element, the More and Less outputs of the arithmetic comparison circuit connected to the second inputs of the sixth and seventh elements And, respectively, the outputs of the sixth and seventh elements And connected to the third inputs of the second and first elements OR, respectively. Functional diagram of the device shown in the drawing. The device contains input buses T-4 of the sign bits of the numbers, the elements And 5-11. element OR-NOT 12, elements tf LI 13 and 14, input More than 15 cf we compare, input Less than 16 comparison circuits, outputs 17 and 18 of the device, control input 19, circuit 20 arithmetic comparison. The device works as follows. The device allows you to compare algebraic numbers, represented as in the reverse or additional return codes (mode I - zero control signal at input 19), in the forward code (mode II - single control signal at input 19) 1 If the numbers are equal, then zero and more signals are formed at the Bolshe and Less outputs. A single signal is formed at the output of More, if A B, and at the output of Less, if A & 0 however, the signals at the outputs More and Less determine the final result of the comparison at outputs 17 and 18 only with the same signs of the numbers being compared. With different signs of the numbers being compared, the AND elements are blocked by zero signals from the outputs of the AND 11 and OR-NO 12 elements, and the comparison result G is determined only by the comparison circuit of sign bits, the outputs of the AND elements of which, respectively, are connected through the OR elements 13 and 14 to the outputs 17 and 18 devices. When comparing positive numbers, elements AND S, 10 are blocked by a zero signal from an output of element 11, and elements AND are unblocked by a single signal from an output of element OR NOT 12, and a single signal formed at the output More (Less) comparison circuit is transmitted through elements AND 7 (9) and OR 13 (14) at output 17 or 18. When comparing negative numbers presented in the reverse or additional reverse ko, groin (mode I), elements AND 8,10-zero signal from the output of element I. , And elements And 7.9 unlocked and, as in the comparison, put Yelnia numbers, unit signal formed at the output of over 15 (less than 16) comparing circuit is transmitted through the AND 7 (9) OR 13 and (14) on shiyu 17 (18). When comparing the negative numbers represented in the forward code (the G1 mode, elements AND 7, 9 are blocked by a zero signal from the output of the element ILI 12, and elements And 10.8 are unblocked by a single signal from the output of the element 11, and a single signal. Formed on. Output More (Less) comparison circuits are transmitted through the elements AND 10 (8) and OR 14 (13) to output 18 (17). 5.6 are zero signals that define zero signals on you device 17 (18). Implementing a device for analyzing the results of the comparison, consisting of a mixture of AND elements, two OR elements and one OR-NOT element with the proposed, structural link system, provides enhanced functionality due to

Claims (1)

Claim A device for comparing numbers containing an arithmetic comparison circuit, two And elements, the output of More arithmetic comparison circuit connected to the first input of the first And element, output Less arithmetic comparison circuit connected to the first input of the second And element, characterized in that, in order to expand the functional capabilities by providing algebraic comparison of numbers, the elements AND, OR, OR-HE are introduced into it, and the inputs of the direct and inverse values of the signed digit ί of the first number are connected to per. the inputs of the third and fourth elements AND, respectively, the inputs of the direct and inverse values of the sign discharge of the second number are connected to the second inputs of the fourth and third elements AND, respectively, the outputs of the fourth and third elements AND are connected to the first inputs of the first and second elements OR, respectively, the output of the first element AND connected to the second input of the first OR element, the output of the second element AND is connected to the second input of the second OR element, the inputs of direct values of the sign digits of the compared numbers and the bus The comparison device is connected to the inputs of the fifth * 0 element AND, the output of which is connected to the first inputs of the sixth and seventh elements AND and to the first input of the OR-HE element, the output of which is connected to the second inputs of the first and 15 second elements AND, the outputs of the third and fourth elements And connected to the second and third inputs of the OR-HE element, outputs More ”and Less” of the arithmetic comparison circuit are connected to the second inputs of the sixth and seventh elements AND, respectively, the outputs of the sixth and seventh elements AND are connected to the third inputs in orogo and the first OR element 25, respectively.