SU1499351A1 - Device for checking operability of computer units - Google Patents

Abstract

The invention relates to automation and computing and can be used to build the reliability of digital blocks. The purpose of the invention is to expand the field of application of the device. The device contains decoders 1,2, a group of 3 modulo-three adders, a block of 5 multiplication modulo three, an adder 6 modulo three, an adder 7 modulo two, switches 8.9, elements OR 15 - 24. The device allows to form at the output 13 devices, the modulo three products, the sum and the difference of the numbers supplied to the groups of 10.11 inputs of the first and second operands of the device. The operation mode of the device is controlled with the help of signals arriving at the inputs 4.14 of setting the device subtraction and multiplication modes, respectively. At the output 12 of the parity signal of the device, a parity signal of two numbers is formed. 2 Il.

Description

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The invention relates to automation and computing and can be used in the construction of reliable digital blocks.

The aim of the invention is to expand the field of application of the device.

Fig; 1 shows a functional diagram of the device; in fig. 2 shows a multiplication modulo three functional circuit.

The device contains decoders I and 2, a group of 3 modulo two adders, an input 4 specifies the device subtraction mode, a multiplication unit 5 of modulo three, an adder 6 modulo three, an adder 7 modulo two, switches 8 and 9, a group of 10 inputs of the first operand the device, the group Mi of the inputs of the second operand of the device, the output I 2 of the device parity, the output 13 test bits modulo three devices, the input 14 of the task — the device multiplication mode, the elements OR 15-24.

Block 5 multiplying modulo three (FIG. 2) contains AND-OR elements 25 and 26.

The device works as follows.

The device operates in two modes: calculating the remainder modulo three products of two numbers and adding the remainder modulo three sums or differences of two numbers.

The modes of operation of the device are set with the power of the signals at the inputs 4 and 14. In the multiplication mode, the inputs 4 and 1 4 of the device are respectively zero and single signals. In the subtraction control mode, the unit inputs 4 and 14 are respectively single and zero signals, and in the addition control mode, zero signals are output.

The elements OR 15 and 16 assembled the outputs of the first decoder I, corresponding to odd input codes with modulo three residues equal to one and two, respectively. The elements OR 17 and 18 collect the outputs of the first decoder 1, corresponding to the even input codes with weights modulo three, equal to one and two, respectively. By the same rule, the outputs of the second decoder 2 are combined on the elements OR 20-23.

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At the outputs of the multiplication unit 5 and the adder 6 modulo three, residues modulo three are formed, respectively, at multiplying and adding (subtracting) the operands entering the groups 10 and 11 of the device inputs.

The second switch 9 passes on the output of the control bits modulo three devices from the output of block 5 multiplying or compiler 6 modulo three depending on the value of the signal at input 14 specifying the multiplication mode of the device.

When monitoring the entry operation using a single signal at the input 4 of the device subtraction mode setting, the second operand on modulo two groups 3 is inverted. At the same time, the first switch 8 inverts the modulo three second operands.

Using an adder 7 modulo two, the output 12 of the device generates a parity signal for the number of units in both operands.

The device allows you to control operations on binary and binary-ten numbers, specified in codes 8, 4, 2 and 1.

Claims (1)

Invention Formula A device for controlling modulo arithmetic operations containing two decoders, ten OR elements, a modulo two adder and a modulo three adder, the group of information inputs of the first decoder is the group of inputs of the first operand of the device, the group of outputs of the first decoder corresponding to odd codes on its information inputs of the group, having a modulo three residue, equal to one, and a residue of three, equal to two, are connected to the input groups of the first and second elements OR, respectively, output groups The first decoder corresponding to the even codes at its information inputs of the group, having a modulo three residue, is one, and a modulo three residue, equal to two, are connected to the input groups of the third and fourth elements OR, respectively, the output of the first element OR is connected to the input the third element OR and the first input of the fifth OR element, the output of the second OR element is connected to the input of the fourth OR element and the second input of the fifth OR element, the output of which is connected to the first input of the modulo two, the outputs of the third the third and fourth elements OR are connected to the corresponding inputs of the first group of the modulo-three adder, groups of outputs of the second decoder corresponding to the odd codes on its information inputs of the group, having a modulo residue of three equal to one, and a residue of three equal to two, connected to the groups of inputs of the sixth and seventh elements OR, respectively, the group of outputs of the second decoder corresponding to the even codes on its information inputs of the group having a modulo three residue equal to one, and the remainder module three, equal to two, is connected to groups of inputs of the eighth and ninth elements OR, respectively, the output of the sixth element OR is connected to the corresponding input of the eighth element OR and the first input of the tenth element OR, the output of the seventh element OR is connected to the corresponding input of the ninth element OR and the second input of the tenth element OR, the output of which is connected to the second input of the modulo-2 adder, characterized in that, in order to expand the field of application of the device, a group of modulators of the adder two, multiply modulo three and two switches, with the first inputs of modulators two groups form a group of inputs of the second operand of the device, the outputs of modulators modulo two groups co. united with the group of information inputs of the second decoder, the outputs of the third and fourth elements OR are connected to the first group of information inputs of the multiplication unit modulo three, the outputs of the eighth and ninth elements OR are connected respectively to the first and second information inputs of the first group of the first switch, the outputs of nine of the first and the eighth elements OR are connected respectively with the first and second information inputs of the second group of the first switch, the group of outputs of which is connected to the second group of inputs with modulo three and with the second group of information inputs of the multiplication unit modulo three, the outputs of the multiplication unit modulo 5, three and modulo-three adders are connected respectively to the first and second informational inputs of the second switch, the output of which is the output of test bits for 0, the module has three devices, the output of the modulo two is the output of the device parity signal, the control input of the first switch is connected to the input of the device's eight mode setting, the control input of the second switch is connected to the input of the device's multiplication mode setting. F1 / G.2