SU1304019A1 - Device for modulo 2p-1 multiplying - Google Patents

Abstract

The invention relates to computing and technical cybernetics and can be used in devices for digital signal processing (in particular, images), as well as in coding systems, the principle of which is based on Galois field theory. The purpose of the invention is to reduce hardware costs. The goal is achieved by introducing the Sn-Parallel t (p + l) / 2j shift register, multiplexer group p, p-feedback register and synchronization unit, which allowed us to organize an analysis of GROUPS from one or three bits. Dow multiplier and consistently accumulate the amount in the feedback register. 4 il. with about 4

Description

113

The invention relates to computing and technical cybernetics and can be used in devices for digital signal processing (in particular, images), as well as in coding devices, the principle of which is based on the theory of finite rings.

The purpose of the invention is to reduce hardware costs.

t

FIG. 1 shows the device

for multiplication modulo 2 -1;. in fig. 2 - synchronization unit; in fig. 3 - result correction block; in fig. 4 is a timing diagram of the operation of the synchronization unit in a device for multiplying modulo 2 -1 in the case.

The device for multiplying modulo 2-1 (FIG.) Contains the shift register 1, the group of elements AND 2, - 2re adder 3, the storage register 4, the result correction unit 5 and the synchronization unit 6.

The synchronization unit 6 (FIG. 2) contains RS triggers 7,8 and 9j elements 10 AND and element I OR, element 12 NOT, elements 3e 14 OR, shift register 15, element 16 AND, element 17 OR clock input 18, input 19 logical Oh, input 20 logical 1, inputs 21,22 start and install the device, the first, second and third outputs 23,24 and 25 of block 6.

In the drawings, D is indicated with an index — information inputs of the shift registers and the storage register; Q - outputs of shift registers, storage register and direct inputs of RS-triiggers; E - inputs for resetting shift registers and storage registers; C — shift register synchronization inputs — and a storage register; DR - register shift enable input; SO - mode input; A, B are the inputs of the first and second components of adders .; S with the index - the outputs of the sum of adders; P and P - respectively, the input and output transfer of adders.,

Block 5 correction result (Fig. Contains the element 26 AND-NOT and the group of elements 27 I.

In the timing diagram (Fig. 4), 21,24,23,25, and f, RG 15 (, 11 (Q), T8 (Q), T9 (Q)) denote the plots of voltages at the corresponding points of the synchronization unit.

192

A device for multiplying modulo 2 -1 numbers is based on an algorithm as follows.

Let A 2 Ep., +2 -2ap. +. . .

. ..2a | + ae is the multiplicand, and bо. +

p-1

. a) a .l - ivirtu J inuc, ct and P-

+2 lp + ... + 2b, + hz - multiplier. We write the product A. In the form:

r-g

A-B A b o + 2b, A + 2Ch2A +. . . + 2 b.

xA + 2 b

p-1

one)

Thus, in order to multiply A by B, A is necessary. , where (, 1, ..., p-), multiply accordingly by b; with the subsequent summation of the formed partial works. Since b; can take only two values - O and 1, then the partial product of A; b will be zero when and A - with C-.

To reduce hardware costs when implementing this algorithm, it is convenient to create a product A.B, taking into account the equality 2.lmod. (2 -1), be represented as:

.Bo + 2GA-b, + 2GA-b +. ..

, ... ,, + 2 (A.Ъr,) ... lj. (2) I

A device for multiplying modulo numbers (2-1) works as follows.

Multiplier B, which is a number that does not exceed 2 -1 and is coded with a binary code, i.e. Binary-numbered binary number is supplied to the DO, ..., Dp. inputs of shift register 1. A multiplicative A, which is a number not exceeding 2 -1 and is encoded by a binary code, i.e. . represented in a binary number system by a p-bit binary number, is fed to the first inputs of the group of elements And 2, ..., 2n, the second inputs of which are combined and connected to the output of the shift register 1, thus passing the multiplicand A through the groups of elements And the bits of the multiplier B are controlled starting from the most significant bit. At the start of operation of the device or after turning on the power, to the input 22 of block 6, it is necessary to apply a pulse of the initial setup, which resets the (t + 1) -discharge, shift register 13 of block 6 to the zero state (in this variant), what. includes setting the RS-flip-flops 7 and 9 into the state of logical O. After filing the bits of the multiplier B and the multiplicand A on a 15

20

The corresponding inputs of the device in order to multiply them to the input 21 of block 6 must be given a Start impulse. Pulse Start from output 24 of block 6 is fed to the input SO of setting 5 of shift register mode I, and is also fed directly to the input of SO setting of shift register register 15 of block 6. The same pulse through element 17 OR with some delay set to Record mode in register 1, comes from output 23 of block 6 to clock input C of register 1, thereby recording the bits of the multiplier B to register 1, as well as through the element

14I, it arrives at the clock input C of the shift register 15, thereby producing a record of the unit in bit Q and zero in bit Qf + Q. register 15, since the input D of register 15 is connected to the bus of a single potential, and the inputs are connected to the bus of a zero potential. From the output of the Q register

15 a single potential is applied to the input of the RS RS-flip-flop 8, to the input of which the potential of the logical

from output Q, register 15. Thus, trigger 8 is set to the zero state and from it, through output 25 of block b, a reset signal is sent to register 4, which has zero activity level at output R. Impulse Start is also fed to input S of trigger 7 and , including it in the unit state, permits the passage of the inverse clock frequency through the element 10 AND, from the output of which it is fed to the first input of the element 14 OR.

c40

As a result, after the start of a pulse, the multiplier B is written to register 1, the register 1 5 is set to the state of one only

thirty

35

The rye are fed to the inputs B (,, ..., Bp.

BUT

17

tin

adder 3, the inputs A ,, ..., L

p-1 from which the logical register flow 4 is applied. To ensure the operation of adder 3 modulo (2 -1) its transfer output p is connected to transfer transfer input G, because a binary number with a weight of 2 appears at output p, and 2 lmod (2 -l).

In the case of a feed to the input R., transfer of the unit from the output P of transfer, one more transfer in principle cannot arise. This can be seen from the following: the maximum possible numbers, summed by such an adder, are 2-1, when added, the number 2 (2 -1) is obtained, represented in binary code by P units and one zero in the least significant bit 1 ... .10, and therefore, when transferring the highest unit to the lower order, one more transfer does not occur. As a result, after a time interval equal to the sum of the time of arrival of the transfer signal at the input p of adder 3 (first actuation), starting from the moment the terms are applied to the inputs of the adder 3, and the time of occurrence of the sum of these addends at the outputs S,. . . , Sp., Adder 3 (second actuation of adder 3), a binary code appears at the outputs Sg, ..., Sp., Adder 3 equal to the value of 5 total1 modulo 2 ° - two terms at the inputs of the adder 3

After the end of the impulse Start-through elements 10 AND, 14 OR, the positive input voltage of the inverted clock frequency arrives at the clock input of the register 15, the switch-register 15 goes to the state with the presence of the logical level 1 only at the output Q, which sets the trigger 8 in a single state

output QP, reset register 4, and also, e. thereby removing the reset mode from the ref. -5f

the inverse clock frequency is opened to the clock input C of the register 15. After the start of the impulse is triggered, the registers 1 and 15 are transferred to the Shift mode by feeding to

50

the horn 4, as well as sets the trigger 9 into a single state, thus opening the way for the forward clock frequency to pass through the elements 16 AND, 17 OR. to the output 23 of block 6. With the arrival of a positive forward voltage differential, the difference through the elements 16 AND, 17 OR arrives at clock inputs

their inputs are 80 logical potential from the bus to which they are supplied 50

ABOUT

the horn 4, as well as sets the trigger 9 into a single state, thus opening the way for the forward clock frequency to pass through the elements 16 AND, 17 OR. to the output 23 of block 6. With the arrival of a positive forward voltage differential, the difference through the elements 16 AND, 17 OR arrives at clock inputs

pulse start. Qp., Register output

I to the second inputs of the group of elements

And 2 ,, ..., 2p is given a bit of Lp, multiply of registers 4 and 1, producing by this

inhabitant B, and depending on him. recording information from the outputs of the adder

O or 1 values at the outputs of this 3 taking into account the cyclic shift on

groups of elements AND appear either

zeros or digits of the multiplicand A, which is one bit in register 4, which is a register with information

0

5 o

0

0

five

The rye are fed to the inputs B (,, ..., Bp.

BUT

17

tin

adder 3, the inputs A ,, ..., L

p-1 from which the logical register flow 4 is applied. To ensure the operation of adder 3 modulo (2 -1) its transfer output p is connected to transfer transfer input G, because a binary number with a weight of 2 appears at output p, and 2 lmod (2 -l).

In the case of a feed to the input R., transfer of the unit from the output P of transfer, one more transfer in principle cannot arise. This can be seen from the following: the maximum possible numbers, summed by such an adder, are 2-1, when added, the number 2 (2 -1) is obtained, represented in binary code by P units and one zero in the least significant bit 1 ... .10, and therefore, when transferring the highest unit to the lower order, one more transfer does not occur. As a result, after a time interval equal to the sum of the time of arrival of the transfer signal at the input p of adder 3 (first actuation), starting from the moment the terms are applied to the inputs of the adder 3, and the time of occurrence of the sum of these addends at the outputs S,. . . , Sp., Adder 3 (second actuation of adder 3), at the outputs Sg, ..., Sp., Adder 3 a binary code appears equal to 5 total1 modulo 2 ° - two terms on the inputs of adder 3.

After the end of the impulse Start-through elements 10 AND, 14 OR, a positive differential voltage of the inverted clock frequency arrives at the clock input of the register 15, the switch-register 15 goes to the state with the presence of the logic level 1 only at the output Q, which sets the trigger 8 into one condition.

f

the horn 4, as well as sets the trigger 9 into a single state, thus opening the way for the forward clock frequency to pass through the elements 16 AND, 17 OR. to the output 23 of block 6. With the arrival of a positive forward voltage differential, the difference through the elements 16 AND, 17 OR arrives at clock inputs

one bit into register 4, which is a register with the record information513040

positive differential to eliminate races; as well as a shift by one bit to the right of the code recorded in register 1. Thus,

the outputs Q, ..., Qp., register 4 contains the binary code corresponding to the product 2 A.cp, and at the output of Qp, register 1 there appears a bit of factor B to feed to the inputs Bd,. . . , BP, adder 3 is the binary code corresponding to the product ZF. BUT.

With the arrival of the next positive inverse clock differential, the register 15 of block 6 switches into a state with logical 1 only at output Q ,, and the adder 3 at this time produces a complication of code A coming from the outputs of elements 7 AND, and the code corresponding to - corresponding to the product 2A Lr. (coming from the outputs of the register 4 to the inputs AQ, ..., A p.1 of the adder 3. With the arrival of a positive forward frequency difference to the clock input of the register 4 from the output 23 of the block b to the register 4, binary code corresponding to the value 2 (А рр.2 + + 2A bp.,), And by the same differential in register 1, the code of the multiplier B is shifted again and the output of multiplier B appears at the output of register 1. Similarly, after switching register 15 to the state from logical 1 only Qti then with the arrival of a direct voltage drop in direct voltage in register 4, a binary code is written corresponding to a value of 2 (A b, + 2 (A b +.. + 2 (A bp, + 2 (A bp,) .. .)}., and at the output Qp-i of register 1, a discharge bd of the multiplier B appears. Upon receipt of a positive differential inverse clock frequency reg page 15 is switched to the state with the presence of only a unit at the output Q, through the setting member 13 or the trigger 9 to a logical thereby blocking the passage of the forward clock. The adder 3 at this time produces the addition of a binary code corresponding to the value A-b, and a binary code corresponding to the value. +2 A bm + ... Lp, bp + +2 (a bm.) 1-3 result at the outputs of the adder 3 Q

ABOUT

p-1

the binary code value appears,

five

5 0 0 5 0 5

0

five

96

corresponding to the value of the product

AB equal to:

A b In, + 2GA b, n- + Lp, +2 (L Lp.) .... This binary code from the outputs v,; ..., Qp., Of the adder 3 is fed to the inputs of block 5, which eliminates the ambiguity of the representation of modulo 2 zero.

If it is necessary to multiply two numbers, impulse must be set, then the binary codes of multiplicand and multiplier should be sent to the device inputs, and then impulse Start. The operation described is repeated.

Claims (1)

Invention Formula A device for multiplying modulo 2 -I (p-odd) containing an adder and a result correction block, the output of the sum of the adder connected to the input of the result correction block, the output of which is the output of the result of the device, in order to reduce hardware costs , a shift register, a group of multiplexers, a storage register, and a synchronization unit are entered into it, with the i-th information input of the shift register (where, l ... t-I; t is input (p-2i -) - ro bit, device multiplier, the t-th information input of the shift register is the input of the zero multiplier of the device multiplier, j-th information input of the shift register (where, t + 2, ... , t-1) is the input of the p-2 (jt-1) -2j bit of the device multiplier, the 2 th information input of the shift register is connected to the input of the zero bit of the device multiplier the kth information input of the shift register (where k ( 2t + l) f X (2t + 2) ... (3t-l) is the input of the p-2 (k- (2t-l) -1) J bit of the device multiplier, the outputs (tl) -ro and ( The 2t--1) and (3t-l) -ro bits of the shift register are connected, respectively. but with the first, second, and third control inputs of the SX group multiplexers (where S is 1,2,3 ... p), the first information input of the S-ro group multiplexer is connected to the device logical zero bus, the second information input of the first multiplexer the group is the input of the (p − 1) th inverse bit of the multiplicand device 713 The second information input q.-ro of the group multiplexer (where q 2.3 ... p) is the input of the (q-2) -ro inverse spread of the multiplicable device, the third information input S-ro of the group multiplexer is the input ( 3-1) th device multiplier bit, the fourth information input S-ro of the group multiplexer is the input (Sl) -ro inverse of the multiplicable device, the fifth information input S-ro of the group multiplexer is connected to the third information input S -ro group multiplexer, the sixth information input of which is connected to the fourth inf the S-ro input multiplexer of the group multiplexer; the seventh information input of the first group multiplexer is connected to the input (pl) -ro bit of the multiplicable device; the seventh information input of the q-ro multiplexer group is connected to the input of the q-2 -ro bit multiply 1 device, the eighth information input of the group multiplexer S-ro is connected to the first input of the group multiplexer S-ro and the shift register reset enable input, the output of the group multiplexer S-ro is connected to the first information input of the S-ro bit1 "1mator, second information input S -ro bit which is connected to the output of the B-th time- " five 40 5 o 0 five 0 198 p yes of the storage register, the information input of the n-th bit of which (where, 2,3 ... p-2) is connected to the output of the sum of the (r + 2) th digit of the adder, the output of the first and second digits of the sum of which are connected respectively, with the information inputs (pl) -ro and p-th bits of the storage register, the transfer output of the adder is connected to the transfer input of the adder, the device start input is the start input of the synchronization unit, the setup input of which is the device installation input, the first output of the synchronization unit connected to the reset input of multiplexers and synchronization inputs of the shift and storage registers, the shift register enable input of the shift register is connected to the second output of the synchronization unit, the third output of which is connected to the reset input of the storage register, the result correction block contains the AND-N element and the group of elements AND, the 1st input of the element NAND (where 1 1,2 ... p) is the input of the 1st bit of the result correction block and is connected to the first input of the 1st AND element of the group, the second input of which is connected to the output of the NAND element, outputs elements and groups are given by the outputs of the correction block AI results. Jofj i nineteen TO Order 1678 Circulation 673 Subscription VNIIPI USSR State Committee . for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 15 i 4i R