SU383050A1 - DEVICE FOR DECODING HAMMING CODE - Google Patents

Description

one

The invention relates to the field of immersive technology and can be used in digital computers processing information arriving via communication lines.

A known device for decoding a Hamming code, comprising a receiving register, convolution schemes, an error correction scheme, and communication circuits, has a number of significant limitations. For example, for long messages, the use of this device leads to almost insurmountable difficulties due to large loads on the elements.

The purpose of the invention is to build a high-speed device for decoding a Hamming code that performs a decoding operation for docks of arbitrary length, while economically using the equipment.

For this, the proposed device decodes with a speed of several bits (one group) in one clock of two-phase clocking, while the equipment is economically used in comparison with the device of parallel combinational decoding.

The proposed device uses the principle of combining information processing steps in which several consecutive groups of bits are simultaneously processed. In order to implement the decoding algorithm in the form of step-by-step combination processing, the rule of decoding the Hammipg code is configured in the following ways; The result of decoding (a set of check bits) of a message of arbitrary length is the sum modulo 2 (convolution) of the number of message bits that are equal to one.

The consequence of such a formulation is the following: to decode a group Of several bits, it is necessary to collapse (sum modulo 2) the corresponding bit numbers in the group. In this case, each group of bits starts with a bit, the number of which in binary form is written as

... 00, where the number of zeros is defined as, where the number of bits in the group and g / g are arbitrary values: either O or 1, then the numbers of the bits in the group will be written as follows:

y „y„ 1r / j 00O,

 001,

g / "U" -1g /, 11, ... 1,

or in other words, the upper parts of the bit numbers are the same for all bits of the group.

Instead of a general convolution of numbers, we will consider discharges of a higher part of numbers of discharges and a convolution of the younger part of GG3,

measures of bits, taking into account the values of bits in the group. If the number of units in the group is odd, then the result of convolving the highest parts

U „U, g-1i /,

If the number of units in the group is even, then the result of convolution of the higher parts

00 .... 00

To obtain the convolution of the lower parts of the bit numbers, we denote the value of the bits in the group as

, a2 "-2,. . . “And“ 01 rewrite the bit numbers in binary form

;"P. . .. P, 1110,. . . "00 .. ..01," 00. ..00.

Denote the result of the convolution of the younger part of the numbers of bits Vj, where / is the number of the bits of the result.

Then

00 ... 00 - / (.00... 00, COO... 01, "00 ... And,

-Oo ... 101 ..) SB. . . 01 / (... 01, "00 ... 10, W-YO ... and

"00 ... but ...)

00 ... 10 / (XQQ ... 10. "00... 100, JAOO.. 101,

"00 ... at)

where I is the convolution function, Xi is the discharge of the result of the convolution of the minor part for the preceding groups.

na f-ig. 1 is a block diagram of a device for decoding a Hamming code; in fig. 2 is a time diagram of the operation of the device.

 The decoding structure consists of receiving register 1, accepting it from Od via input 2 words that make up the message, and an extended one zero bit, the value of which is zero so that in the first group selected from the message to get bits from to By measures

 , 00 .... 00, 00. ... 01, 00 ... .10, etc.,

.. where the first coitrol bit is the bit number 00 ... 01; the device also contains a counter 3 containing the most significant bit of the bit number in the message, i.e., representing the group number selected from the message through the decoder 4 to the register, 5; the first circuit of light 6, which implements the convolution of the higher part of the bit numbers, with the first input through register 7, which is an intermediate buffer for the counter, is connected to the counter 3. The output of the second convolution circuit 8 is connected to the second input of the circuit. the number of units in the group of bits chosen for the register -5, with the third input of which through the register I is 4

the daily buffer m for the result of overthrowing the higher part of the message bit number, the output of the first convolution circuit is connected; the value of the bits at the output of the first convolution scheme 6 either represents the old register I if the output of the second convolution scheme. We conclude that the selected group of bits has an even number of units, or a new value (mod 2) of the counter and

the old value of the register I representing the previous result of convolution; the third convolution scheme 10, which implements the convolution of the younger parts of the bit numbers, with the first input of which is connected to the output of the register 5,

on the latter there is a group of bits selected by the decoder, with the second input of which register 11 is connected, which is an intermediate buffer for the result of convolution of the lower part of the digit number; value

the output bits of the third convolution scheme represents the described function Uj of the output of the third convolution scheme 10 and the first convolution scheme 6 connected to the output 12 of the decoding device.

The dynamics of the operation of the circuit is shown in the time diagram of the operation of the decoding device of the Hamming code (see Fig. 2), where the numbers of the graphs correspond to the numbers of the blocks on f: ig. 1, two-phase clocking signals are shown and time points ti, tz -.- tis- are noted. For specificity, the following device parameters are used: message length not more than 100 bits, number of check bits not more than 7, decoding rate is 4 bits per one measure. In this case, the cash register 3, registers 7, 9 are five bits long. Register 5 has a corresponding length of four bits. Register 11 is two bits long. At the initial time / counter 3 selects the first 4 bits for register 5, respectively, the contents of counter 00000, at time ta the contents of counter 3 are transferred to register 7 and at the same time become equal to 00001. At time / s, the output of the convolution scheme 8 is equal to one if the convolution (mod 2 sum) of register bits 5 is equal to one, at the same time the output at the output of the convolution scheme will be determined by the following rule:

U, f (x ,, j. ,, a,},

and 3 - I 2 -z)

where L / i, f / 2 are the output bits of the circuit 10;

K o, az, register bit 5;

f - convolution function.

At time 4, the second four digits from the message will be set on register 5, i.e. bits 5 through 8, and the output of the convolution scheme will be 6

there is a convolution (sum mod 2) 7 and 5 registers, if the output state of the convolution scheme 8 is "1, if the output state of scheme 8 is" O, then the output of the convolution circuit. 6 is equal to the contents of register 9. At the time / 4, the state of counter 3 is equal to 00010, the state of register 7 is equal to 00001, and the state of register 9 is equal to the state of output of convolution circuit 6 at the previous moment. Thus, at time 5, the result of processing the first four bits is stored in registers 9 and 10 and the output of the convolution scheme 8 is set to convolution (sum over niod 2) of the second four and at register 7 the number of these fours. Then everything repeats in the same way until the last four digits of the message pass through welding circuit 6 and the result of decoding the message at this moment is on registers 9 and //.

Subject invention

A device for decoding a Hamming code, containing a receive register, circuits

convolutions, buffer registers and a descrambler, characterized in that, in order to increase the speed of the device, a counter is entered in it, the output of which is connected to the first input of the decoder and through the first buffer register to the first input of the first convolution scheme, the second input of which is connected to the second convolution circuit, and with the third input through the second buffer register - the output of the first convolution scheme, the output of the receiving register is connected to the second input of the decoder, the output of which through the third buffer register is connected to the input of the second circuit ki and the first input of the third convolution circuit, wherein the second input via a fourth buffer register connected to its output, the outputs of the first and third convolution circuits connected to the output device.

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